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121 lines
4.1 KiB
VHDL

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-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name: axis_demux - imp
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Library xpm;
--use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_demux is
generic(
DWIDTH : integer := 512
);
port (
aclk : in STD_LOGIC;
aresetn : in std_logic;
aselect : in std_logic;
s_axis_tdata : in std_logic_vector(DWIDTH-1 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
m0_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
m0_axis_tvalid : out std_logic;
m0_axis_tready : in std_logic;
m1_axis_tdata : out std_logic_vector(DWIDTH-1 downto 0);
m1_axis_tvalid : out std_logic;
m1_axis_tready : in std_logic
);
end axis_demux;
architecture imp of axis_demux is
-- ATTRIBUTE X_INTERFACE_INFO : STRING;
-- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-- ATTRIBUTE X_INTERFACE_INFO of aclk: SIGNAL is "xilinx.com:signal:clock:1.0 aclk CLK";
-- -- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
-- -- Most of these parameters are optional. However, when using AXI, at least one clock must be associated to the AXI interface.
-- -- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple interfaces, separate each name by ':'
-- -- Use the port name for ASSOCIATED_RESET.
-- -- Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
-- ATTRIBUTE X_INTERFACE_INFO of aresetn: SIGNAL is "xilinx.com:signal:reset:1.0 aresetn RST";
-- ATTRIBUTE X_INTERFACE_PARAMETER of aresetn: SIGNAL is "POLARITY ACTIVE_LOW";
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TDATA";
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TVALID";
-- ATTRIBUTE X_INTERFACE_INFO of s0_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s0_axis TREADY";
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TDATA";
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TVALID";
-- ATTRIBUTE X_INTERFACE_INFO of s1_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 s1_axis TREADY";
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TDATA";
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TVALID";
-- ATTRIBUTE X_INTERFACE_INFO of m_axis_tready : SIGNAL is "xilinx.com:interface:axis:1.0 m_axis TREADY";
-- ATTRIBUTE X_INTERFACE_PARAMETER of aclk: SIGNAL is "ASSOCIATED_BUSIF s0_axis : s1_axis : m_axis, ASSOCIATED_RESET aresetn";
--signal aselect_int : std_logic;
begin
-- i_xpm_cdc_single_0 : xpm_cdc_single
-- generic map(
-- DEST_SYNC_FF => 4,
-- INIT_SYNC_FF => 0,
-- SIM_ASSERT_CHK => 0,
-- SRC_INPUT_REG => 0
-- )
-- port map(
-- dest_out => aselect_int,
-- dest_clk => aclk,
-- src_clk => '0',
-- src_in => aselect
-- );
m0_axis_tdata <= s_axis_tdata;
m1_axis_tdata <= s_axis_tdata;
m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0';
m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0';
s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready;
end imp;