moving repo from git to local repo
This commit is contained in:
@@ -0,0 +1,105 @@
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// ***************************************************************************
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||||
// ***************************************************************************
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||||
// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
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||||
//
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||||
// ***************************************************************************
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||||
// ***************************************************************************
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||||
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||||
`timescale 1ns/100ps
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||||
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||||
//
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||||
// A 4-wire to 3-wire SPI converter, supporting maximum 8 slaves.
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||||
// The expected transfer format is defined in ADI_SPI technical specification
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||||
// (https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf)
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//
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||||
// 16 bit instruction followed by N x 8 bits of data; the MSB bit of the
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// instruction defines the direction of the SDIO during data transfer. (READ
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||||
// is 1 and WRITE is 0)
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//
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||||
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||||
module ad_3w_spi #(
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||||
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parameter NUM_OF_SLAVES = 8
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) (
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input [NUM_OF_SLAVES-1:0] spi_csn,
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input spi_clk,
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input spi_mosi,
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output spi_miso,
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inout spi_sdio,
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output spi_dir
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);
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// internal registers
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reg [ 5:0] spi_count = 'd0;
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reg spi_rd_wr_n = 'd0;
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reg spi_enable = 'd0;
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// internal signals
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wire spi_csn_s;
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wire spi_enable_s;
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// check on rising edge and change on falling edge
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assign spi_csn_s = & spi_csn;
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assign spi_dir = ~spi_enable_s;
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assign spi_enable_s = spi_enable & ~spi_csn_s;
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always @(posedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_count <= 6'd0;
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spi_rd_wr_n <= 1'd0;
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end else begin
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spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
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if (spi_count == 6'd0) begin
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spi_rd_wr_n <= spi_mosi;
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end
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end
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end
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always @(negedge spi_clk or posedge spi_csn_s) begin
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if (spi_csn_s == 1'b1) begin
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spi_enable <= 1'b0;
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end else begin
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if (spi_count == 6'd16) begin
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spi_enable <= spi_rd_wr_n;
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end
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end
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end
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// io butter
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assign spi_miso = spi_sdio;
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assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
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endmodule
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@@ -0,0 +1,56 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
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`timescale 1ns/100ps
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module ad_iobuf #(
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parameter DATA_WIDTH = 1
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) (
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input [(DATA_WIDTH-1):0] dio_t,
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input [(DATA_WIDTH-1):0] dio_i,
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output [(DATA_WIDTH-1):0] dio_o,
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inout [(DATA_WIDTH-1):0] dio_p
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);
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genvar n;
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generate
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
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assign dio_o[n] = dio_p[n];
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assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
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end
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endgenerate
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endmodule
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@@ -0,0 +1,65 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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Library xpm;
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use xpm.vcomponents.all;
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||||
-- Uncomment the following library declaration if using
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||||
-- arithmetic functions with Signed or Unsigned values
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||||
--use IEEE.NUMERIC_STD.ALL;
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||||
|
||||
-- Uncomment the following library declaration if instantiating
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||||
-- any Xilinx leaf cells in this code.
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||||
--library UNISIM;
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||||
--use UNISIM.VComponents.all;
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||||
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||||
entity axis_mux_128b is
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port (
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||||
aclk : in STD_LOGIC;
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aresetn : in std_logic;
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||||
aselect : in std_logic_vector(1 downto 0);
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||||
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s0_axis_tdata : in std_logic_vector(127 downto 0);
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s0_axis_tvalid : in std_logic;
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||||
s0_axis_tready : out std_logic;
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||||
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||||
s1_axis_tdata : in std_logic_vector(127 downto 0);
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||||
s1_axis_tvalid : in std_logic;
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||||
s1_axis_tready : out std_logic;
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||||
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||||
s2_axis_tdata : in std_logic_vector(127 downto 0);
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s2_axis_tvalid : in std_logic;
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s2_axis_tready : out std_logic;
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||||
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||||
s3_axis_tdata : in std_logic_vector(127 downto 0);
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s3_axis_tvalid : in std_logic;
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s3_axis_tready : out std_logic;
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||||
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m_axis_tdata : out std_logic_vector(127 downto 0);
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m_axis_tvalid : out std_logic;
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m_axis_tready : in std_logic
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||||
);
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end entity axis_mux_128b;
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architecture imp of axis_mux_128b is
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begin
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m_axis_tdata <= s0_axis_tdata when aselect = "00" else
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s1_axis_tdata when aselect = "01" else
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s2_axis_tdata when aselect = "10" else
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s3_axis_tdata;
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m_axis_tvalid <= s0_axis_tvalid when aselect = "00" else
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s1_axis_tvalid when aselect = "01" else
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s2_axis_tvalid when aselect = "10" else
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s3_axis_tvalid;
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s0_axis_tready <= m_axis_tready when aselect = "00" else '0';
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s1_axis_tready <= m_axis_tready when aselect = "01" else '0';
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s2_axis_tready <= m_axis_tready when aselect = "10" else '0';
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s3_axis_tready <= m_axis_tready when aselect = "11" else '0';
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end imp;
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@@ -0,0 +1,46 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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Library xpm;
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use xpm.vcomponents.all;
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||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
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||||
-- any Xilinx leaf cells in this code.
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||||
--library UNISIM;
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--use UNISIM.VComponents.all;
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entity axis_mux_s2_128b is
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port (
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aclk : in STD_LOGIC;
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aresetn : in std_logic;
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||||
aselect : in std_logic;
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||||
|
||||
s0_axis_tdata : in std_logic_vector(127 downto 0);
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||||
s0_axis_tvalid : in std_logic;
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||||
s0_axis_tready : out std_logic;
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||||
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||||
s1_axis_tdata : in std_logic_vector(127 downto 0);
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||||
s1_axis_tvalid : in std_logic;
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||||
s1_axis_tready : out std_logic;
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||||
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||||
m_axis_tdata : out std_logic_vector(127 downto 0);
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||||
m_axis_tvalid : out std_logic;
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||||
m_axis_tready : in std_logic
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||||
);
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||||
end entity axis_mux_s2_128b;
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||||
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||||
architecture imp of axis_mux_s2_128b is
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begin
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||||
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m_axis_tdata <= s0_axis_tdata when aselect = '0' else s1_axis_tdata;
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m_axis_tvalid <= s0_axis_tvalid when aselect = '0' else s1_axis_tvalid;
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||||
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||||
s0_axis_tready <= m_axis_tready when aselect = '0' else '0';
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||||
s1_axis_tready <= m_axis_tready when aselect = '1' else '0';
|
||||
|
||||
end imp;
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||||
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||||
@@ -0,0 +1,280 @@
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library ieee;
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||||
use ieee.std_logic_1164.all;
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--use ieee.numeric_std.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity qsfp1_capture_intfc is
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port (
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qsfp1_capture_aclk_in : in std_logic;
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qsfp1_capture_aresetn_in : in std_logic;
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||||
qsfp1_capture_tdata_240b_in : in std_logic_vector(239 downto 0);
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||||
qsfp1_capture_tvalid_240b_in : in std_logic;
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qsfp1_capture_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
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qsfp1_capture_iq_240b_to_512b_overflow_cnt_out : out std_logic_vector( 31 downto 0);
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qsfp1_capture_tvalid_512b_cnt_out : out std_logic_vector( 31 downto 0);
|
||||
|
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qsfp1_capture_rx_data_ready_out : out std_logic;
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||||
qsfp1_capture_rx_data_ready_cnt_out : out std_logic_vector( 31 downto 0);
|
||||
|
||||
tx_device_clk_in : in std_logic;
|
||||
tx_device_clk_aresetn_in : in std_logic;
|
||||
tx_fifo_tdata_128b_out : out std_logic_vector(127 downto 0);
|
||||
tx_fifo_tvalid_128b_out : out std_logic;
|
||||
tx_fifo_tready_128b_in : in std_logic;
|
||||
qsfp1_tx_fifo_tvalid_128b_cnt_out : out std_logic_vector( 31 downto 0);
|
||||
qsfp1_tx_fifo_128_aempty_cnt_out : out std_logic_vector( 31 downto 0);
|
||||
|
||||
qsfp1_capture_en_n_in : in std_logic;
|
||||
qsfp1_capture_rst_in : in std_logic;
|
||||
cnt_reset_in : in std_logic
|
||||
);
|
||||
end entity qsfp1_capture_intfc;
|
||||
|
||||
architecture arch_imp of qsfp1_capture_intfc is
|
||||
|
||||
signal qsfp1_rx_data_ready : std_logic;
|
||||
signal qsfp1_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp1_prog_full_240b : std_logic;
|
||||
signal qsfp1_afull_240b : std_logic;
|
||||
signal qsfp1_aempty_240b : std_logic;
|
||||
|
||||
signal qsfp1_rx_data_ready_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp1_iq_240b_to_512b_overflow : std_logic;
|
||||
signal qsfp1_iq_240b_to_512b_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp1_tdata_512b : std_logic_vector(511 downto 0);
|
||||
signal qsfp1_tvalid_512b : std_logic;
|
||||
signal qsfp1_tready_512b : std_logic;
|
||||
|
||||
signal qsfp1_tdata_512b_pipe : std_logic_vector(511 downto 0);
|
||||
signal qsfp1_tvalid_512b_pipe : std_logic;
|
||||
|
||||
signal qsfp1_almost_empty_512b_pipe : std_logic;
|
||||
signal qsfp1_almost_empty_512b_pipe_r : std_logic := '1';
|
||||
signal qsfp1_fifo_aempty_512b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal axis_dwidth_converter_512b_to_128b_tdata_128 : std_logic_vector(127 downto 0);
|
||||
signal axis_dwidth_converter_512b_to_128b_tvalid_128 : std_logic;
|
||||
signal axis_dwidth_converter_512b_to_128b_tready : std_logic;
|
||||
|
||||
signal qsfp1_tready_128b : std_logic;
|
||||
|
||||
signal tx_fifo_tvalid_128b : std_logic;
|
||||
signal tx_fifo_128_aempty : std_logic;
|
||||
signal tx_fifo_128_aempty_r : std_logic := '0';
|
||||
signal tx_fifo_128_aempty_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tx_fifo_tvalid_128b_ena : std_logic;
|
||||
signal tx_fifo_tready_128b_ena : std_logic;
|
||||
|
||||
signal tx_pre_buff_rdy_r : std_logic := '0';
|
||||
|
||||
signal tx_fifo_128b_tvalid_128b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tx_fifo_128_prog_full : std_logic;
|
||||
|
||||
signal qsfp1_tvalid_512b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tx_device_clk_aresetn : std_logic;
|
||||
signal qsfp1_capture_aresetn : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
qsfp1_capture_rx_data_ready_out <= qsfp1_rx_data_ready;
|
||||
qsfp1_capture_rx_data_ready_cnt_out <= qsfp1_rx_data_ready_cnt_r;
|
||||
|
||||
qsfp1_capture_tvalid_240b_cnt_out <= qsfp1_tvalid_240b_cnt_r;
|
||||
qsfp1_capture_iq_240b_to_512b_overflow_cnt_out <= qsfp1_iq_240b_to_512b_overflow_cnt_r;
|
||||
qsfp1_tx_fifo_128_aempty_cnt_out <= tx_fifo_128_aempty_cnt_r;
|
||||
qsfp1_tx_fifo_tvalid_128b_cnt_out <= tx_fifo_128b_tvalid_128b_cnt_r;
|
||||
qsfp1_capture_tvalid_512b_cnt_out <= qsfp1_tvalid_512b_cnt_r;
|
||||
|
||||
tx_device_clk_aresetn <= '0' when tx_device_clk_aresetn_in = '0' or qsfp1_capture_rst_in = '1' else '1';
|
||||
qsfp1_capture_aresetn <= '0' when qsfp1_capture_aresetn_in = '0' or qsfp1_capture_rst_in = '1' else '1';
|
||||
|
||||
-- ***240 to 128 converter
|
||||
i_iq_240b_to_512b : entity work.iq_240b_to_512b
|
||||
port map (
|
||||
aclk => qsfp1_capture_aclk_in, -- in
|
||||
aresetn => qsfp1_capture_aresetn, -- in
|
||||
s_axis_tdata => qsfp1_capture_tdata_240b_in, -- in
|
||||
s_axis_tvalid => qsfp1_capture_tvalid_240b_in, -- in
|
||||
prog_full => qsfp1_prog_full_240b, -- out
|
||||
almost_full => qsfp1_afull_240b, --out
|
||||
|
||||
m_axis_tdata => qsfp1_tdata_512b, -- out
|
||||
m_axis_tvalid => qsfp1_tvalid_512b, -- out
|
||||
m_axis_tready => qsfp1_tready_512b, -- in
|
||||
almost_empty => qsfp1_aempty_240b, -- out
|
||||
overflow => qsfp1_iq_240b_to_512b_overflow, -- out
|
||||
sel_12b_16bn => '0' -- 16-bit samples -- in
|
||||
);
|
||||
|
||||
qsfp1_rx_data_ready <= not qsfp1_prog_full_240b;
|
||||
|
||||
process(qsfp1_capture_aclk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp1_capture_aclk_in)) then
|
||||
|
||||
if (qsfp1_capture_aresetn = '0' or cnt_reset_in = '1') then
|
||||
qsfp1_tvalid_240b_cnt_r <= (others => '0');
|
||||
elsif (qsfp1_capture_tvalid_240b_in = '1') then
|
||||
qsfp1_tvalid_240b_cnt_r <= qsfp1_tvalid_240b_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (qsfp1_capture_aresetn = '0' or cnt_reset_in = '1') then
|
||||
qsfp1_rx_data_ready_cnt_r <= (others => '0');
|
||||
elsif (qsfp1_rx_data_ready = '0') then
|
||||
qsfp1_rx_data_ready_cnt_r <= qsfp1_rx_data_ready_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (qsfp1_capture_aresetn = '0' or cnt_reset_in = '1') then
|
||||
qsfp1_iq_240b_to_512b_overflow_cnt_r <= (others => '0');
|
||||
elsif (qsfp1_iq_240b_to_512b_overflow = '1') then
|
||||
qsfp1_iq_240b_to_512b_overflow_cnt_r <= qsfp1_iq_240b_to_512b_overflow_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (qsfp1_capture_aresetn = '0' or cnt_reset_in = '1') then
|
||||
qsfp1_tvalid_512b_cnt_r <= (others => '0');
|
||||
elsif (qsfp1_tvalid_512b = '1' and qsfp1_tready_512b = '1') then
|
||||
qsfp1_tvalid_512b_cnt_r <= qsfp1_tvalid_512b_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- this fifo is actually 64 words deep
|
||||
i_axis_data_fifo_32x512 : entity work.axis_data_fifo_32x512
|
||||
port map (
|
||||
s_axis_aclk => qsfp1_capture_aclk_in,
|
||||
s_axis_aresetn => qsfp1_capture_aresetn,
|
||||
s_axis_tdata => qsfp1_tdata_512b, -- in
|
||||
s_axis_tvalid => qsfp1_tvalid_512b, -- in
|
||||
s_axis_tready => qsfp1_tready_512b, -- out
|
||||
|
||||
m_axis_aclk => tx_device_clk_in,
|
||||
m_axis_tdata => qsfp1_tdata_512b_pipe, -- out
|
||||
m_axis_tvalid => qsfp1_tvalid_512b_pipe, -- out
|
||||
m_axis_tready => axis_dwidth_converter_512b_to_128b_tready, -- in
|
||||
almost_empty => qsfp1_almost_empty_512b_pipe
|
||||
);
|
||||
|
||||
-- i_ila_128_4_qsfp1 : ila_128_4
|
||||
-- port map (
|
||||
-- clk => qsfp1_capture_aclk_in,
|
||||
-- probe0 => qsfp1_tvalid_240b,
|
||||
-- probe1 => qsfp1_aempty_240b,
|
||||
-- probe2 => qsfp1_afull_240b,
|
||||
-- probe3 => qsfp1_rx_data_ready,
|
||||
-- probe4 => qsfp1_tvalid_512b,
|
||||
-- probe5 => qsfp1_tready_512b,
|
||||
-- probe6 => qsfp1_afull_512b,
|
||||
-- probe7 => qsfp1_prog_full_512b,
|
||||
-- probe8 => qsfp1_almost_empty_512b_pipe)
|
||||
-- );
|
||||
|
||||
i_axis_dwidth_converter_512b_to_128b : entity work.axis_dwidth_converter_512b_to_128b
|
||||
port map (
|
||||
aclk => tx_device_clk_in, -- in
|
||||
aresetn => tx_device_clk_aresetn, -- in
|
||||
s_axis_tdata => qsfp1_tdata_512b_pipe, -- in
|
||||
s_axis_tvalid => qsfp1_tvalid_512b_pipe, -- in
|
||||
s_axis_tready => axis_dwidth_converter_512b_to_128b_tready, -- out
|
||||
m_axis_tdata => axis_dwidth_converter_512b_to_128b_tdata_128, -- out
|
||||
m_axis_tvalid => axis_dwidth_converter_512b_to_128b_tvalid_128, -- out
|
||||
m_axis_tready => qsfp1_tready_128b -- in
|
||||
);
|
||||
|
||||
-- big FIFO before JESD TX PORT - actually 64 words deep
|
||||
i_tx_fifo_32kx128 : entity work.axis_data_fifo_32kx128
|
||||
port map (
|
||||
s_axis_aclk => tx_device_clk_in, -- in
|
||||
s_axis_aresetn => tx_device_clk_aresetn, -- in
|
||||
s_axis_tdata => axis_dwidth_converter_512b_to_128b_tdata_128, -- in
|
||||
s_axis_tvalid => axis_dwidth_converter_512b_to_128b_tvalid_128, -- in
|
||||
s_axis_tready => qsfp1_tready_128b, -- out
|
||||
|
||||
m_axis_tdata => tx_fifo_tdata_128b_out, -- out
|
||||
m_axis_tvalid => tx_fifo_tvalid_128b, -- out
|
||||
m_axis_tready => tx_fifo_tready_128b_ena, -- in
|
||||
almost_empty => tx_fifo_128_aempty,-- out
|
||||
prog_full => tx_fifo_128_prog_full
|
||||
);
|
||||
|
||||
tx_fifo_tvalid_128b_ena <= tx_pre_buff_rdy_r and tx_fifo_tvalid_128b;
|
||||
tx_fifo_tready_128b_ena <= tx_pre_buff_rdy_r and tx_fifo_tready_128b_in;
|
||||
|
||||
process(tx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(tx_device_clk_in)) then
|
||||
if (qsfp1_capture_en_n_in = '1') then
|
||||
tx_pre_buff_rdy_r <= '0';
|
||||
elsif (tx_fifo_128_prog_full = '1') then
|
||||
tx_pre_buff_rdy_r <= '1';
|
||||
end if;
|
||||
|
||||
if (tx_device_clk_aresetn = '0' or cnt_reset_in = '1') then
|
||||
tx_fifo_128b_tvalid_128b_cnt_r <= (others => '0');
|
||||
elsif (tx_fifo_tvalid_128b_ena = '1' and tx_fifo_tready_128b_ena = '1') then
|
||||
tx_fifo_128b_tvalid_128b_cnt_r <= tx_fifo_128b_tvalid_128b_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(tx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(tx_device_clk_in)) then
|
||||
tx_fifo_128_aempty_r <= tx_fifo_128_aempty;
|
||||
|
||||
if (tx_device_clk_aresetn = '0' or cnt_reset_in = '1') then
|
||||
tx_fifo_128_aempty_cnt_r <= (others => '0');
|
||||
elsif (tx_fifo_128_aempty = '1' and tx_fifo_128_aempty_r = '0') then
|
||||
tx_fifo_128_aempty_cnt_r <= tx_fifo_128_aempty_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
tx_fifo_tvalid_128b_out <= tx_fifo_tvalid_128b_ena;
|
||||
|
||||
i_ila_3_qsfp1 : entity work.ila_3
|
||||
port map (
|
||||
clk => tx_device_clk_in,
|
||||
probe0(0) => axis_dwidth_converter_512b_to_128b_tvalid_128, --1
|
||||
probe1(0) => qsfp1_tready_128b, --
|
||||
probe2(0) => tx_fifo_128_prog_full, --1
|
||||
probe3(0) => tx_fifo_128_aempty, --1
|
||||
probe4(0) => tx_pre_buff_rdy_r, --1
|
||||
probe5(0) => tx_fifo_tvalid_128b_ena, --1
|
||||
probe6(0) => tx_fifo_tready_128b_ena, --1
|
||||
probe7(0) => tx_fifo_tready_128b_in, --1
|
||||
probe8(0) => qsfp1_almost_empty_512b_pipe, --1
|
||||
probe9(0) => qsfp1_tvalid_512b_pipe, -- 1
|
||||
probe10(0) => axis_dwidth_converter_512b_to_128b_tready -- 1
|
||||
);
|
||||
|
||||
|
||||
i_ila_3_qsfp1_IN : entity work.ila_3
|
||||
port map (
|
||||
clk => qsfp1_capture_aclk_in,
|
||||
probe0(0) => qsfp1_capture_tvalid_240b_in, --1
|
||||
probe1(0) => qsfp1_prog_full_240b, --
|
||||
probe2(0) => qsfp1_afull_240b, --1
|
||||
probe3(0) => qsfp1_tvalid_512b, --1
|
||||
probe4(0) => qsfp1_tready_512b, --1
|
||||
probe5(0) => qsfp1_aempty_240b, --1
|
||||
probe6(0) => qsfp1_iq_240b_to_512b_overflow , --1
|
||||
probe7(0) => qsfp1_rx_data_ready, --1
|
||||
probe8(0) => '0', --1
|
||||
probe9(0) => '0', -- 1
|
||||
probe10(0) => '0' -- 1
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
end architecture arch_imp;
|
||||
@@ -0,0 +1,235 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
--use ieee.numeric_std.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity qsfp4_playback_intfc is
|
||||
port (
|
||||
rx_device_clk_in : in std_logic;
|
||||
rx_device_clk_aresetn_in : in std_logic;
|
||||
rx_tdata_128b_in : in std_logic_vector(127 downto 0);
|
||||
rx_tvalid_128b_in : in std_logic;
|
||||
rx_tready_128b_out : out std_logic;
|
||||
rx_tvalid_128b_cnt_out : out std_logic_vector( 31 downto 0);
|
||||
rx_tvalid_128b_en_cnt_out : out std_logic_vector( 31 downto 0);
|
||||
playback_data_path_enable_n_in : in std_logic;
|
||||
|
||||
qsfp4_playback_aclk_in : in std_logic;
|
||||
qsfp4_playback_aresetn_in : in std_logic;
|
||||
qsfp4_playback_tdata_240b_out : out std_logic_vector(239 downto 0);
|
||||
qsfp4_playback_tvalid_240b_out : out std_logic;
|
||||
qsfp4_playback_tready_240b_in : in std_logic;
|
||||
qsfp4_playback_tvalid_240b_cnt_out : out std_logic_vector( 31 downto 0);
|
||||
|
||||
cnt_reset_in : in std_logic
|
||||
);
|
||||
end entity qsfp4_playback_intfc;
|
||||
|
||||
architecture arch_imp of qsfp4_playback_intfc is
|
||||
|
||||
signal playback_data_path_enable_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
signal rx_path_fifo_rst_n : std_logic;
|
||||
signal qsfp4_fifo_rst_n : std_logic;
|
||||
signal iq_512b_to_240b_rst_n : std_logic;
|
||||
signal playback_data_path_enable : std_logic;
|
||||
|
||||
signal rx_tvalid_128b_en : std_logic;
|
||||
signal rx_tvalid_128b_en_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal rx_tvalid_128b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal rx_tready_128b : std_logic;
|
||||
|
||||
signal rx_tdata_128b_pipe : std_logic_vector(127 downto 0);
|
||||
signal rx_tvalid_128b_pipe : std_logic;
|
||||
signal rx_tready_128b_pipe : std_logic;
|
||||
|
||||
signal rx_tdata_512b : std_logic_vector(511 downto 0);
|
||||
signal rx_tvalid_512b : std_logic;
|
||||
signal rx_tready_512b : std_logic;
|
||||
signal rx_tdata_512b_pipe : std_logic_vector(511 downto 0);
|
||||
signal rx_tvalid_512b_pipe : std_logic;
|
||||
signal rx_tready_512b_pipe : std_logic;
|
||||
|
||||
signal rx_tdata_240b : std_logic_vector(239 downto 0);
|
||||
signal rx_tvalid_240b : std_logic;
|
||||
signal rx_tready_240b : std_logic;
|
||||
|
||||
signal rx_tdata_240b_pipe : std_logic_vector(239 downto 0);
|
||||
signal rx_tvalid_240b_pipe : std_logic;
|
||||
signal rx_tready_240b_pipe : std_logic;
|
||||
|
||||
signal qsfp4_playback_tvalid_240b : std_logic;
|
||||
signal qsfp4_playback_tvalid_240b_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
qsfp4_playback_tvalid_240b_out <= qsfp4_playback_tvalid_240b;
|
||||
qsfp4_playback_tvalid_240b_cnt_out <= qsfp4_playback_tvalid_240b_cnt_r;
|
||||
rx_tvalid_128b_cnt_out <= rx_tvalid_128b_cnt_r;
|
||||
rx_tvalid_128b_en_cnt_out <= rx_tvalid_128b_en_cnt_r;
|
||||
rx_tready_128b_out <= rx_tready_128b;
|
||||
|
||||
process(rx_device_clk_in, rx_device_clk_aresetn_in)
|
||||
begin
|
||||
if (rx_device_clk_aresetn_in = '0') then
|
||||
playback_data_path_enable_r <= (others => '0');
|
||||
elsif (rising_edge(rx_device_clk_in)) then
|
||||
if (playback_data_path_enable_n_in = '1') then
|
||||
playback_data_path_enable_r <= (others => '0');
|
||||
else
|
||||
playback_data_path_enable_r <= playback_data_path_enable_r(1 to 31) & '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
rx_path_fifo_rst_n <= playback_data_path_enable_r(27);
|
||||
qsfp4_fifo_rst_n <= playback_data_path_enable_r(20);
|
||||
iq_512b_to_240b_rst_n <= playback_data_path_enable_r(16);
|
||||
playback_data_path_enable <= playback_data_path_enable_r(0);
|
||||
|
||||
process(rx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(rx_device_clk_in)) then
|
||||
if (rx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
rx_tvalid_128b_cnt_r <= (others => '0');
|
||||
elsif (rx_tvalid_128b_in = '1') then
|
||||
rx_tvalid_128b_cnt_r <= rx_tvalid_128b_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
rx_tvalid_128b_en <= rx_tvalid_128b_in when playback_data_path_enable = '1' else '0';
|
||||
|
||||
i_rx_register_slice_128 : entity work.axis_register_slice_128
|
||||
port map (
|
||||
aclk => rx_device_clk_in, -- in
|
||||
aresetn => rx_path_fifo_rst_n, -- in
|
||||
s_axis_tdata => rx_tdata_128b_in, -- in
|
||||
s_axis_tvalid => rx_tvalid_128b_en, -- in
|
||||
s_axis_tready => rx_tready_128b, -- out
|
||||
|
||||
m_axis_tdata => rx_tdata_128b_pipe, -- out
|
||||
m_axis_tvalid => rx_tvalid_128b_pipe, -- out
|
||||
m_axis_tready => rx_tready_128b_pipe -- in
|
||||
);
|
||||
|
||||
|
||||
-- i_ila_4 : entity work.ila_4
|
||||
-- port map (
|
||||
-- clk => rx_device_clk_in,
|
||||
-- probe0 => rx_tdata_128b_in, -- 128
|
||||
-- probe1 => rx_tvalid_128b_en, -- 1
|
||||
-- probe2 => rx_tready_128b, -- 1
|
||||
-- probe3 => rx_tvalid_128b_cnt_r -- 32
|
||||
-- );
|
||||
|
||||
|
||||
process(rx_device_clk_in)
|
||||
begin
|
||||
if (rising_edge(rx_device_clk_in)) then
|
||||
if (rx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
rx_tvalid_128b_en_cnt_r <= (others => '0');
|
||||
elsif (rx_tvalid_128b_pipe = '1' and rx_tready_128b_pipe = '1') then
|
||||
rx_tvalid_128b_en_cnt_r <= rx_tvalid_128b_en_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_axis_dwidth_converter_128b_to_512b : entity work.axis_dwidth_converter_128b_to_512b
|
||||
port map (
|
||||
aclk => rx_device_clk_in, -- in
|
||||
aresetn => rx_path_fifo_rst_n, -- in
|
||||
s_axis_tdata => rx_tdata_128b_pipe, -- in
|
||||
s_axis_tvalid => rx_tvalid_128b_pipe,-- in
|
||||
s_axis_tready => rx_tready_128b_pipe,-- out
|
||||
m_axis_tdata => rx_tdata_512b, -- out
|
||||
m_axis_tvalid => rx_tvalid_512b, -- out
|
||||
m_axis_tready => rx_tready_512b -- in
|
||||
);
|
||||
|
||||
i_qsfp4_reg_slice_512 : entity work.axis_register_slice_512
|
||||
port map (
|
||||
aclk => rx_device_clk_in, -- in
|
||||
aresetn => rx_path_fifo_rst_n, -- in
|
||||
s_axis_tdata => rx_tdata_512b, -- in
|
||||
s_axis_tvalid => rx_tvalid_512b, -- in
|
||||
s_axis_tready => rx_tready_512b, -- out
|
||||
m_axis_tdata => rx_tdata_512b_pipe, -- out
|
||||
m_axis_tvalid => rx_tvalid_512b_pipe, -- out
|
||||
m_axis_tready => rx_tready_512b_pipe -- in
|
||||
);
|
||||
|
||||
i_iq_512b_to_240b : entity work.iq_512b_to_240b
|
||||
port map (
|
||||
aclk => rx_device_clk_in, -- in
|
||||
aresetn => iq_512b_to_240b_rst_n, -- in
|
||||
s_axis_tdata => rx_tdata_512b_pipe, --in
|
||||
s_axis_tvalid => rx_tvalid_512b_pipe, --in
|
||||
s_axis_tready => rx_tready_512b_pipe, --out
|
||||
m_axis_tdata => rx_tdata_240b, --out
|
||||
m_axis_tvalid => rx_tvalid_240b, --out
|
||||
m_axis_tready => rx_tready_240b --in
|
||||
);
|
||||
|
||||
i_qsfp4_reg_slice_240b : entity work.axis_register_slice_240
|
||||
port map (
|
||||
aclk => rx_device_clk_in, -- in
|
||||
aresetn => rx_path_fifo_rst_n, -- in
|
||||
s_axis_tdata => rx_tdata_240b, --in
|
||||
s_axis_tvalid => rx_tvalid_240b, --in
|
||||
s_axis_tready => rx_tready_240b, --out
|
||||
m_axis_tdata => rx_tdata_240b_pipe, --out
|
||||
m_axis_tvalid => rx_tvalid_240b_pipe, --out
|
||||
m_axis_tready => rx_tready_240b_pipe --in
|
||||
);
|
||||
|
||||
-- this fifo is actually 32 words deep
|
||||
i_qsfp4_fifo : entity work.axis_data_fifo_32x240
|
||||
port map (
|
||||
s_axis_aclk => rx_device_clk_in, -- in
|
||||
s_axis_aresetn => qsfp4_fifo_rst_n, -- in
|
||||
s_axis_tdata => rx_tdata_240b_pipe, --in
|
||||
s_axis_tvalid => rx_tvalid_240b_pipe, --in
|
||||
s_axis_tready => rx_tready_240b_pipe, --out
|
||||
|
||||
m_axis_aclk => qsfp4_playback_aclk_in, -- in
|
||||
m_axis_tdata => qsfp4_playback_tdata_240b_out, --out
|
||||
m_axis_tvalid => qsfp4_playback_tvalid_240b, --out
|
||||
m_axis_tready => qsfp4_playback_tready_240b_in --in
|
||||
);
|
||||
|
||||
process(qsfp4_playback_aclk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp4_playback_aclk_in)) then
|
||||
if (rx_device_clk_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
qsfp4_playback_tvalid_240b_cnt_r <= (others => '0');
|
||||
elsif (qsfp4_playback_tvalid_240b = '1' and qsfp4_playback_tready_240b_in = '1') then
|
||||
qsfp4_playback_tvalid_240b_cnt_r <= qsfp4_playback_tvalid_240b_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
i_ila_3_qsfp4_IN : entity work.ila_3
|
||||
port map (
|
||||
clk => rx_device_clk_in,
|
||||
probe0(0) => rx_tvalid_240b_pipe, --1
|
||||
probe1(0) => rx_tready_240b_pipe, --
|
||||
|
||||
probe2(0) => rx_tvalid_240b, --1
|
||||
probe3(0) => rx_tready_240b, --1
|
||||
|
||||
probe4(0) => rx_tvalid_512b_pipe, --1
|
||||
probe5(0) => rx_tready_512b_pipe, --1
|
||||
|
||||
probe6(0) => rx_tvalid_128b_pipe , --1
|
||||
probe7(0) => rx_tready_128b_pipe, --1
|
||||
|
||||
probe8(0) => rx_tvalid_128b_en, --1 ,
|
||||
probe9(0) => rx_tready_128b, -- 1 ,
|
||||
probe10(0) => playback_data_path_enable_n_in -- 1
|
||||
);
|
||||
|
||||
|
||||
end architecture arch_imp;
|
||||
|
||||
+1186
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,121 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity tick_gen is
|
||||
generic(
|
||||
CLOCK_SPEED_MHZ : integer := 100
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
|
||||
tick_1us_out : out std_logic;
|
||||
tick_1ms_out : out std_logic;
|
||||
tick_500ms_out : out std_logic;
|
||||
tick_750ms_out : out std_logic;
|
||||
tick_1s_out : out std_logic;
|
||||
|
||||
prog_us_tick_rate_in : in std_logic_vector(31 downto 0);
|
||||
prog_us_tick_out : out std_logic;
|
||||
|
||||
reset_in : in std_logic
|
||||
);
|
||||
end entity tick_gen;
|
||||
|
||||
architecture imp of tick_gen is
|
||||
|
||||
signal sysclk_cnt_r : integer range 0 to CLOCK_SPEED_MHZ-1;
|
||||
signal usec_cnt_r : integer range 0 to 999;
|
||||
signal msec_cnt_r : integer range 0 to 499;
|
||||
signal msec_cnt1_r : integer range 0 to 999;
|
||||
signal tick_1us_r : std_logic;
|
||||
signal tick_1ms_r : std_logic;
|
||||
signal tick_500ms_r : std_logic;
|
||||
signal tick_750ms_r : std_logic;
|
||||
signal tick_1s_r : std_logic;
|
||||
|
||||
signal prog_usec_cnt_r : std_logic_vector(31 downto 0);
|
||||
signal prog_us_tick_r : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
tick_1us_out <= tick_1us_r;
|
||||
tick_1ms_out <= tick_1ms_r;
|
||||
tick_500ms_out <= tick_500ms_r;
|
||||
tick_750ms_out <= tick_750ms_r;
|
||||
tick_1s_out <= tick_1s_r;
|
||||
prog_us_tick_out <= prog_us_tick_r;
|
||||
|
||||
process(clk_in, reset_in)
|
||||
begin
|
||||
if(reset_in = '1') then
|
||||
sysclk_cnt_r <= 0;
|
||||
usec_cnt_r <= 0;
|
||||
msec_cnt_r <= 0;
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '0';
|
||||
elsif rising_edge(clk_in) then
|
||||
tick_1ms_r <= '0';
|
||||
tick_500ms_r <= '0';
|
||||
tick_750ms_r <= '0';
|
||||
tick_1s_r <= '0';
|
||||
prog_us_tick_r <= '0';
|
||||
|
||||
if(sysclk_cnt_r = CLOCK_SPEED_MHZ-1) then
|
||||
sysclk_cnt_r <= 0;
|
||||
tick_1us_r <= '1';
|
||||
else
|
||||
sysclk_cnt_r <= sysclk_cnt_r + 1;
|
||||
tick_1us_r <= '0';
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(usec_cnt_r = 999) then -- 1000us
|
||||
usec_cnt_r <= 0;
|
||||
tick_1ms_r <= '1';
|
||||
else
|
||||
usec_cnt_r <= usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt_r = 499) then -- 500ms
|
||||
msec_cnt_r <= 0;
|
||||
tick_500ms_r <= '1';
|
||||
else
|
||||
msec_cnt_r <= msec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1ms_r = '1') then
|
||||
if(msec_cnt1_r = 749) then -- 750ms
|
||||
tick_750ms_r <= '1';
|
||||
end if;
|
||||
if(msec_cnt1_r = 999) then -- 1s
|
||||
msec_cnt1_r <= 0;
|
||||
tick_1s_r <= '1';
|
||||
else
|
||||
msec_cnt1_r <= msec_cnt1_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(tick_1us_r = '1') then
|
||||
if(prog_usec_cnt_r = prog_us_tick_rate_in) then
|
||||
prog_usec_cnt_r <= (others => '0');
|
||||
prog_us_tick_r <= '1';
|
||||
else
|
||||
prog_usec_cnt_r <= prog_usec_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,256 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company: Erisys
|
||||
-- Engineer: Jason M Blevins
|
||||
--
|
||||
-- Create Date: 07/08/2023
|
||||
-- Design Name:
|
||||
-- Module Name: top - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity top_si5341 is
|
||||
generic (
|
||||
SIM_ENABLED : boolean := FALSE;
|
||||
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0409_2025";
|
||||
MINOR_REV : std_logic_vector( 7 downto 0) := x"01"
|
||||
);
|
||||
Port(
|
||||
|
||||
pl_clk0_p : in std_logic;
|
||||
pl_clk0_n : in std_logic;
|
||||
|
||||
-- QSFP2_SI570_CLOCK_P : in std_logic;
|
||||
-- QSFP2_SI570_CLOCK_N : in std_logic; --//CLK3_N
|
||||
|
||||
-- QSFP3_SI570_CLOCK_P : in std_logic;
|
||||
-- QSFP3_SI570_CLOCK_N : in std_logic; --//CLK1_N
|
||||
|
||||
PL_SCL : inout std_logic;
|
||||
PL_SDA : inout std_logic
|
||||
|
||||
);
|
||||
end top_si5341;
|
||||
|
||||
architecture imp of top_si5341 is
|
||||
|
||||
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
attribute keep : string;
|
||||
attribute keep of fpga_revision_date_r : signal is "true";
|
||||
|
||||
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
|
||||
attribute keep of minor_rev_r : signal is "true";
|
||||
|
||||
signal clk_200 : std_logic;
|
||||
signal clk_200_resetn_r : std_logic_vector(0 to 31) := (others => '0');
|
||||
signal clk_200_resetn : std_logic;
|
||||
|
||||
signal clk_100 : std_logic;
|
||||
signal clk_100_reset_r : std_logic_vector(0 to 31) := (others => '1');
|
||||
signal clk_100_reset : std_logic;
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal sda_i : std_logic;
|
||||
signal sda_o : std_logic;
|
||||
signal sda_t : std_logic;
|
||||
|
||||
signal scl_i : std_logic;
|
||||
signal scl_o : std_logic;
|
||||
signal scl_t : std_logic;
|
||||
|
||||
signal i2c_mux_access_ok : std_logic;
|
||||
signal si5341_access_ok : std_logic;
|
||||
signal si5341_config_done : std_logic;
|
||||
signal si5341_config_error : std_logic;
|
||||
|
||||
signal man_clk_gen_en : std_logic;
|
||||
signal man_clk_gty_rst_n : std_logic;
|
||||
signal man_clk_gen_cfg_reset : std_logic;
|
||||
|
||||
signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
|
||||
i_pl_clk0_ibufds : entity work.IBUFDS
|
||||
port map (
|
||||
I => pl_clk0_p,
|
||||
IB => pl_clk0_n,
|
||||
O => clk_200
|
||||
);
|
||||
|
||||
process(clk_200)
|
||||
begin
|
||||
if (rising_edge(clk_200)) then
|
||||
clk_200_resetn_r <= clk_200_resetn_r(1 to 31) & '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
clk_200_resetn <= clk_200_resetn_r(0);
|
||||
|
||||
i_bufgce_div : BUFGCE_DIV
|
||||
generic map (
|
||||
BUFGCE_DIVIDE => 2, -- 1-8
|
||||
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
|
||||
IS_CE_INVERTED => '0', -- Optional inversion for CE
|
||||
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
|
||||
IS_I_INVERTED => '0', -- Optional inversion for I
|
||||
SIM_DEVICE => "ULTRASCALE_PLUS" -- ULTRASCALE, ULTRASCALE_PLUS
|
||||
)
|
||||
port map (
|
||||
O => clk_100, -- 1-bit output: Buffer
|
||||
CE => '1', -- 1-bit input: Buffer enable
|
||||
CLR => '0', -- 1-bit input: Asynchronous clear
|
||||
I => clk_200 -- 1-bit input: Buffer
|
||||
);
|
||||
|
||||
process(clk_100)
|
||||
begin
|
||||
if (rising_edge(clk_100)) then
|
||||
clk_100_reset_r <= clk_100_reset_r(1 to 31) & '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
clk_100_reset <= clk_100_reset_r(0);
|
||||
|
||||
|
||||
|
||||
|
||||
i_si5341_clk_conf : entity work.si5341_clk_configurator
|
||||
port map (
|
||||
sys_clk100_in => clk_100,
|
||||
tick_1ms_in => tick_1ms,
|
||||
|
||||
si5341_clk_gty_rst_n_out => open,
|
||||
|
||||
si5341_clk_sync_n_out => open,
|
||||
si5341_clk_lol_n_in => '1',
|
||||
si5341_clk_intr_n_in => '1',
|
||||
|
||||
sda_in => sda_i,
|
||||
sda_out => sda_o,
|
||||
sda_t_out => sda_t,
|
||||
|
||||
scl_in => scl_i,
|
||||
scl_out => scl_o,
|
||||
scl_t_out => scl_t,
|
||||
|
||||
clk_gen_i2c_buf_sel_out => open,
|
||||
|
||||
i2c_rst_n_out => open,
|
||||
|
||||
i2c_mux_access_ok_out => i2c_mux_access_ok,
|
||||
si5341_access_ok_out => si5341_access_ok,
|
||||
si5341_config_done_out => si5341_config_done,
|
||||
si5341_config_error_out => si5341_config_error,
|
||||
|
||||
man_clk_gen_en_in => man_clk_gen_en,
|
||||
man_clk_gty_rst_n_in => man_clk_gty_rst_n,
|
||||
man_clk_gen_cfg_reset_in => man_clk_gen_cfg_reset,
|
||||
reset_in => clk_100_reset
|
||||
);
|
||||
|
||||
i_scl_iobuf : IOBUF
|
||||
port map (
|
||||
O => scl_i,
|
||||
I => scl_o,
|
||||
IO => PL_SCL,
|
||||
T => scl_t
|
||||
);
|
||||
|
||||
i_sda_iobuf : IOBUF
|
||||
port map (
|
||||
O => sda_i,
|
||||
I => sda_o,
|
||||
IO => PL_SDA,
|
||||
T => sda_t
|
||||
);
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => clk_100,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"0000_0000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => clk_100_reset
|
||||
);
|
||||
|
||||
process(clk_100)
|
||||
begin
|
||||
if (rising_edge(clk_100)) then
|
||||
fpga_revision_date_r <= FPGA_REVISION_DATE;
|
||||
minor_rev_r <= MINOR_REV;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_vio_0 : entity work.vio_0
|
||||
port map (
|
||||
clk => clk_100,
|
||||
probe_in0 => fpga_revision_date_r, -- 32
|
||||
probe_in1 => minor_rev_r, -- 8
|
||||
probe_in2(0) => i2c_mux_access_ok, -- 1
|
||||
probe_in3(0) => si5341_access_ok, -- 1
|
||||
probe_in4(0) => si5341_config_done, -- 1
|
||||
probe_in5(0) => si5341_config_error, -- 1
|
||||
probe_in6 => clk_100_freq_r, -- 32
|
||||
probe_in7 => clk_100_cnt_r, -- 32
|
||||
|
||||
probe_out2(0) => man_clk_gen_en, -- 1
|
||||
probe_out3(0) => man_clk_gty_rst_n, -- 1
|
||||
probe_out4(0) => man_clk_gen_cfg_reset -- 1
|
||||
);
|
||||
|
||||
process(clk_100)
|
||||
begin
|
||||
if (rising_edge(clk_100)) then
|
||||
clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (clk_100_tick_1ms_r(0 to 1) = "01") then
|
||||
clk_100_freq_r <= clk_100_cnt_r;
|
||||
clk_100_cnt_r <= (others => '0');
|
||||
else
|
||||
clk_100_cnt_r <= clk_100_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end imp;
|
||||
Reference in New Issue
Block a user