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moving repo from git to local repo

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Nick Santana
2026-06-02 13:29:07 -04:00
commit e84a517056
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:22 03/24/2017
-- Design Name:
-- Module Name:
-- Project Name: xem7350
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dac_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
Library xpm;
use xpm.vcomponents.all;
--library UNISIM;
--use UNISIM.VComponents.all;
entity dds_wrapper_tb is
end dds_wrapper_tb;
architecture behavior of dds_wrapper_tb is
-- Clock period definitions
constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
constant CLK_100_PERIOD : time := 10 ns; -- 100 MHz
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
signal clk_100 : std_logic := '0';
signal clk_100_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_250 : std_logic := '0';
signal clk_250_aresetn : std_logic_vector(0 to 63) := x"0000_FFFF_0000_0000";--(others => '0');
signal m_axis_tready_r : std_logic := '0';
signal m_axis_tdata : std_logic_vector(127 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal util_mxfe_upack_s_axis_tdata_pipe : std_logic_vector(127 downto 0);
signal util_mxfe_upack_s_axis_tvalid_pipe : std_logic;
signal m_axis_tdata_1 : std_logic_vector(127 downto 0);
signal m_axis_tvalid_1 : std_logic;
signal m_axis_tready_1 : std_logic;
signal cmd_send_i : std_logic_vector(0 to 3) := (others => '0');
signal dac_holdoff_r : std_logic := '1';
signal chan1_i : std_logic_vector(15 downto 0);
signal chan1_q : std_logic_vector(15 downto 0);
signal chan2_i : std_logic_vector(15 downto 0);
signal chan2_q : std_logic_vector(15 downto 0);
signal chan3_i : std_logic_vector(15 downto 0);
signal chan3_q : std_logic_vector(15 downto 0);
signal chan4_i : std_logic_vector(15 downto 0);
signal chan4_q : std_logic_vector(15 downto 0);
signal cmd_send_0_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_1_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_2_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_3_r : std_logic_vector(0 to 2) := (others => '0');
signal cnt_reset : std_logic := '0';
begin
clk_100 <= not clk_100 after CLK_100_PERIOD/2;
clk_250 <= not clk_250 after CLK_250_PERIOD/2;
--
process(clk_100)
begin
if (rising_edge(clk_100)) then
clk_100_aresetn <= clk_100_aresetn(1 to 15) & '1';
end if;
end process;
--
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_aresetn <= clk_250_aresetn(1 to 63) & '1';
end if;
end process;
process (clk_100)
begin
if rising_edge(clk_100) then
if (cmd_send_i(0) = '1') then
cmd_send_0_r <= "111";
else
cmd_send_0_r <= cmd_send_0_r(1 to 2) & '0';
end if;
if (cmd_send_i(1) = '1') then
cmd_send_1_r <= "111";
else
cmd_send_1_r <= cmd_send_1_r(1 to 2) & '0';
end if;
if (cmd_send_i(2) = '1') then
cmd_send_2_r <= "111";
else
cmd_send_2_r <= cmd_send_2_r(1 to 2) & '0';
end if;
if (cmd_send_i(3) = '1') then
cmd_send_3_r <= "111";
else
cmd_send_3_r <= cmd_send_3_r(1 to 2) & '0';
end if;
end if;
end process;
i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4
port map (
s_axi_aclk_in => clk_100,
s_axi_aresetn_in => clk_100_aresetn(0),
cmd_idx_in => "000",
dac_holdoff_in => dac_holdoff_r,
dds_chan_en_in => "1111",
cmd_send_0_in => cmd_send_0_r(0),
scale_0_in => x"8000",
dds_phase_inc_dwell_time_0_in => x"00000000",
dds_phase_inc_step_size_0_in => x"0000D6BF",
idle_samples_0_in => x"00000000",
dds_samples_0_in => x"000004E2",
phase_inc_0_in => x"010624DD",
phase_off_0_in => x"00000000",
swap_sf_0_in => x"00008000",
cmd_send_1_in => cmd_send_1_r(0),
scale_1_in => x"8000",
dds_phase_inc_dwell_time_1_in => x"00000000",
dds_phase_inc_step_size_1_in => x"0000D6BF",
idle_samples_1_in => x"00000000",
dds_samples_1_in => x"000014E2", --x"000004E2",
phase_inc_1_in => x"010624DD",
phase_off_1_in => x"00000000",
swap_sf_1_in => x"00008000",
cmd_send_2_in => cmd_send_2_r(0),
scale_2_in => x"8000",
dds_phase_inc_dwell_time_2_in => x"00000000",
dds_phase_inc_step_size_2_in => x"0000D6BF",
idle_samples_2_in => x"00000000",
dds_samples_2_in => x"000004E2",
phase_inc_2_in => x"010624DD",
phase_off_2_in => x"00000000",
swap_sf_2_in => x"00008000",
cmd_send_3_in => cmd_send_3_r(0),
scale_3_in => x"8000",
dds_phase_inc_dwell_time_3_in => x"00000000",
dds_phase_inc_step_size_3_in => x"0000D6BF",
idle_samples_3_in => x"00000000",
dds_samples_3_in => x"000004E2",
phase_inc_3_in => x"010624DD",
phase_off_3_in => x"00000000",
swap_sf_3_in => x"00008000",
m_axis_aclk_in => clk_250,
m_axis_aresetn_in => clk_250_aresetn(0),
m_axis_tdata_out => m_axis_tdata,
m_axis_tvalid_out => m_axis_tvalid,
m_axis_tready_in => m_axis_tready,
cnt_reset_in => cnt_reset,
m_axis_tvalid_cnt_out => open,
dds_pulse_data_cnt_out => open
);
-- big FIFO before JESD TX PORT
i_dac_data_fifo_32kx128 : entity work.axis_data_fifo_32kx128
port map (
s_axis_aclk => clk_250, -- in
s_axis_aresetn => clk_250_aresetn(0), -- in
s_axis_tdata => m_axis_tdata, -- in
s_axis_tvalid => m_axis_tvalid, -- in
s_axis_tready => m_axis_tready, -- out
m_axis_tdata => m_axis_tdata_1, -- out
m_axis_tvalid => m_axis_tvalid_1, -- out
m_axis_tready => m_axis_tready_1 -- in
);
-- big FIFO before JESD TX PORT
i_dac_data_fifo_32kx128_1 : entity work.axis_data_fifo_32kx128
port map (
s_axis_aclk => clk_250, -- in
s_axis_aresetn => clk_250_aresetn(0), -- in
s_axis_tdata => m_axis_tdata_1, -- in
s_axis_tvalid => m_axis_tvalid_1, -- in
s_axis_tready => m_axis_tready_1, -- out
m_axis_tdata => util_mxfe_upack_s_axis_tdata_pipe, -- out
m_axis_tvalid => util_mxfe_upack_s_axis_tvalid_pipe, -- out
m_axis_tready => m_axis_tready_r -- in
);
chan1_i <= util_mxfe_upack_s_axis_tdata_pipe(15 downto 0);
chan1_q <= util_mxfe_upack_s_axis_tdata_pipe(31 downto 16);
chan2_i <= util_mxfe_upack_s_axis_tdata_pipe(47 downto 32);
chan2_q <= util_mxfe_upack_s_axis_tdata_pipe(63 downto 48);
chan3_i <= util_mxfe_upack_s_axis_tdata_pipe(79 downto 64);
chan3_q <= util_mxfe_upack_s_axis_tdata_pipe(95 downto 80);
chan4_i <= util_mxfe_upack_s_axis_tdata_pipe(111 downto 96);
chan4_q <= util_mxfe_upack_s_axis_tdata_pipe(127 downto 112);
-- Stimulus process
stim_proc: process
begin
wait until clk_100_aresetn(0) = '1';
-- wait for 24 us;
wait until rising_edge(clk_250);
m_axis_tready_r <= '1';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(0) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(0) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(1) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(1) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(2) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(2) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(3) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(3) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
dac_holdoff_r <= '0';
wait for 8 us;
cnt_reset <= '1';
wait until rising_edge(clk_100);
cnt_reset <= '0';
-- m_axis_tready_r <= '0';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '1';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '0';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '1';
wait until rising_edge(clk_100);
wait; -- wait here forever
end process;
end;