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moving repo from git to local repo

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This commit is contained in:
Nick Santana
2026-06-02 13:29:07 -04:00
commit e84a517056
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sim/dds_wrapper_tb.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:22 03/24/2017
-- Design Name:
-- Module Name:
-- Project Name: xem7350
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dac_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
Library xpm;
use xpm.vcomponents.all;
--library UNISIM;
--use UNISIM.VComponents.all;
entity dds_wrapper_tb is
end dds_wrapper_tb;
architecture behavior of dds_wrapper_tb is
-- Clock period definitions
constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
constant CLK_100_PERIOD : time := 10 ns; -- 100 MHz
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
signal clk_100 : std_logic := '0';
signal clk_100_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_250 : std_logic := '0';
signal clk_250_aresetn : std_logic_vector(0 to 63) := x"0000_FFFF_0000_0000";--(others => '0');
signal m_axis_tready_r : std_logic := '0';
signal m_axis_tdata : std_logic_vector(127 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal util_mxfe_upack_s_axis_tdata_pipe : std_logic_vector(127 downto 0);
signal util_mxfe_upack_s_axis_tvalid_pipe : std_logic;
signal m_axis_tdata_1 : std_logic_vector(127 downto 0);
signal m_axis_tvalid_1 : std_logic;
signal m_axis_tready_1 : std_logic;
signal cmd_send_i : std_logic_vector(0 to 3) := (others => '0');
signal dac_holdoff_r : std_logic := '1';
signal chan1_i : std_logic_vector(15 downto 0);
signal chan1_q : std_logic_vector(15 downto 0);
signal chan2_i : std_logic_vector(15 downto 0);
signal chan2_q : std_logic_vector(15 downto 0);
signal chan3_i : std_logic_vector(15 downto 0);
signal chan3_q : std_logic_vector(15 downto 0);
signal chan4_i : std_logic_vector(15 downto 0);
signal chan4_q : std_logic_vector(15 downto 0);
signal cmd_send_0_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_1_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_2_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_3_r : std_logic_vector(0 to 2) := (others => '0');
signal cnt_reset : std_logic := '0';
begin
clk_100 <= not clk_100 after CLK_100_PERIOD/2;
clk_250 <= not clk_250 after CLK_250_PERIOD/2;
--
process(clk_100)
begin
if (rising_edge(clk_100)) then
clk_100_aresetn <= clk_100_aresetn(1 to 15) & '1';
end if;
end process;
--
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_aresetn <= clk_250_aresetn(1 to 63) & '1';
end if;
end process;
process (clk_100)
begin
if rising_edge(clk_100) then
if (cmd_send_i(0) = '1') then
cmd_send_0_r <= "111";
else
cmd_send_0_r <= cmd_send_0_r(1 to 2) & '0';
end if;
if (cmd_send_i(1) = '1') then
cmd_send_1_r <= "111";
else
cmd_send_1_r <= cmd_send_1_r(1 to 2) & '0';
end if;
if (cmd_send_i(2) = '1') then
cmd_send_2_r <= "111";
else
cmd_send_2_r <= cmd_send_2_r(1 to 2) & '0';
end if;
if (cmd_send_i(3) = '1') then
cmd_send_3_r <= "111";
else
cmd_send_3_r <= cmd_send_3_r(1 to 2) & '0';
end if;
end if;
end process;
i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4
port map (
s_axi_aclk_in => clk_100,
s_axi_aresetn_in => clk_100_aresetn(0),
cmd_idx_in => "000",
dac_holdoff_in => dac_holdoff_r,
dds_chan_en_in => "1111",
cmd_send_0_in => cmd_send_0_r(0),
scale_0_in => x"8000",
dds_phase_inc_dwell_time_0_in => x"00000000",
dds_phase_inc_step_size_0_in => x"0000D6BF",
idle_samples_0_in => x"00000000",
dds_samples_0_in => x"000004E2",
phase_inc_0_in => x"010624DD",
phase_off_0_in => x"00000000",
swap_sf_0_in => x"00008000",
cmd_send_1_in => cmd_send_1_r(0),
scale_1_in => x"8000",
dds_phase_inc_dwell_time_1_in => x"00000000",
dds_phase_inc_step_size_1_in => x"0000D6BF",
idle_samples_1_in => x"00000000",
dds_samples_1_in => x"000014E2", --x"000004E2",
phase_inc_1_in => x"010624DD",
phase_off_1_in => x"00000000",
swap_sf_1_in => x"00008000",
cmd_send_2_in => cmd_send_2_r(0),
scale_2_in => x"8000",
dds_phase_inc_dwell_time_2_in => x"00000000",
dds_phase_inc_step_size_2_in => x"0000D6BF",
idle_samples_2_in => x"00000000",
dds_samples_2_in => x"000004E2",
phase_inc_2_in => x"010624DD",
phase_off_2_in => x"00000000",
swap_sf_2_in => x"00008000",
cmd_send_3_in => cmd_send_3_r(0),
scale_3_in => x"8000",
dds_phase_inc_dwell_time_3_in => x"00000000",
dds_phase_inc_step_size_3_in => x"0000D6BF",
idle_samples_3_in => x"00000000",
dds_samples_3_in => x"000004E2",
phase_inc_3_in => x"010624DD",
phase_off_3_in => x"00000000",
swap_sf_3_in => x"00008000",
m_axis_aclk_in => clk_250,
m_axis_aresetn_in => clk_250_aresetn(0),
m_axis_tdata_out => m_axis_tdata,
m_axis_tvalid_out => m_axis_tvalid,
m_axis_tready_in => m_axis_tready,
cnt_reset_in => cnt_reset,
m_axis_tvalid_cnt_out => open,
dds_pulse_data_cnt_out => open
);
-- big FIFO before JESD TX PORT
i_dac_data_fifo_32kx128 : entity work.axis_data_fifo_32kx128
port map (
s_axis_aclk => clk_250, -- in
s_axis_aresetn => clk_250_aresetn(0), -- in
s_axis_tdata => m_axis_tdata, -- in
s_axis_tvalid => m_axis_tvalid, -- in
s_axis_tready => m_axis_tready, -- out
m_axis_tdata => m_axis_tdata_1, -- out
m_axis_tvalid => m_axis_tvalid_1, -- out
m_axis_tready => m_axis_tready_1 -- in
);
-- big FIFO before JESD TX PORT
i_dac_data_fifo_32kx128_1 : entity work.axis_data_fifo_32kx128
port map (
s_axis_aclk => clk_250, -- in
s_axis_aresetn => clk_250_aresetn(0), -- in
s_axis_tdata => m_axis_tdata_1, -- in
s_axis_tvalid => m_axis_tvalid_1, -- in
s_axis_tready => m_axis_tready_1, -- out
m_axis_tdata => util_mxfe_upack_s_axis_tdata_pipe, -- out
m_axis_tvalid => util_mxfe_upack_s_axis_tvalid_pipe, -- out
m_axis_tready => m_axis_tready_r -- in
);
chan1_i <= util_mxfe_upack_s_axis_tdata_pipe(15 downto 0);
chan1_q <= util_mxfe_upack_s_axis_tdata_pipe(31 downto 16);
chan2_i <= util_mxfe_upack_s_axis_tdata_pipe(47 downto 32);
chan2_q <= util_mxfe_upack_s_axis_tdata_pipe(63 downto 48);
chan3_i <= util_mxfe_upack_s_axis_tdata_pipe(79 downto 64);
chan3_q <= util_mxfe_upack_s_axis_tdata_pipe(95 downto 80);
chan4_i <= util_mxfe_upack_s_axis_tdata_pipe(111 downto 96);
chan4_q <= util_mxfe_upack_s_axis_tdata_pipe(127 downto 112);
-- Stimulus process
stim_proc: process
begin
wait until clk_100_aresetn(0) = '1';
-- wait for 24 us;
wait until rising_edge(clk_250);
m_axis_tready_r <= '1';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(0) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(0) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(1) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(1) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(2) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(2) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(3) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(3) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
dac_holdoff_r <= '0';
wait for 8 us;
cnt_reset <= '1';
wait until rising_edge(clk_100);
cnt_reset <= '0';
-- m_axis_tready_r <= '0';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '1';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '0';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '1';
wait until rising_edge(clk_100);
wait; -- wait here forever
end process;
end;
sim/tb_cap_plybk.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:22 03/24/2017
-- Design Name:
-- Module Name:
-- Project Name: xem7350
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dac_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
entity tb_cap_plybk is
end tb_cap_plybk;
architecture behavior of tb_cap_plybk is
constant C_M_AXI_DATA_WIDTH : integer := 32;
constant C_M_AXI_ADDR_WIDTH : integer := 32;
-- Clock period definitions
constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
signal clk_125 : std_logic := '0';
signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_125_reset : std_logic;
signal clk_250 : std_logic := '0';
signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_250_areset : std_logic;
signal tx_device_clk_1 : std_logic := '0';
signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal tx_device_clk_aresetn : std_logic;
signal rx_device_clk_1 : std_logic := '0';
signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal rx_device_clk_aresetn : std_logic;
signal rx_device_clk_areset : std_logic;
signal qsfp4_playback_aclk : std_logic := '0';
signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp4_playback_aresetn : std_logic;
signal qsfp1_capture_aclk : std_logic;
signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp1_capture_aresetn : std_logic;
--
signal tick_1ms : std_logic;
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal adc_rx_tdata_128b : std_logic_vector(127 downto 0) := (others => '0');
signal adc_rx_tvalid_128b : std_logic := '0';
signal adc_rx_tready_128b : std_logic;
signal adc_rx_tvalid_128b_cnt : std_logic_vector(31 downto 0);
signal qsfp4_playback_tdata_240b : std_logic_vector(239 downto 0);
signal qsfp4_playback_tvalid_240b : std_logic;
signal qsfp4_playback_tready_240b : std_logic := '1';
signal qsfp1_capture_tdata_240b : std_logic_vector(239 downto 0);
signal qsfp1_capture_tvalid_240b : std_logic;
signal tx_tdata_128b : std_logic_vector(127 downto 0);
signal tx_tvalid_128b : std_logic;
signal tx_tready_128b : std_logic := '1';
signal qsfp1_capture_rx_data_ready : std_logic;
signal playback_data_path_enable_n : std_logic := '1';
signal adc_rx_tvalid_128b_ena : std_logic;
begin
clk_125 <= not clk_125 after CLK_125_PERIOD/2;
clk_250 <= not clk_250 after CLK_250_PERIOD/2;
tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2;
rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2;
qsfp4_playback_aclk <= not qsfp4_playback_aclk after QSFP4_AXIS_ACLK_PERIOD/2;
-- qsfp1_capture_aclk <= not qsfp1_capture_aclk after QSFP1_AXIS_ACLK_PERIOD/2;
--
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
clk_125_reset <= not clk_125_aresetn(0);
--
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1';
end if;
end process;
clk_250_areset <= not clk_250_aresetn(0);
--
process(tx_device_clk_1)
begin
if (rising_edge(tx_device_clk_1)) then
tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1';
end if;
end process;
tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0);
--
process(rx_device_clk_1)
begin
if (rising_edge(rx_device_clk_1)) then
rx_device_clk_aresetn_r <= rx_device_clk_aresetn_r(1 to 15) & '1';
end if;
end process;
rx_device_clk_aresetn <= rx_device_clk_aresetn_r(0);
--
process(qsfp4_playback_aclk)
begin
if (rising_edge(qsfp4_playback_aclk)) then
qsfp4_axis_aresetn_r <= qsfp4_axis_aresetn_r(1 to 15) & '1';
end if;
end process;
qsfp4_playback_aresetn <= qsfp4_axis_aresetn_r(0);
--
process(rx_device_clk_1)
begin
if (rising_edge(rx_device_clk_1)) then
adc_rx_tdata_128b <= adc_rx_tdata_128b + x"0003_0002_0001_0004_0005_0006_0007_0008";
end if;
end process;
--
process(qsfp1_capture_aclk)
begin
if (rising_edge(qsfp1_capture_aclk)) then
qsfp1_axis_aresetn_r <= qsfp1_axis_aresetn_r(1 to 15) & '1';
end if;
end process;
qsfp1_capture_aresetn <= qsfp1_axis_aresetn_r(0);
adc_rx_tvalid_128b_ena <= adc_rx_tvalid_128b and qsfp1_capture_rx_data_ready;
i_qsfp4_playback_intfc : entity work.qsfp4_playback_intfc
port map (
rx_device_clk_in => rx_device_clk_1,
rx_device_clk_aresetn_in => rx_device_clk_aresetn,
rx_tdata_128b_in => adc_rx_tdata_128b,
rx_tvalid_128b_in => adc_rx_tvalid_128b_ena,
rx_tready_128b_out => adc_rx_tready_128b,
rx_tvalid_128b_cnt_out => adc_rx_tvalid_128b_cnt,
rx_tvalid_128b_en_cnt_out => open,
playback_data_path_enable_n_in => playback_data_path_enable_n,
qsfp4_playback_aclk_in => qsfp4_playback_aclk,
qsfp4_playback_aresetn_in => qsfp4_playback_aresetn,
qsfp4_playback_tdata_240b_out => qsfp4_playback_tdata_240b,
qsfp4_playback_tvalid_240b_out => qsfp4_playback_tvalid_240b,
qsfp4_playback_tready_240b_in => qsfp4_playback_tready_240b,
qsfp4_playback_tvalid_240b_cnt_out => open,
cnt_reset_in => '0'
);
--///////////////////////////////
qsfp1_capture_aclk <= qsfp4_playback_aclk; --
qsfp1_capture_tdata_240b <= qsfp4_playback_tdata_240b; --
qsfp1_capture_tvalid_240b <= qsfp4_playback_tvalid_240b; --
--///////////////////////////////
--// ****>>>> FROM QSFP1 CAPTURE INTERFACE
i_qsfp1_capture_intfc : entity work.qsfp1_capture_intfc
port map (
qsfp1_capture_aclk_in => qsfp1_capture_aclk,
qsfp1_capture_aresetn_in => qsfp1_capture_aresetn,
qsfp1_capture_tdata_240b_in => qsfp1_capture_tdata_240b,
qsfp1_capture_tvalid_240b_in => qsfp1_capture_tvalid_240b,
qsfp1_capture_tvalid_240b_cnt_out => open,
qsfp1_capture_fifo_aempty_512b_cnt_out => open,
qsfp1_capture_iq_240b_to_512b_overflow_cnt_out => open,
qsfp1_capture_rx_data_ready_out => qsfp1_capture_rx_data_ready,
qsfp1_capture_rx_data_ready_cnt_out => open,
tx_device_clk_in => tx_device_clk_1,
tx_device_clk_aresetn_in => tx_device_clk_aresetn,
tx_tdata_128b_out => tx_tdata_128b, -- out
tx_tvalid_128b_out => tx_tvalid_128b, -- out
tx_tready_128b_in => tx_tready_128b, -- in
tx_tvalid_128b_cnt_out => open,
cnt_reset_in => '0'
);
-- Stimulus process
stim_proc: process
begin
wait until rx_device_clk_aresetn = '1';
wait for 200 ns;
wait until rising_edge(rx_device_clk_1);
adc_rx_tvalid_128b <= '1';
wait for 500 ns;
wait until rising_edge(rx_device_clk_1);
playback_data_path_enable_n <= '0';
wait for 5 us;
wait until rising_edge(qsfp4_playback_aclk);
playback_data_path_enable_n <='0';
wait for 5 us;
wait until rising_edge(qsfp4_playback_aclk);
qsfp4_playback_tready_240b <='1';
wait; -- wait here forever
end process;
end;
sim/tb_cap_plybk_behav.wcfg
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_cap_plybk_behav.wdb" id="1">
<top_modules>
<top_module name="\$unit_xpm_cdc_sv_220102727 " />
<top_module name="glbl" />
<top_module name="tb_cap_plybk" />
<top_module name="vcomponents" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
<ZoomEndTime time="16.000001 us"></ZoomEndTime>
<Cursor1Time time="1.268070 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="375"></NameColumnWidth>
<ValueColumnWidth column_width="73"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="29" />
<wvobject type="logic" fp_name="/tb_cap_plybk/rx_device_clk_1">
<obj_property name="ElementShortName">rx_device_clk_1</obj_property>
<obj_property name="ObjectShortName">rx_device_clk_1</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/rx_device_clk_aresetn_r">
<obj_property name="ElementShortName">rx_device_clk_aresetn_r[0:15]</obj_property>
<obj_property name="ObjectShortName">rx_device_clk_aresetn_r[0:15]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/rx_device_clk_aresetn">
<obj_property name="ElementShortName">rx_device_clk_aresetn</obj_property>
<obj_property name="ObjectShortName">rx_device_clk_aresetn</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_aclk">
<obj_property name="ElementShortName">qsfp4_playback_aclk</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_aclk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/qsfp4_axis_aresetn_r">
<obj_property name="ElementShortName">qsfp4_axis_aresetn_r[0:15]</obj_property>
<obj_property name="ObjectShortName">qsfp4_axis_aresetn_r[0:15]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_aresetn">
<obj_property name="ElementShortName">qsfp4_playback_aresetn</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_aresetn</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/adc_rx_tdata_128b">
<obj_property name="ElementShortName">adc_rx_tdata_128b[127:0]</obj_property>
<obj_property name="ObjectShortName">adc_rx_tdata_128b[127:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tvalid_128b">
<obj_property name="ElementShortName">adc_rx_tvalid_128b</obj_property>
<obj_property name="ObjectShortName">adc_rx_tvalid_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tready_128b">
<obj_property name="ElementShortName">adc_rx_tready_128b</obj_property>
<obj_property name="ObjectShortName">adc_rx_tready_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tdata_128b_overflow">
<obj_property name="ElementShortName">adc_rx_tdata_128b_overflow</obj_property>
<obj_property name="ObjectShortName">adc_rx_tdata_128b_overflow</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/rx_tvalid_128b_cnt_out">
<obj_property name="ElementShortName">rx_tvalid_128b_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">rx_tvalid_128b_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/rx_tvalid_128b_en_cnt_out">
<obj_property name="ElementShortName">rx_tvalid_128b_en_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">rx_tvalid_128b_en_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/qsfp4_playback_tdata_240b">
<obj_property name="ElementShortName">qsfp4_playback_tdata_240b[239:0]</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tdata_240b[239:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/qsfp4_playback_tvalid_240b">
<obj_property name="ElementShortName">qsfp4_playback_tvalid_240b</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tvalid_240b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_tready_240b">
<obj_property name="ElementShortName">qsfp4_playback_tready_240b</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tready_240b</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/qsfp4_playback_tvalid_240b_cnt_out">
<obj_property name="ElementShortName">qsfp4_playback_tvalid_240b_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tvalid_240b_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/playback_data_path_enable_n">
<obj_property name="ElementShortName">playback_data_path_enable_n</obj_property>
<obj_property name="ObjectShortName">playback_data_path_enable_n</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/qsfp1_capture_tdata_240b">
<obj_property name="ElementShortName">qsfp1_capture_tdata_240b[239:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_tdata_240b[239:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp1_capture_tvalid_240b">
<obj_property name="ElementShortName">qsfp1_capture_tvalid_240b</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_tvalid_240b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp1_capture_rx_data_ready">
<obj_property name="ElementShortName">qsfp1_capture_rx_data_ready</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_rx_data_ready</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_rx_data_ready_cnt_out">
<obj_property name="ElementShortName">qsfp1_capture_rx_data_ready_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_rx_data_ready_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_fifo_aempty_512b_cnt_out">
<obj_property name="ElementShortName">qsfp1_capture_fifo_aempty_512b_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_fifo_aempty_512b_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_iq_240b_to_512b_overflow_cnt_out">
<obj_property name="ElementShortName">qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/tx_tdata_128b">
<obj_property name="ElementShortName">tx_tdata_128b[127:0]</obj_property>
<obj_property name="ObjectShortName">tx_tdata_128b[127:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/tx_tvalid_128b">
<obj_property name="ElementShortName">tx_tvalid_128b</obj_property>
<obj_property name="ObjectShortName">tx_tvalid_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/tx_tready_128b">
<obj_property name="ElementShortName">tx_tready_128b</obj_property>
<obj_property name="ObjectShortName">tx_tready_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_512b">
<obj_property name="ElementShortName">qsfp1_tready_512b</obj_property>
<obj_property name="ObjectShortName">qsfp1_tready_512b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_512b_pipe">
<obj_property name="ElementShortName">qsfp1_tready_512b_pipe</obj_property>
<obj_property name="ObjectShortName">qsfp1_tready_512b_pipe</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_128b">
<obj_property name="ElementShortName">qsfp1_tready_128b</obj_property>
<obj_property name="ObjectShortName">qsfp1_tready_128b</obj_property>
</wvobject>
</wave_config>
sim/test_bench.vhd
+188
View File
@@ -0,0 +1,188 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:22 03/24/2017
-- Design Name:
-- Module Name:
-- Project Name: xem7350
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dac_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
entity test_bench is
end test_bench;
architecture behavior of test_bench is
constant C_M_AXI_DATA_WIDTH : integer := 32;
constant C_M_AXI_ADDR_WIDTH : integer := 32;
-- Clock period definitions
constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
signal clk_125 : std_logic := '0';
signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_125_reset : std_logic;
signal clk_250 : std_logic := '0';
signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_250_areset : std_logic;
signal tx_device_clk_1 : std_logic := '0';
signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal tx_device_clk_aresetn : std_logic;
signal rx_device_clk_1 : std_logic := '0';
signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal rx_device_clk_aresetn : std_logic;
signal rx_device_clk_areset : std_logic;
signal qsfp4_axis_aclk : std_logic := '0';
signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp4_axis_aresetn : std_logic;
signal qsfp1_axis_aclk : std_logic := '0';
signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp1_axis_aresetn : std_logic;
--
signal tick_1ms : std_logic;
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
clk_125 <= not clk_125 after CLK_125_PERIOD/2;
clk_250 <= not clk_250 after CLK_250_PERIOD/2;
tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2;
rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2;
qsfp4_axis_aclk <= not qsfp4_axis_aclk after QSFP4_AXIS_ACLK_PERIOD/2;
qsfp1_axis_aclk <= not qsfp1_axis_aclk after QSFP1_AXIS_ACLK_PERIOD/2;
--
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
clk_125_reset <= not clk_125_aresetn(0);
--
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1';
end if;
end process;
clk_250_areset <= not clk_250_aresetn(0);
--
process(tx_device_clk_1)
begin
if (rising_edge(tx_device_clk_1)) then
tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1';
end if;
end process;
tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0);
------------------------------------------------
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 125
)
port map (
clk_in => clk_125,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => x"0000_0000",
prog_us_tick_out => open,
reset_in => clk_125_reset
);
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_125_tick_1ms_r(0 to 1) = "01") then
clk_125_freq_r <= clk_125_cnt_r;
clk_125_cnt_r <= (others => '0');
else
clk_125_cnt_r <= clk_125_cnt_r + 1;
end if;
end if;
end process;
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_250_tick_1ms_r(0 to 1) = "01") then
clk_250_freq_r <= clk_250_cnt_r;
clk_250_cnt_r <= (others => '0');
else
clk_250_cnt_r <= clk_250_cnt_r + 1;
end if;
end if;
end process;
end;