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moving repo from git to local repo

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This commit is contained in:
Nick Santana
2026-06-02 13:29:07 -04:00
commit e84a517056
152 changed files with 353024 additions and 0 deletions
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ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
Library xpm;
use xpm.vcomponents.all;
entity qsfp_init_fsm is
port(
clk_125_in : in std_logic;
clk_125_aresetn_in : in std_logic;
mode_50g_40g_n_in : in std_logic;
qsfp1_reset_n_in : in std_logic;
qsfp4_reset_n_in : in std_logic;
cmd_strb_out : out std_logic;
cmd_addr_out : out std_logic_vector(11 downto 0);
cmd_write_out : out std_logic;
cmd_sel_out : out std_logic_vector( 2 downto 0);
cmd_wdata_out : out std_logic_vector(31 downto 0);
cmd_ready_in : in std_logic;
fsm_running_out : out std_logic
);
end entity qsfp_init_fsm;
architecture imp of qsfp_init_fsm is
type fsm_state is (IDLE, QSFP1_INIT_WAIT, QSFP1_INIT, QSFP4_INIT_WAIT, QSFP4_INIT, DONE, ERROR);
signal state_r : fsm_state := IDLE;
signal state_cnt_r : integer := 0;
signal qsfp1_reset_n : std_logic_vector(0 to 0);
signal qsfp1_reset_b : std_logic_vector(0 to 0);
signal qsfp1_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
signal qsfp4_reset_n : std_logic_vector(0 to 0);
signal qsfp4_reset_b : std_logic_vector(0 to 0);
signal qsfp4_reset_n_r : std_logic_vector(0 to 31) := x"0000_0000";
signal qsfp1_reset_r : std_logic := '0';
signal qsfp4_reset_r : std_logic := '0';
signal cmd_addr_r : std_logic_vector (11 downto 0) := (others => '0');
signal cmd_sel_r : std_logic_vector ( 2 downto 0) := (others => '0');
signal cmd_strb_r : std_logic := '0';
signal cmd_wdata_r : std_logic_vector (31 downto 0) := (others => '0');
signal cmd_write_r : std_logic := '0';
signal fsm_running_r : std_logic := '0';
begin
cmd_strb_out <= cmd_strb_r;
cmd_addr_out <= cmd_addr_r;
cmd_write_out <= cmd_write_r;
cmd_sel_out <= cmd_sel_r;
cmd_wdata_out <= cmd_wdata_r;
fsm_running_out <= fsm_running_r;
--
qsfp1_reset_n(0) <= qsfp1_reset_n_in;
i_cdc_qsfp1_reset_n : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 1 -- DECIMAL; range: 1-1024
)
port map (
dest_out => qsfp1_reset_b,
dest_clk => clk_125_in,
src_clk => '0',
src_in => qsfp1_reset_n
);
process(clk_125_in)
begin
if (rising_edge(clk_125_in)) then
qsfp1_reset_n_r <= qsfp1_reset_n_r(1 to 31) & qsfp1_reset_b(0);
end if;
end process;
--
qsfp4_reset_n(0) <= qsfp4_reset_n_in;
i_cdc_qsfp4_reset_n : xpm_cdc_array_single
generic map (
DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
SRC_INPUT_REG => 0, -- DECIMAL; 0=do not register input, 1=register input
WIDTH => 1 -- DECIMAL; range: 1-1024
)
port map (
dest_out => qsfp4_reset_b,
dest_clk => clk_125_in,
src_clk => '0',
src_in => qsfp4_reset_n
);
process(clk_125_in)
begin
if (rising_edge(clk_125_in)) then
qsfp4_reset_n_r <= qsfp4_reset_n_r(1 to 31) & qsfp4_reset_b(0);
end if;
end process;
process(clk_125_in)
begin
if (clk_125_aresetn_in = '0') then
qsfp1_reset_r <= '0';
qsfp4_reset_r <= '0';
cmd_sel_r <= (others => '0');
cmd_addr_r <= (others => '0');
cmd_wdata_r <= (others => '0');
cmd_write_r <= '0';
cmd_strb_r <= '0';
state_cnt_r <= 0;
state_r <= IDLE;
elsif (rising_edge(clk_125_in)) then
cmd_strb_r <= '0';
if (qsfp1_reset_n_r(1) = '1' and qsfp1_reset_n_r(0) = '0') then
qsfp1_reset_r <= '1';
end if;
if (qsfp4_reset_n_r(1) = '1' and qsfp4_reset_n_r(0) = '0') then
qsfp4_reset_r <= '1';
end if;
case (state_r) is
when IDLE =>
if (qsfp1_reset_r = '1') then
fsm_running_r <= '1';
cmd_sel_r <= "000";
cmd_addr_r <= x"001";
if (mode_50g_40g_n_in = '1') then
cmd_wdata_r <= x"0000_0001";
else
cmd_wdata_r <= x"0000_0011";
end if;
cmd_write_r <= '1';
cmd_strb_r <= '1';
state_cnt_r <= 0;
state_r <= QSFP1_INIT_WAIT;
elsif (qsfp4_reset_r = '1') then
fsm_running_r <= '1';
cmd_sel_r <= "001";
cmd_addr_r <= x"001";
if (mode_50g_40g_n_in = '1') then
cmd_wdata_r <= x"0000_0001";
else
cmd_wdata_r <= x"0000_0011";
end if;
cmd_write_r <= '1';
cmd_strb_r <= '1';
state_cnt_r <= 0;
state_r <= QSFP4_INIT_WAIT;
else
fsm_running_r <= '0';
state_r <= IDLE;
end if;
when QSFP1_INIT_WAIT =>
if (state_cnt_r = 8) then
state_cnt_r <= 0;
state_r <= QSFP1_INIT;
else
state_cnt_r <= state_cnt_r + 1;
state_r <= QSFP1_INIT_WAIT;
end if;
when QSFP1_INIT =>
if (state_cnt_r = 32) then
qsfp1_reset_r <= '0';
state_r <= ERROR;
else
state_cnt_r <= state_cnt_r + 1;
if (cmd_ready_in = '1') then
qsfp1_reset_r <= '0';
state_r <= DONE;
else
state_r <= QSFP1_INIT;
end if;
end if;
when QSFP4_INIT_WAIT =>
if (state_cnt_r = 8) then
state_cnt_r <= 0;
state_r <= QSFP4_INIT;
else
state_cnt_r <= state_cnt_r + 1;
state_r <= QSFP4_INIT_WAIT;
end if;
when QSFP4_INIT =>
if (state_cnt_r = 32) then
qsfp4_reset_r <= '0';
state_r <= ERROR;
else
state_cnt_r <= state_cnt_r + 1;
if (cmd_ready_in = '1') then
qsfp4_reset_r <= '0';
state_r <= DONE;
else
state_r <= QSFP4_INIT;
end if;
end if;
when DONE =>
cmd_write_r <= '0';
state_r <= IDLE;
when ERROR =>
cmd_write_r <= '0';
state_r <= IDLE;
when others =>
state_r <= IDLE;
end case;
end if;
end process;
end architecture imp;
ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd
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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity qsfp_intfc_v1_0 is
generic (
-- Users to add parameters here
FPGA_REVISION_DATE : std_logic_vector(31 downto 0) := x"0603_2024";
MINOR_REV : std_logic_vector( 7 downto 0) := x"01";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
clk_125_in : in std_logic;
clk_125_reset_n_in : in std_logic;
clk_250_in : in std_logic;
clk_250_reset_n_in : in std_logic;
rx_device_clk_in : in std_logic;
tx_device_clk_in : in std_logic;
clkin8_in : in std_logic;
-- sysref_in : in std_logic;
ref_clk_div2_in : in std_logic;
qsfp2_clk_in : in std_logic;
qsfp3_clk_in : in std_logic;
pl_clk3_0 : in std_logic;
QSFP1_SI570_CLOCK_P : in std_logic;
QSFP1_SI570_CLOCK_N : in std_logic;
QSFP1_TX1_P : out std_logic;
QSFP1_TX1_N : out std_logic;
QSFP1_RX1_P : in std_logic;
QSFP1_RX1_N : in std_logic;
--
QSFP1_TX2_P : out std_logic;
QSFP1_TX2_N : out std_logic;
QSFP1_RX2_P : in std_logic;
QSFP1_RX2_N : in std_logic;
--
QSFP1_TX3_P : out std_logic;
QSFP1_TX3_N : out std_logic;
QSFP1_RX3_P : in std_logic;
QSFP1_RX3_N : in std_logic;
--
QSFP1_TX4_P : out std_logic;
QSFP1_TX4_N : out std_logic;
QSFP1_RX4_P : in std_logic;
QSFP1_RX4_N : in std_logic;
QSFP1_RESETL_LS : out std_logic;
QSFP1_MODPRSL_LS : in std_logic;
QSFP1_INTL_LS : in std_logic;
-----------------
QSFP4_SI570_CLOCK_P : in std_logic;
QSFP4_SI570_CLOCK_N : in std_logic;
QSFP4_TX1_P : out std_logic;
QSFP4_TX1_N : out std_logic;
QSFP4_RX1_P : in std_logic;
QSFP4_RX1_N : in std_logic;
--
QSFP4_TX2_P : out std_logic;
QSFP4_TX2_N : out std_logic;
QSFP4_RX2_P : in std_logic;
QSFP4_RX2_N : in std_logic;
--
QSFP4_TX3_P : out std_logic;
QSFP4_TX3_N : out std_logic;
QSFP4_RX3_P : in std_logic;
QSFP4_RX3_N : in std_logic;
--
QSFP4_TX4_P : out std_logic;
QSFP4_TX4_N : out std_logic;
QSFP4_RX4_P : in std_logic;
QSFP4_RX4_N : in std_logic;
QSFP4_RESETL_LS : out std_logic;
QSFP4_MODPRSL_LS : in std_logic;
QSFP4_INTL_LS : in std_logic;
qsfp1_capture_aclk_out : out std_logic;
qsfp1_capture_aresetn_out : out std_logic;
qsfp1_capture_tdata_240b_out : out std_logic_vector(239 downto 0);
qsfp1_capture_tvalid_240b_out : out std_logic;
qsfp1_capture_rx_data_ready_in : in std_logic;
qsfp4_playback_aclk_out : out std_logic;
qsfp4_playback_aresetn_out : out std_logic;
qsfp4_playback_tdata_240b_in : in std_logic_vector(239 downto 0);
qsfp4_playback_tvalid_240b_in : in std_logic;
qsfp4_playback_tready_240b_out : out std_logic;
qsfp1_capture_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_capture_overflow_240b_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_capture_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_tx_fifo_128_aempty_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_capture_rx_data_ready_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
mem_xfer_tx_upload_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
dac_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
adc_rx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
adc_rx_tvalid_128b_overflow_cnt_in : in std_logic_vector(31 downto 0);
qsfp4_playback_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
qsfp4_playback_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
fiber_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
cnt_reset_out : out std_logic;
slv_reg9_out : out std_logic_vector(31 downto 0);
slv_reg10_out : out std_logic_vector(31 downto 0);
slv_reg21_out : out std_logic_vector(31 downto 0);
slv_reg22_out : out std_logic_vector(31 downto 0);
slv_reg23_out : out std_logic_vector(31 downto 0);
slv_reg24_out : out std_logic_vector(31 downto 0);
slv_reg25_out : out std_logic_vector(31 downto 0);
slv_reg26_out : out std_logic_vector(31 downto 0);
slv_reg27_out : out std_logic_vector(31 downto 0);
slv_reg28_out : out std_logic_vector(31 downto 0);
slv_reg29_out : out std_logic_vector(31 downto 0);
slv_reg30_out : out std_logic_vector(31 downto 0);
slv_reg31_out : out std_logic_vector(31 downto 0);
slv_reg32_out : out std_logic_vector(31 downto 0);
slv_reg33_out : out std_logic_vector(31 downto 0);
slv_reg34_out : out std_logic_vector(31 downto 0);
slv_reg35_out : out std_logic_vector(31 downto 0);
slv_reg36_out : out std_logic_vector(31 downto 0);
slv_reg37_out : out std_logic_vector(31 downto 0);
slv_reg38_out : out std_logic_vector(31 downto 0);
slv_reg39_out : out std_logic_vector(31 downto 0);
slv_reg40_out : out std_logic_vector(31 downto 0);
slv_reg41_out : out std_logic_vector(31 downto 0);
slv_reg42_out : out std_logic_vector(31 downto 0);
slv_reg43_out : out std_logic_vector(31 downto 0);
slv_reg44_out : out std_logic_vector(31 downto 0);
slv_reg45_out : out std_logic_vector(31 downto 0);
slv_reg46_out : out std_logic_vector(31 downto 0);
slv_reg47_out : out std_logic_vector(31 downto 0);
slv_reg48_out : out std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
sys_cpu_clk_in : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end qsfp_intfc_v1_0;
architecture arch_imp of qsfp_intfc_v1_0 is
signal fpga_revision_date_r : std_logic_vector(31 downto 0) := (others => '0');
attribute keep : string;
attribute keep of fpga_revision_date_r : signal is "true";
signal minor_rev_r : std_logic_vector( 7 downto 0) := (others => '0');
attribute keep of minor_rev_r : signal is "true";
signal dig_iq_cmd_addr_i : std_logic_vector (11 downto 0);
signal dig_iq_cmd_sel_i : std_logic_vector ( 2 downto 0);
signal dig_iq_cmd_strb_i : std_logic;
signal dig_iq_cmd_wdata_i : std_logic_vector (31 downto 0);
signal dig_iq_cmd_write_i : std_logic;
signal dig_iq_cmd_addr : std_logic_vector (11 downto 0);
signal dig_iq_cmd_rdata : std_logic_vector (31 downto 0);
signal dig_iq_cmd_ready : std_logic;
signal dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
signal dig_iq_cmd_strb : std_logic;
signal dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
signal dig_iq_cmd_write : std_logic;
signal dig_iq_interface_ready : std_logic_vector ( 1 downto 0);
signal dig_iq_interface_ready_r : std_logic_vector ( 1 downto 0) := (others => '0');
signal dig_iq_interface_ready_0_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal dig_iq_interface_ready_1_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal dig_iq_interface_reset : std_logic_vector ( 1 downto 0);
--
signal qsfp1_axis_aclk : std_logic;
signal qsfp1_axis_aresetn : std_logic;
signal qsfp1_rx_rxn : std_logic_vector(3 downto 0);
signal qsfp1_rx_rxp : std_logic_vector(3 downto 0);
signal qsfp1_tx_txn : std_logic_vector(3 downto 0);
signal qsfp1_tx_txp : std_logic_vector(3 downto 0);
signal qsfp1_reset_n : std_logic;
signal qsfp1_reset_n_i : std_logic;
signal qsfp1_modprsl : std_logic;
signal qsfp1_intl : std_logic;
signal qsfp1_m_axis_tdata : std_logic_vector(239 downto 0);
signal qsfp1_m_axis_tvalid : std_logic;
--
signal qsfp4_axis_aclk : std_logic;
signal qsfp4_axis_aresetn : std_logic;
signal qsfp4_rx_rxn : std_logic_vector(3 downto 0);
signal qsfp4_rx_rxp : std_logic_vector(3 downto 0);
signal qsfp4_tx_txn : std_logic_vector(3 downto 0);
signal qsfp4_tx_txp : std_logic_vector(3 downto 0);
signal qsfp4_reset_n : std_logic;
signal qsfp4_reset_n_i : std_logic;
signal qsfp4_modprsl : std_logic;
signal qsfp4_intl : std_logic;
signal qsfp4_s_axis_tready : std_logic;
--
signal tick_1ms : std_logic;
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp1_s_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal qsfp1_s_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp1_s_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp4_s_axis_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal qsfp4_s_axis_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp4_s_axis_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal rx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal rx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal tx_device_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal tx_device_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal tx_device_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clkin8_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clkin8_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clkin8_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal sys_cpu_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal sys_cpu_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal sys_cpu_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal ref_clk_div2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal ref_clk_div2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal ref_clk_div2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp2_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal qsfp2_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp2_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp3_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal qsfp3_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp3_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal slv_reg0 : std_logic_vector(31 downto 0);
signal slv_reg1 : std_logic_vector(31 downto 0);
signal slv_reg2 : std_logic_vector(31 downto 0);
signal slv_reg3 : std_logic_vector(31 downto 0);
signal slv_reg4 : std_logic_vector(31 downto 0);
signal slv_reg5 : std_logic_vector(31 downto 0);
signal slv_reg6 : std_logic_vector(31 downto 0);
signal slv_reg7 : std_logic_vector(31 downto 0);
signal slv_reg8 : std_logic_vector(31 downto 0);
signal cnt_rst_i : std_logic;
signal fsm_dig_iq_cmd_strb : std_logic;
signal fsm_dig_iq_cmd_addr : std_logic_vector (11 downto 0);
signal fsm_dig_iq_cmd_write : std_logic;
signal fsm_dig_iq_cmd_sel : std_logic_vector ( 2 downto 0);
signal fsm_dig_iq_cmd_wdata : std_logic_vector (31 downto 0);
signal fsm_running : std_logic;
signal clk_50 : std_logic;
signal clk_50_reset : std_logic_vector(0 to 15) := (others => '1');
signal pl_clk3_0_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal pl_clk3_0_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal pl_clk3_0_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
cnt_reset_out <= cnt_rst_i;
i_bufgce_div : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 2, -- 1-8
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
IS_CE_INVERTED => '0', -- Optional inversion for CE
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
IS_I_INVERTED => '0', -- Optional inversion for I
SIM_DEVICE => "ULTRASCALE_PLUS" -- ULTRASCALE, ULTRASCALE_PLUS
)
port map (
O => clk_50, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => sys_cpu_clk_in -- 1-bit input: Buffer
);
process(clk_50)
begin
if (rising_edge(clk_50)) then
clk_50_reset <= clk_50_reset(1 to 15) & '0';
end if;
end process;
-- Instantiation of Axi Bus Interface S00_AXI
qsfp_intfc_v1_0_S00_AXI_inst : entity work.qsfp_intfc_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
slv_reg0_in => slv_reg0, -- 0x8000_0000
slv_reg1_in => slv_reg1, -- 0x8000_0004
slv_reg2_in => slv_reg2, -- 0x8000_0008
slv_reg3_out => slv_reg3, -- 0x8000_000C
slv_reg4_out => slv_reg4, -- 0x8000_0010
slv_reg5_out => slv_reg5, -- 0x8000_0014
slv_reg6_out => slv_reg6, -- 0x8000_0018
slv_reg7_out => slv_reg7, -- 0x8000_001C
slv_reg8_out => slv_reg8, -- 0x8000_0020
slv_reg9_out => slv_reg9_out, -- 0x8000_0024
slv_reg10_out => slv_reg10_out, -- 0x8000_0028
slv_reg11_in => qsfp1_s_axis_aclk_freq_r, -- 0x8000_002C
slv_reg12_in => qsfp1_s_axis_aclk_cnt_r, -- 0x8000_0030
slv_reg13_in => qsfp4_s_axis_aclk_freq_r, -- 0x8000_0034
slv_reg14_in => qsfp4_s_axis_aclk_cnt_r, -- 0x8000_0038
slv_reg15_in => rx_device_clk_freq_r, -- 0x8000_003C
slv_reg16_in => tx_device_clk_freq_r, -- 0x8000_0040
slv_reg17_in => clk_125_freq_r, -- 0x8000_0044
slv_reg18_in => clk_125_cnt_r, -- 0x8000_0048
slv_reg19_in => clk_250_freq_r, -- 0x8000_004C
slv_reg20_in => clk_250_cnt_r, -- 0x8000_0050
slv_reg21_out => slv_reg21_out, -- 0x8000_0054
slv_reg22_out => slv_reg22_out, -- 0x8000_0058
slv_reg23_out => slv_reg23_out, -- 0x8000_005C *
slv_reg24_out => slv_reg24_out, -- 0x8000_0060
slv_reg25_out => slv_reg25_out, -- 0x8000_0064 *
slv_reg26_out => slv_reg26_out, -- 0x8000_0068 *
slv_reg27_out => slv_reg27_out, -- 0x8000_006C
slv_reg28_out => slv_reg28_out, -- 0x8000_0070
slv_reg29_out => slv_reg29_out, -- 0x8000_0074
slv_reg30_out => slv_reg30_out, -- 0x8000_0078
slv_reg31_out => slv_reg31_out, -- 0x8000_007C *
slv_reg32_out => slv_reg32_out, -- 0x8000_0080
slv_reg33_out => slv_reg33_out, -- 0x8000_0084 *
slv_reg34_out => slv_reg34_out, -- 0x8000_0088 *
slv_reg35_out => slv_reg35_out, -- 0x8000_008C
slv_reg36_out => slv_reg36_out, -- 0x8000_0090
slv_reg37_out => slv_reg37_out, -- 0x8000_0094
slv_reg38_out => slv_reg38_out, -- 0x8000_0098
slv_reg39_out => slv_reg39_out, -- 0x8000_009C *
slv_reg40_out => slv_reg40_out, -- 0x8000_00A0
slv_reg41_out => slv_reg41_out, -- 0x8000_00A4 *
slv_reg42_out => slv_reg42_out, -- 0x8000_00A8 *
slv_reg43_out => slv_reg43_out, -- 0x8000_00AC
slv_reg44_out => slv_reg44_out, -- 0x8000_00B0
slv_reg45_out => slv_reg45_out, -- 0x8000_00B4
slv_reg46_out => slv_reg46_out, -- 0x8000_00B8
slv_reg47_out => slv_reg47_out, -- 0x8000_00BC *
slv_reg48_out => slv_reg48_out, -- 0x8000_00C0
slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4 *
slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8 *
slv_reg51_in => dig_iq_interface_ready_1_cnt_r, -- 0x8000_00CC
slv_reg52_in => adc_rx_tvalid_128b_overflow_cnt_in, -- 0x8000_00D0
slv_reg53_in => qsfp4_playback_tvalid_240b_cnt_in, -- 0x8000_00D4
slv_reg54_in => qsfp1_capture_overflow_240b_cnt_in, -- 0x8000_00D8
slv_reg55_in => qsfp4_playback_tvalid_128b_cnt_in, -- 0x8000_00DC
slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0
slv_reg57_in => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 0x8000_00E4
slv_reg58_in => adc_rx_tvalid_128b_cnt_in, -- 0x8000_00E8
slv_reg59_in => fiber_tx_tvalid_128b_cnt_in, -- 0x8000_00EC
slv_reg60_in => dac_tx_tvalid_128b_cnt_in, -- 0x8000_00F0
slv_reg61_in => qsfp1_capture_tvalid_240b_cnt_in, -- 0x8000_00F4
slv_reg62_in => qsfp1_tx_fifo_128_aempty_cnt_in, -- 0x8000_00F8
slv_reg63_in => qsfp1_capture_rx_data_ready_cnt_in, -- 0x8000_00FC
S_AXI_ACLK => sys_cpu_clk_in,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
--
slv_reg0 <= fpga_revision_date_r; -- 0x8000_0000
--
slv_reg1(0) <= dig_iq_interface_ready(0); -- 0x8000_0004
slv_reg1(1) <= qsfp1_modprsl;
slv_reg1(2) <= qsfp1_intl;
slv_reg1(3) <= '0';
slv_reg1(4) <= '0'; --dig_iq_interface_ready_1(0);
slv_reg1(5) <= '1'; --qsfp2_modprsl;
slv_reg1(6) <= '1'; --qsfp2_intl;
slv_reg1(7) <= '0';
slv_reg1(8) <= '0'; --dig_iq_interface_ready_1(1);
slv_reg1(9) <= '1'; --qsfp3_modprsl;
slv_reg1(10) <= '1'; --qsfp3_intl;
slv_reg1(11) <= '0';
slv_reg1(12) <= dig_iq_interface_ready(1);
slv_reg1(13) <= qsfp4_modprsl;
slv_reg1(14) <= qsfp4_intl;
slv_reg1(15) <= '0';
slv_reg1(23 downto 16) <= (others => '0');
slv_reg1(31 downto 24) <= minor_rev_r;
--
slv_reg2 <= dig_iq_cmd_rdata; -- 0x8000_0008
--
dig_iq_cmd_addr_i <= slv_reg3(11 downto 0); -- 0x8000_000C
--
dig_iq_cmd_sel_i <= slv_reg4( 2 downto 0); -- 0x8000_0010
--
dig_iq_cmd_strb_i <= slv_reg5(0); -- 0x8000_0014
qsfp1_reset_n_i <= slv_reg5(16);
qsfp4_reset_n_i <= slv_reg5(24);
--
dig_iq_cmd_wdata_i <= slv_reg6(31 downto 0); -- 0x8000_0018
--
dig_iq_cmd_write_i <= slv_reg7(0); -- 0x8000_001C
--
-- <= slv_reg8(0); -- 0x8000_0020
-- <= slv_reg8(24);
-- <= slv_reg8(28);
cnt_rst_i <= slv_reg8(31);
-- Add user logic here
QSFP1_TX1_P <= qsfp1_tx_txp(0);
QSFP1_TX1_N <= qsfp1_tx_txn(0);
qsfp1_rx_rxp(0) <= QSFP1_RX1_P;
qsfp1_rx_rxn(0) <= QSFP1_RX1_N;
QSFP1_TX2_P <= qsfp1_tx_txp(1);
QSFP1_TX2_N <= qsfp1_tx_txn(1);
qsfp1_rx_rxp(1) <= QSFP1_RX2_P;
qsfp1_rx_rxn(1) <= QSFP1_RX2_N;
QSFP1_TX3_P <= qsfp1_tx_txp(2);
QSFP1_TX3_N <= qsfp1_tx_txn(2);
qsfp1_rx_rxp(2) <= QSFP1_RX3_P;
qsfp1_rx_rxn(2) <= QSFP1_RX3_N;
QSFP1_TX4_P <= qsfp1_tx_txp(3);
QSFP1_TX4_N <= qsfp1_tx_txn(3);
qsfp1_rx_rxp(3) <= QSFP1_RX4_P;
qsfp1_rx_rxn(3) <= QSFP1_RX4_N;
QSFP1_RESETL_LS <= qsfp1_reset_n;
qsfp1_modprsl <= QSFP1_MODPRSL_LS;
qsfp1_intl <= QSFP1_INTL_LS;
-------
QSFP4_TX1_P <= qsfp4_tx_txp(0);
QSFP4_TX1_N <= qsfp4_tx_txn(0);
qsfp4_rx_rxp(0) <= QSFP4_RX1_P;
qsfp4_rx_rxn(0) <= QSFP4_RX1_N;
QSFP4_TX2_P <= qsfp4_tx_txp(1);
QSFP4_TX2_N <= qsfp4_tx_txn(1);
qsfp4_rx_rxp(1) <= QSFP4_RX2_P;
qsfp4_rx_rxn(1) <= QSFP4_RX2_N;
QSFP4_TX3_P <= qsfp4_tx_txp(2);
QSFP4_TX3_N <= qsfp4_tx_txn(2);
qsfp4_rx_rxp(2) <= QSFP4_RX3_P;
qsfp4_rx_rxn(2) <= QSFP4_RX3_N;
QSFP4_TX4_P <= qsfp4_tx_txp(3);
QSFP4_TX4_N <= qsfp4_tx_txn(3);
qsfp4_rx_rxp(3) <= QSFP4_RX4_P;
qsfp4_rx_rxn(3) <= QSFP4_RX4_N;
QSFP4_RESETL_LS <= qsfp4_reset_n;
qsfp4_modprsl <= QSFP4_MODPRSL_LS;
qsfp4_intl <= QSFP4_INTL_LS;
dig_iq_cmd_strb <= fsm_dig_iq_cmd_strb when fsm_running = '1' else dig_iq_cmd_strb_i;
dig_iq_cmd_addr <= fsm_dig_iq_cmd_addr when fsm_running = '1' else dig_iq_cmd_addr_i;
dig_iq_cmd_write <= fsm_dig_iq_cmd_write when fsm_running = '1' else dig_iq_cmd_write_i;
dig_iq_cmd_sel <= fsm_dig_iq_cmd_sel when fsm_running = '1' else dig_iq_cmd_sel_i;
dig_iq_cmd_wdata <= fsm_dig_iq_cmd_wdata when fsm_running = '1' else dig_iq_cmd_wdata_i;
qsfp1_reset_n <= qsfp1_reset_n_i;
dig_iq_interface_reset(0) <= not qsfp1_reset_n;
qsfp4_reset_n <= qsfp4_reset_n_i;
dig_iq_interface_reset(1) <= not qsfp4_reset_n;
i_qsfp_int_fsm : entity work.qsfp_init_fsm
port map (
clk_125_in => clk_125_in,
clk_125_aresetn_in => clk_125_reset_n_in,
mode_50g_40g_n_in => '1',
qsfp1_reset_n_in => qsfp1_reset_n,
qsfp4_reset_n_in => qsfp4_reset_n,
cmd_strb_out => fsm_dig_iq_cmd_strb,
cmd_addr_out => fsm_dig_iq_cmd_addr,
cmd_write_out => fsm_dig_iq_cmd_write,
cmd_sel_out => fsm_dig_iq_cmd_sel,
cmd_wdata_out => fsm_dig_iq_cmd_wdata,
cmd_ready_in => dig_iq_cmd_ready,
fsm_running_out => fsm_running
);
------------------------------------------------------
i_dig_iq_x2 : entity work.dig_iq_x2
port map(
--
clk_125_resetn_in => clk_125_reset_n_in,
clk_125_in => clk_125_in,
--
aclk_in => clk_250_in,
aresetn_in => clk_250_reset_n_in,
cmd_strb_in => dig_iq_cmd_strb,
cmd_addr_in => dig_iq_cmd_addr,
cmd_write_in => dig_iq_cmd_write,
cmd_sel_in => dig_iq_cmd_sel,
cmd_wdata_in => dig_iq_cmd_wdata,
cmd_ready_out => dig_iq_cmd_ready,
cmd_rdata_out => dig_iq_cmd_rdata,
dig_iq_interface_reset_in => dig_iq_interface_reset,
--
dig_iq_interface_ready_out => dig_iq_interface_ready,
--
rx_data_ready_in => qsfp1_capture_rx_data_ready_in,
axis_0_aclk_out => qsfp1_axis_aclk,
axis_0_aresetn_out => qsfp1_axis_aresetn,
m0_axis_tdata_out => qsfp1_m_axis_tdata,
m0_axis_tvalid_out => qsfp1_m_axis_tvalid,
s0_axis_tdata_in => (others =>'0'),
s0_axis_tvalid_in => '0',
s0_axis_tready_out => open,
--
axis_1_aclk_out => qsfp4_axis_aclk,
axis_1_aresetn_out => qsfp4_axis_aresetn,
m1_axis_tdata_out => open,
m1_axis_tvalid_out => open,
s1_axis_tdata_in => qsfp4_playback_tdata_240b_in,
s1_axis_tvalid_in => qsfp4_playback_tvalid_240b_in,
s1_axis_tready_out => qsfp4_s_axis_tready,
tx_data_channel_reset_in => '0',
tx_data_clear_in => '0',
--
qsfp0_ref_clk_p_in => QSFP1_SI570_CLOCK_P,
qsfp0_ref_clk_n_in => QSFP1_SI570_CLOCK_N,
qsfp0_rx_rxp_in => qsfp1_rx_rxp,
qsfp0_rx_rxn_in => qsfp1_rx_rxn,
qsfp0_tx_txp_out => qsfp1_tx_txp,
qsfp0_tx_txn_out => qsfp1_tx_txn,
--
qsfp1_ref_clk_p_in => QSFP4_SI570_CLOCK_P,
qsfp1_ref_clk_n_in => QSFP4_SI570_CLOCK_N,
qsfp1_rx_rxp_in => qsfp4_rx_rxp,
qsfp1_rx_rxn_in => qsfp4_rx_rxn,
qsfp1_tx_txp_out => qsfp4_tx_txp,
qsfp1_tx_txn_out => qsfp4_tx_txn
);
qsfp1_capture_aclk_out <= qsfp1_axis_aclk;
qsfp1_capture_aresetn_out <= qsfp1_axis_aresetn;
qsfp1_capture_tdata_240b_out <= qsfp1_m_axis_tdata;
qsfp1_capture_tvalid_240b_out <= qsfp1_m_axis_tvalid;
-- i_ila_3_qsfp1 : entity work.ila_3
-- port map (
-- clk => qsfp1_axis_aclk,
-- probe0(0) => qsfp1_m_axis_tvalid, --1
-- probe1(0) => '0', --1
-- probe2 => qsfp1_m_axis_tdata(31 downto 0), --32
-- probe3 => qsfp1_m_axis_tdata(63 downto 32), --32
-- probe4 => qsfp1_m_axis_tdata(95 downto 64), --32
-- probe5 => qsfp1_m_axis_tdata(127 downto 96), --32
-- probe6 => qsfp1_m_axis_tdata(159 downto 128), --32
-- probe7 => qsfp1_m_axis_tdata(191 downto 160), --32
-- probe8 => qsfp1_m_axis_tdata(223 downto 192), --32
-- probe9 => qsfp1_m_axis_tdata(239 downto 224) --16
-- );
--------------------------------------------------------------------------------------------
qsfp4_playback_aclk_out <= qsfp4_axis_aclk;
qsfp4_playback_aresetn_out <= qsfp4_axis_aresetn;
qsfp4_playback_tready_240b_out <= qsfp4_s_axis_tready;
-- i_ila_3_qsfp4 : entity work.ila_3
-- port map (
-- clk => qsfp4_axis_aclk,
-- probe0(0) => qsfp4_playback_tvalid_240b_in, --1
-- probe1(0) => qsfp4_s_axis_tready, --1
-- probe2 => qsfp4_playback_tdata_240b_in(31 downto 0), --32
-- probe3 => qsfp4_playback_tdata_240b_in(63 downto 32), --32
-- probe4 => qsfp4_playback_tdata_240b_in(95 downto 64), --32
-- probe5 => qsfp4_playback_tdata_240b_in(127 downto 96), --32
-- probe6 => qsfp4_playback_tdata_240b_in(159 downto 128), --32
-- probe7 => qsfp4_playback_tdata_240b_in(191 downto 160), --32
-- probe8 => qsfp4_playback_tdata_240b_in(223 downto 192), --32
-- probe9 => qsfp4_playback_tdata_240b_in(239 downto 224) --16
-- );
------------------------------------------------
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 50
)
port map (
clk_in => clk_50,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => x"0000_0000",
prog_us_tick_out => open,
reset_in => clk_50_reset(0)
);
process(clk_50)
begin
if (rising_edge(clk_50)) then
fpga_revision_date_r <= FPGA_REVISION_DATE;
minor_rev_r <= MINOR_REV;
end if;
end process;
-- i_vio_0 : entity work.vio_0_1
-- port map (
-- clk => clk_50,
-- probe_in0 => fpga_revision_date_r, -- 32
-- probe_in1 => minor_rev_r, -- 8
-- probe_in2 => clk_125_freq_r, -- 32
-- probe_in3 => clk_125_cnt_r, -- 32
-- probe_in4 => clk_250_freq_r, -- 32
-- probe_in5 => clk_250_cnt_r, -- 32
-- probe_in6 => qsfp1_s_axis_aclk_freq_r, -- 32
-- probe_in7 => qsfp1_s_axis_aclk_cnt_r, -- 32
-- probe_in8 => qsfp4_s_axis_aclk_freq_r, -- 32
-- probe_in9 => qsfp4_s_axis_aclk_cnt_r, -- 32
-- probe_in10 => rx_device_clk_freq_r, -- 32
-- probe_in11 => rx_device_clk_cnt_r, -- 32
-- probe_in12 => tx_device_clk_freq_r, -- 32
-- probe_in13 => tx_device_clk_cnt_r, -- 32
-- probe_in14 => clkin8_freq_r, -- 32
-- probe_in15 => clkin8_cnt_r, -- 32
-- probe_in16 => sys_cpu_clk_freq_r, -- 32
-- probe_in17 => sys_cpu_clk_cnt_r, -- 32
-- probe_in18 => ref_clk_div2_freq_r, -- 32
-- probe_in19 => ref_clk_div2_cnt_r, -- 32
-- probe_in20 => qsfp2_clk_freq_r, -- 32
-- probe_in21 => qsfp2_clk_cnt_r, -- 32
-- probe_in22 => qsfp3_clk_freq_r, -- 32
-- probe_in23 => qsfp3_clk_cnt_r, -- 32
-- probe_in24 => pl_clk3_0_freq_r -- 32
-- );
process(clk_125_in)
begin
if (rising_edge(clk_125_in)) then
dig_iq_interface_ready_r <= dig_iq_interface_ready;
if (clk_125_reset_n_in = '0' or cnt_rst_i = '1') then
dig_iq_interface_ready_0_cnt_r <= (others => '0');
elsif (dig_iq_interface_ready(0) = '1' and dig_iq_interface_ready_r(0) = '0') then
dig_iq_interface_ready_0_cnt_r <= dig_iq_interface_ready_0_cnt_r + 1;
end if;
if (clk_125_reset_n_in = '0' or cnt_rst_i = '1') then
dig_iq_interface_ready_1_cnt_r <= (others => '0');
elsif (dig_iq_interface_ready(1) = '1' and dig_iq_interface_ready_r(1) = '0') then
dig_iq_interface_ready_1_cnt_r <= dig_iq_interface_ready_1_cnt_r + 1;
end if;
end if;
end process;
process(clk_125_in)
begin
if (rising_edge(clk_125_in)) then
clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_125_tick_1ms_r(0 to 1) = "01") then
clk_125_freq_r <= clk_125_cnt_r;
clk_125_cnt_r <= (others => '0');
else
clk_125_cnt_r <= clk_125_cnt_r + 1;
end if;
end if;
end process;
process(clk_250_in)
begin
if (rising_edge(clk_250_in)) then
clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_250_tick_1ms_r(0 to 1) = "01") then
clk_250_freq_r <= clk_250_cnt_r;
clk_250_cnt_r <= (others => '0');
else
clk_250_cnt_r <= clk_250_cnt_r + 1;
end if;
end if;
end process;
process(qsfp1_axis_aclk)
begin
if (rising_edge(qsfp1_axis_aclk)) then
qsfp1_s_axis_aclk_tick_1ms_r <= qsfp1_s_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (qsfp1_s_axis_aclk_tick_1ms_r(0 to 1) = "01") then
qsfp1_s_axis_aclk_freq_r <= qsfp1_s_axis_aclk_cnt_r;
qsfp1_s_axis_aclk_cnt_r <= (others => '0');
else
qsfp1_s_axis_aclk_cnt_r <= qsfp1_s_axis_aclk_cnt_r + 1;
end if;
end if;
end process;
process(qsfp4_axis_aclk)
begin
if (rising_edge(qsfp4_axis_aclk)) then
qsfp4_s_axis_aclk_tick_1ms_r <= qsfp4_s_axis_aclk_tick_1ms_r(1 to 2) & tick_1ms;
if (qsfp4_s_axis_aclk_tick_1ms_r(0 to 1) = "01") then
qsfp4_s_axis_aclk_freq_r <= qsfp4_s_axis_aclk_cnt_r;
qsfp4_s_axis_aclk_cnt_r <= (others => '0');
else
qsfp4_s_axis_aclk_cnt_r <= qsfp4_s_axis_aclk_cnt_r + 1;
end if;
end if;
end process;
process(rx_device_clk_in)
begin
if (rising_edge(rx_device_clk_in)) then
rx_device_clk_tick_1ms_r <= rx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (rx_device_clk_tick_1ms_r(0 to 1) = "01") then
rx_device_clk_freq_r <= rx_device_clk_cnt_r;
rx_device_clk_cnt_r <= (others => '0');
else
rx_device_clk_cnt_r <= rx_device_clk_cnt_r + 1;
end if;
end if;
end process;
process(tx_device_clk_in)
begin
if (rising_edge(tx_device_clk_in)) then
tx_device_clk_tick_1ms_r <= tx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (tx_device_clk_tick_1ms_r(0 to 1) = "01") then
tx_device_clk_freq_r <= tx_device_clk_cnt_r;
tx_device_clk_cnt_r <= (others => '0');
else
tx_device_clk_cnt_r <= tx_device_clk_cnt_r + 1;
end if;
end if;
end process;
process(clkin8_in)
begin
if (rising_edge(clkin8_in)) then
clkin8_tick_1ms_r <= clkin8_tick_1ms_r(1 to 2) & tick_1ms;
if (clkin8_tick_1ms_r(0 to 1) = "01") then
clkin8_freq_r <= clkin8_cnt_r;
clkin8_cnt_r <= (others => '0');
else
clkin8_cnt_r <= clkin8_cnt_r + 1;
end if;
end if;
end process;
process(sys_cpu_clk_in)
begin
if (rising_edge(sys_cpu_clk_in)) then
sys_cpu_clk_tick_1ms_r <= sys_cpu_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (sys_cpu_clk_tick_1ms_r(0 to 1) = "01") then
sys_cpu_clk_freq_r <= sys_cpu_clk_cnt_r;
sys_cpu_clk_cnt_r <= (others => '0');
else
sys_cpu_clk_cnt_r <= sys_cpu_clk_cnt_r + 1;
end if;
end if;
end process;
process(ref_clk_div2_in)
begin
if (rising_edge(ref_clk_div2_in)) then
ref_clk_div2_tick_1ms_r <= ref_clk_div2_tick_1ms_r(1 to 2) & tick_1ms;
if (ref_clk_div2_tick_1ms_r(0 to 1) = "01") then
ref_clk_div2_freq_r <= ref_clk_div2_cnt_r;
ref_clk_div2_cnt_r <= (others => '0');
else
ref_clk_div2_cnt_r <= ref_clk_div2_cnt_r + 1;
end if;
end if;
end process;
process(qsfp2_clk_in)
begin
if (rising_edge(qsfp2_clk_in)) then
qsfp2_clk_tick_1ms_r <= qsfp2_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (qsfp2_clk_tick_1ms_r(0 to 1) = "01") then
qsfp2_clk_freq_r <= qsfp2_clk_cnt_r;
qsfp2_clk_cnt_r <= (others => '0');
else
qsfp2_clk_cnt_r <= qsfp2_clk_cnt_r + 1;
end if;
end if;
end process;
process(qsfp3_clk_in)
begin
if (rising_edge(qsfp3_clk_in)) then
qsfp3_clk_tick_1ms_r <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then
qsfp3_clk_freq_r <= qsfp3_clk_cnt_r;
qsfp3_clk_cnt_r <= (others => '0');
else
qsfp3_clk_cnt_r <= qsfp3_clk_cnt_r + 1;
end if;
end if;
end process;
process(pl_clk3_0)
begin
if (rising_edge(pl_clk3_0)) then
pl_clk3_0_tick_1ms_r <= pl_clk3_0_tick_1ms_r(1 to 2) & tick_1ms;
if (pl_clk3_0_tick_1ms_r(0 to 1) = "01") then
pl_clk3_0_freq_r <= pl_clk3_0_cnt_r;
pl_clk3_0_cnt_r <= (others => '0');
else
pl_clk3_0_cnt_r <= pl_clk3_0_cnt_r + 1;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd
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