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Nick Santana
2026-06-02 13:29:07 -04:00
commit e84a517056
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ip_repo/iq_512b_to_240b/sim/iq_512b_to_240b.vhd
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--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
--Date : Wed Jan 24 11:37:59 2024
--Host : LENOVO-P620-RoundHill running 64-bit major release (build 9200)
--Command : generate_target iq_512b_to_240b.bd
--Design : iq_512b_to_240b
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity iq_512b_to_240b is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
m_axis_tready : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axis_tready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of iq_512b_to_240b : entity is "iq_512b_to_240b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_512b_to_240b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of iq_512b_to_240b : entity is "iq_512b_to_240b.hwdef";
end iq_512b_to_240b;
architecture STRUCTURE of iq_512b_to_240b is
component iq_512b_to_240b_axis_dwidth_converter_0_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
);
end component iq_512b_to_240b_axis_dwidth_converter_0_0;
component iq_512b_to_240b_dig_iq_encoder_0_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 239 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC
);
end component iq_512b_to_240b_dig_iq_encoder_0_0;
signal aclk_1 : STD_LOGIC;
signal aresetn_1 : STD_LOGIC;
signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
signal dig_iq_encoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
signal dig_iq_encoder_0_m_axis_TREADY : STD_LOGIC;
signal dig_iq_encoder_0_m_axis_TVALID : STD_LOGIC;
signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal s_axis_1_TREADY : STD_LOGIC;
signal s_axis_1_TVALID : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 s_axis TREADY";
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_512b_to_240b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
begin
aclk_1 <= aclk;
aresetn_1 <= aresetn;
dig_iq_encoder_0_m_axis_TREADY <= m_axis_tready;
m_axis_tdata(239 downto 0) <= dig_iq_encoder_0_m_axis_TDATA(239 downto 0);
m_axis_tvalid <= dig_iq_encoder_0_m_axis_TVALID;
s_axis_1_TDATA(511 downto 0) <= s_axis_tdata(511 downto 0);
s_axis_1_TVALID <= s_axis_tvalid;
s_axis_tready <= s_axis_1_TREADY;
axis_dwidth_converter_0: component iq_512b_to_240b_axis_dwidth_converter_0_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
s_axis_tdata(511 downto 0) => s_axis_1_TDATA(511 downto 0),
s_axis_tready => s_axis_1_TREADY,
s_axis_tvalid => s_axis_1_TVALID
);
dig_iq_encoder_0: component iq_512b_to_240b_dig_iq_encoder_0_0
port map (
aclk => aclk_1,
aresetn => aresetn_1,
m_axis_tdata(239 downto 0) => dig_iq_encoder_0_m_axis_TDATA(239 downto 0),
m_axis_tready => dig_iq_encoder_0_m_axis_TREADY,
m_axis_tvalid => dig_iq_encoder_0_m_axis_TVALID,
s_axis_tdata(223 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(223 downto 0),
s_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
s_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID
);
end STRUCTURE;