moving repo from git to local repo
This commit is contained in:
@@ -0,0 +1,344 @@
|
||||
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>m_axis_tvalid</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:name>choice_list_9d8b0d81</spirit:name>
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<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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<spirit:fileSets>
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<spirit:file>
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<spirit:name>dig_iq_decoder_ooc.xdc</spirit:name>
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<spirit:userFileType>xdc</spirit:userFileType>
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<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>dig_iq_decoder.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_b952dd62</spirit:userFileType>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:file>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_f64a5dae</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:file>
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<spirit:description>dig_iq_decoder_v1_0</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">dig_iq_decoder_v1_0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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||||
<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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||||
</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
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||||
</xilinx:taxonomies>
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||||
<xilinx:displayName>dig_iq_decoder_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>2</xilinx:coreRevision>
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<xilinx:coreCreationDateTime>2021-06-22T17:47:25Z</xilinx:coreCreationDateTime>
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<xilinx:tags>
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<xilinx:tag xilinx:name="nopcore"/>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@10cd760_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@7024ec49_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@702143e0_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@7318cb6e_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@47f9d0d5_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@467c2891_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@79d4f659_ARCHIVE_LOCATION">c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
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||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="8005bf8b"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6945f44e"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="b2bb5fab"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="c99d0644"/>
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||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
@@ -0,0 +1,114 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date:
|
||||
-- Design Name:
|
||||
-- Module Name: dig_iq_decoder - imp
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
--Library xpm;
|
||||
--use xpm.vcomponents.all;
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity dig_iq_decoder is
|
||||
|
||||
port (
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
|
||||
select_12b : in std_logic;
|
||||
|
||||
s_axis_tdata : in std_logic_vector(239 downto 0);
|
||||
s_axis_tvalid : in std_logic;
|
||||
|
||||
m_axis_tdata : out std_logic_vector(319 downto 0);
|
||||
m_axis_tvalid : out std_logic
|
||||
);
|
||||
end dig_iq_decoder;
|
||||
|
||||
architecture imp of dig_iq_decoder is
|
||||
|
||||
signal tvalid_int : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
m_axis_tvalid <= tvalid_int;
|
||||
|
||||
|
||||
process(aclk, aresetn)
|
||||
begin
|
||||
if(aresetn = '0')then
|
||||
tvalid_int <= '0';
|
||||
elsif(rising_edge(aclk))then
|
||||
tvalid_int <= s_axis_tvalid;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(aclk)
|
||||
begin
|
||||
|
||||
if(rising_edge(aclk))then
|
||||
|
||||
if(select_12b = '0')then
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(15 downto 0 ); -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(32 downto 17 ); -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(49 downto 34 ); -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(66 downto 51 ); -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(83 downto 68 ); -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(100 downto 85 ); -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(117 downto 102 ); -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(134 downto 119 ); -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(151 downto 136 ); -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(168 downto 153 ); -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(185 downto 170 ); -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(202 downto 187 ); -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(219 downto 204 ); -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(236 downto 221 ); -- IMAG[6]
|
||||
else
|
||||
m_axis_tdata(15 downto 0 ) <= s_axis_tdata(11 downto 0 ) & "0000"; -- REAL[0]
|
||||
m_axis_tdata(31 downto 16 ) <= s_axis_tdata(23 downto 12 ) & "0000"; -- IMAG[0]
|
||||
m_axis_tdata(47 downto 32 ) <= s_axis_tdata(35 downto 24 ) & "0000"; -- REAL[1]
|
||||
m_axis_tdata(63 downto 48 ) <= s_axis_tdata(47 downto 36 ) & "0000"; -- IMAG[1]
|
||||
m_axis_tdata(79 downto 64 ) <= s_axis_tdata(59 downto 48 ) & "0000"; -- REAL[2]
|
||||
m_axis_tdata(95 downto 80 ) <= s_axis_tdata(71 downto 60 ) & "0000"; -- IMAG[2]
|
||||
m_axis_tdata(111 downto 96 ) <= s_axis_tdata(83 downto 72 ) & "0000"; -- REAL[3]
|
||||
m_axis_tdata(127 downto 112 ) <= s_axis_tdata(95 downto 84 ) & "0000"; -- IMAG[3]
|
||||
m_axis_tdata(143 downto 128 ) <= s_axis_tdata(107 downto 96 ) & "0000"; -- REAL[4]
|
||||
m_axis_tdata(159 downto 144 ) <= s_axis_tdata(119 downto 108 ) & "0000"; -- IMAG[4]
|
||||
m_axis_tdata(175 downto 160 ) <= s_axis_tdata(131 downto 120 ) & "0000"; -- REAL[5]
|
||||
m_axis_tdata(191 downto 176 ) <= s_axis_tdata(143 downto 132 ) & "0000"; -- IMAG[5]
|
||||
m_axis_tdata(207 downto 192 ) <= s_axis_tdata(155 downto 144 ) & "0000"; -- REAL[6]
|
||||
m_axis_tdata(223 downto 208 ) <= s_axis_tdata(167 downto 156 ) & "0000"; -- IMAG[6]
|
||||
end if;
|
||||
|
||||
m_axis_tdata(239 downto 224 ) <= s_axis_tdata(179 downto 168 ) & "0000"; -- REAL[7]
|
||||
m_axis_tdata(255 downto 240 ) <= s_axis_tdata(191 downto 180 ) & "0000"; -- IMAG[7]
|
||||
m_axis_tdata(271 downto 256 ) <= s_axis_tdata(203 downto 192 ) & "0000"; -- REAL[8]
|
||||
m_axis_tdata(287 downto 272 ) <= s_axis_tdata(215 downto 204 ) & "0000"; -- IMAG[8]
|
||||
m_axis_tdata(303 downto 288 ) <= s_axis_tdata(227 downto 216 ) & "0000"; -- REAL[9]
|
||||
m_axis_tdata(319 downto 304 ) <= s_axis_tdata(239 downto 228 ) & "0000"; -- IMAG[9]
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
end imp;
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
|
||||
|
||||
##############################################################################################
|
||||
#
|
||||
# Used in Out-of-Context (OOC) synthesis only
|
||||
#
|
||||
##############################################################################################
|
||||
|
||||
create_clock -period 4 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user