Merge branch 'main' of https://erisys-gitea.duckdns.org/Erisys/alinx_z19_ad9081

constraints/qsfp_constr.xdc

@@ -1,7 +1,6 @@
 #####################################
 #
-#  VCU128 Rev1.0 XDC
+#   ALINX Z19 BOARD
-#  Date: 01/24/2018
 #
 ####################################
 ###################################
@@ -37,45 +36,54 @@ set_property PACKAGE_PIN R33      [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 130
 set_property PACKAGE_PIN R32      [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 130 - MGTREFCLK0P_130   CLK1_P
 # set_property PACKAGE_PIN W41      [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 130 - MGTREFCLK1N_130
 # set_property PACKAGE_PIN W40      [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 130 - MGTREFCLK1P_130
-# set_property PACKAGE_PIN U54      [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130
+ set_property PACKAGE_PIN L42      [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130
-# set_property PACKAGE_PIN U50      [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130
+ set_property PACKAGE_PIN L41      [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130
-# set_property PACKAGE_PIN T52      [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130
+ set_property PACKAGE_PIN K40      [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130
-# set_property PACKAGE_PIN R54      [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130
+ set_property PACKAGE_PIN K39      [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130
-# set_property PACKAGE_PIN U53      [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130
+ set_property PACKAGE_PIN J42      [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130
-# set_property PACKAGE_PIN U49      [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130
+ set_property PACKAGE_PIN J41      [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130
-# set_property PACKAGE_PIN T51      [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130
+ set_property PACKAGE_PIN H40      [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130
-# set_property PACKAGE_PIN R53      [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130
+ set_property PACKAGE_PIN H39      [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130
-# set_property PACKAGE_PIN V47      [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130
+
-# set_property PACKAGE_PIN U45      [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130
+ set_property PACKAGE_PIN M35      [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130
-# set_property PACKAGE_PIN T47      [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130
+ set_property PACKAGE_PIN M34      [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130
-# set_property PACKAGE_PIN R45      [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130
+ set_property PACKAGE_PIN L37      [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130
-# set_property PACKAGE_PIN V46      [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130
+ set_property PACKAGE_PIN L36      [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130
-# set_property PACKAGE_PIN U44      [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130
+ set_property PACKAGE_PIN K35      [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130
-# set_property PACKAGE_PIN T46      [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130
+ set_property PACKAGE_PIN K34      [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130
-# set_property PACKAGE_PIN R44      [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130
+ set_property PACKAGE_PIN J37      [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130
+ set_property PACKAGE_PIN J36      [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130
+
+set_property -dict {PACKAGE_PIN E7  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP3_INTL_LS"]    ;# 
+set_property -dict {PACKAGE_PIN A8  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP3_RESETL_LS"]  ;# 
+set_property -dict {PACKAGE_PIN A7  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP3_MODPRSL_LS"] ;# 
 
 ### J77
 set_property PACKAGE_PIN W33      [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 129 - MGTREFCLK0N_129   CLK3_N
 set_property PACKAGE_PIN W32      [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 129 - MGTREFCLK0P_129   CLK3_P
 # set_property PACKAGE_PIN R41      [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK1N_129
 # set_property PACKAGE_PIN R40      [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK1P_129
-# set_property PACKAGE_PIN L54      [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129
+# set_property PACKAGE_PIN R42      [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129
-# set_property PACKAGE_PIN K52      [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129
+# set_property PACKAGE_PIN R41      [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129
-# set_property PACKAGE_PIN J54      [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129
+# set_property PACKAGE_PIN P40      [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129
-# set_property PACKAGE_PIN H52      [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129
+# set_property PACKAGE_PIN P39      [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129
-# set_property PACKAGE_PIN L53      [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129
+# set_property PACKAGE_PIN N42      [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129
-# set_property PACKAGE_PIN K51      [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129
+# set_property PACKAGE_PIN N41      [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129
-# set_property PACKAGE_PIN J53      [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129
+# set_property PACKAGE_PIN M40      [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129
-# set_property PACKAGE_PIN H51      [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129
+# set_property PACKAGE_PIN M39      [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129
-# set_property PACKAGE_PIN L49      [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129
-# set_property PACKAGE_PIN L45      [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129
-# set_property PACKAGE_PIN K47      [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129
-# set_property PACKAGE_PIN J49      [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129
-# set_property PACKAGE_PIN L48      [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129
-# set_property PACKAGE_PIN L44      [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129
-# set_property PACKAGE_PIN K46      [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129
-# set_property PACKAGE_PIN J48      [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129
 
+# set_property PACKAGE_PIN T35      [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129
+# set_property PACKAGE_PIN T34      [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129
+# set_property PACKAGE_PIN R37      [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129
+# set_property PACKAGE_PIN R36      [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129
+# set_property PACKAGE_PIN P35      [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129
+# set_property PACKAGE_PIN P34      [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129
+# set_property PACKAGE_PIN N37      [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129
+# set_property PACKAGE_PIN N36      [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129
+
+set_property -dict {PACKAGE_PIN F8  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP2_INTL_LS"]    ;# 
+set_property -dict {PACKAGE_PIN F9  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP2_RESETL_LS"]  ;# 
+set_property -dict {PACKAGE_PIN D8  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP2_MODPRSL_LS"] ;# 
 # set_property PACKAGE_PIN BK25     [get_ports "QSFP2_RECCLK_N"] ;
 # set_property IOSTANDARD  LVDS     [get_ports "QSFP2_RECCLK_N"] ;
 # set_property PACKAGE_PIN BJ26     [get_ports "QSFP2_RECCLK_P"] ;

constraints/timing_constr.xdc

@@ -13,8 +13,8 @@ create_clock -name clkin8            -period  2.0 [get_ports clkin8_p]
 ##create_clock -name sysref2           -period  4.0 [get_ports sysref2_p] # not a clock
 
 create_clock -period 2.640 -name QSFP1_SI570_CLOCK_P [get_ports QSFP1_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
-create_clock -period 2.640 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P]
+create_clock -period 6.400 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P]
-create_clock -period 2.640 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P]
+create_clock -period 6.400 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P]
 create_clock -period 2.640 -name QSFP4_SI570_CLOCK_P [get_ports QSFP4_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
 
 

ip_repo/Si5332/src/si5332_wrapper.vhd

@@ -44,21 +44,6 @@ architecture imp of si5332_wrapper is
   signal man_clk_gen_en                   : std_logic := '0';
   signal man_clk_gen_cfg_reset            : std_logic := '0';
 
-
-  signal clk_100_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
-  signal clk_100_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
-  signal clk_100_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');
-
-  signal qsfp2_tick_1ms_r                 : std_logic_vector(0 to 2) := (others => '0');
-  signal qsfp2_freq_r                     : std_logic_vector(31 downto 0) := (others => '0');
-  signal qsfp2_cnt_r                      : std_logic_vector(31 downto 0) := (others => '0');
-
-  signal qsfp3_tick_1ms_r                 : std_logic_vector(0 to 2) := (others => '0');
-  signal qsfp3_freq_r                     : std_logic_vector(31 downto 0) := (others => '0');
-  signal qsfp3_cnt_r                      : std_logic_vector(31 downto 0) := (others => '0');
-
-
-
 begin
 
 
@@ -105,63 +90,4 @@ begin
       reset_in                              => clk_100_areset_in   
       );
 
-
--- i_vio_3 : entity work.vio_3
---   port map (
---     clk                         => clk_100_in,
---     probe_in0(0)                => i2c_mux_access_ok,       -- 1
---     probe_in1(0)                => si5341_access_ok,        -- 1
---     probe_in2(0)                => si5341_config_done,      -- 1
---     probe_in3(0)                => si5341_config_error,     -- 1
---     probe_in4                   => clk_100_freq_r,          -- 32
---     probe_in5                   => clk_100_cnt_r,           -- 32
---     probe_in6                   => qsfp2_freq_r,            -- 32
---     probe_in7                   => qsfp2_cnt_r,             -- 32
---     probe_in8                   => qsfp3_freq_r,            -- 32
---     probe_in9                   => qsfp3_cnt_r,             -- 32
---
---     probe_out0(0)               => man_clk_gen_en,          -- 1                                   
---     probe_out1(0)               => man_clk_gen_cfg_reset    -- 1                                                                                                                         
---   );
-      
-  process(clk_100_in)
-  begin
-    if (rising_edge(clk_100_in)) then
-      clk_100_tick_1ms_r      <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
-      if (clk_100_tick_1ms_r(0 to 1) = "01") then 
-        clk_100_freq_r        <= clk_100_cnt_r;
-        clk_100_cnt_r         <= (others => '0');
-      else
-        clk_100_cnt_r         <= clk_100_cnt_r + 1;
-      end if;
-    end if;
-  end process;
-      
-  process(qsfp2_clk_in)
-  begin
-    if (rising_edge(qsfp2_clk_in)) then
-      qsfp2_tick_1ms_r      <= qsfp2_tick_1ms_r(1 to 2) & tick_1ms;
-      if (qsfp2_tick_1ms_r(0 to 1) = "01") then 
-        qsfp2_freq_r        <= qsfp2_cnt_r;
-        qsfp2_cnt_r         <= (others => '0');
-      else
-        qsfp2_cnt_r         <= qsfp2_cnt_r + 1;
-      end if;
-    end if;
-  end process;
-      
-  process(qsfp3_clk_in)
-  begin
-    if (rising_edge(qsfp3_clk_in)) then
-      qsfp3_tick_1ms_r      <= qsfp3_tick_1ms_r(1 to 2) & tick_1ms;
-      if (qsfp3_tick_1ms_r(0 to 1) = "01") then 
-        qsfp3_freq_r        <= qsfp3_cnt_r;
-        qsfp3_cnt_r         <= (others => '0');
-      else
-        qsfp3_cnt_r         <= qsfp3_cnt_r + 1;
-      end if;
-    end if;
-  end process;
-      
-
 end architecture imp;

ip_repo/axi_regs_32/axi_regs_32.vhd

@@ -0,0 +1,839 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axi_regs_32 is
+	generic (
+		-- Width of S_AXI data bus
+		C_S_AXI_DATA_WIDTH	: integer	:= 32;
+		-- Width of S_AXI address bus
+		C_S_AXI_ADDR_WIDTH	: integer	:= 7
+	);
+	port (
+    reg0_out  : out std_logic_vector(31 downto 0);  
+    reg1_out  : out std_logic_vector(31 downto 0);  
+    reg2_out  : out std_logic_vector(31 downto 0);  
+    reg3_out  : out std_logic_vector(31 downto 0);  
+    reg4_out  : out std_logic_vector(31 downto 0);  
+    reg5_out  : out std_logic_vector(31 downto 0);  
+    reg6_out  : out std_logic_vector(31 downto 0);  
+    reg7_out  : out std_logic_vector(31 downto 0);  
+    reg8_out  : out std_logic_vector(31 downto 0);  
+    reg9_out  : out std_logic_vector(31 downto 0);  
+    reg10_out : out std_logic_vector(31 downto 0);  
+    reg11_out : out std_logic_vector(31 downto 0);  
+    reg12_out : out std_logic_vector(31 downto 0);  
+    reg13_out : out std_logic_vector(31 downto 0);  
+    reg14_out : out std_logic_vector(31 downto 0);  
+    reg15_out : out std_logic_vector(31 downto 0);  
+    reg16_out : out std_logic_vector(31 downto 0);  
+    reg17_out : out std_logic_vector(31 downto 0);  
+    reg18_out : out std_logic_vector(31 downto 0);  
+    reg19_out : out std_logic_vector(31 downto 0);  
+    reg20_out : out std_logic_vector(31 downto 0);  
+    reg21_out : out std_logic_vector(31 downto 0);  
+    reg22_out : out std_logic_vector(31 downto 0);  
+    reg23_out : out std_logic_vector(31 downto 0);  
+    reg24_out : out std_logic_vector(31 downto 0);  
+    reg25_out : out std_logic_vector(31 downto 0);  
+    reg26_out : out std_logic_vector(31 downto 0);  
+    reg27_out : out std_logic_vector(31 downto 0);  
+    reg28_out : out std_logic_vector(31 downto 0);  
+    reg29_out : out std_logic_vector(31 downto 0);  
+    reg30_out : out std_logic_vector(31 downto 0);  
+    reg31_out : out std_logic_vector(31 downto 0);  
+
+    reg0_in   : in  std_logic_vector(31 downto 0);  
+    reg1_in   : in  std_logic_vector(31 downto 0);  
+    reg2_in   : in  std_logic_vector(31 downto 0);  
+    reg3_in   : in  std_logic_vector(31 downto 0);  
+    reg4_in   : in  std_logic_vector(31 downto 0);  
+    reg5_in   : in  std_logic_vector(31 downto 0);  
+    reg6_in   : in  std_logic_vector(31 downto 0);  
+    reg7_in   : in  std_logic_vector(31 downto 0);  
+    reg8_in   : in  std_logic_vector(31 downto 0);  
+    reg9_in   : in  std_logic_vector(31 downto 0);  
+    reg10_in  : in  std_logic_vector(31 downto 0);  
+    reg11_in  : in  std_logic_vector(31 downto 0);  
+    reg12_in  : in  std_logic_vector(31 downto 0);  
+    reg13_in  : in  std_logic_vector(31 downto 0);  
+    reg14_in  : in  std_logic_vector(31 downto 0);  
+    reg15_in  : in  std_logic_vector(31 downto 0);  
+    reg16_in  : in  std_logic_vector(31 downto 0);  
+    reg17_in  : in  std_logic_vector(31 downto 0);  
+    reg18_in  : in  std_logic_vector(31 downto 0);  
+    reg19_in  : in  std_logic_vector(31 downto 0);  
+    reg20_in  : in  std_logic_vector(31 downto 0);  
+    reg21_in  : in  std_logic_vector(31 downto 0);  
+    reg22_in  : in  std_logic_vector(31 downto 0);  
+    reg23_in  : in  std_logic_vector(31 downto 0);  
+    reg24_in  : in  std_logic_vector(31 downto 0);  
+    reg25_in  : in  std_logic_vector(31 downto 0);  
+    reg26_in  : in  std_logic_vector(31 downto 0);  
+    reg27_in  : in  std_logic_vector(31 downto 0);  
+    reg28_in  : in  std_logic_vector(31 downto 0);  
+    reg29_in  : in  std_logic_vector(31 downto 0);  
+    reg30_in  : in  std_logic_vector(31 downto 0);  
+    reg31_in  : in  std_logic_vector(31 downto 0);  
+
+		-- Global Clock Signal
+		S_AXI_ACLK	: in std_logic;
+		-- Global Reset Signal. This Signal is Active LOW
+		S_AXI_ARESETN	: in std_logic;
+		-- Write address (issued by master, acceped by Slave)
+		S_AXI_AWADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		-- Write channel Protection type. This signal indicates the
+    		-- privilege and security level of the transaction, and whether
+    		-- the transaction is a data access or an instruction access.
+		S_AXI_AWPROT	: in std_logic_vector(2 downto 0);
+		-- Write address valid. This signal indicates that the master signaling
+    		-- valid write address and control information.
+		S_AXI_AWVALID	: in std_logic;
+		-- Write address ready. This signal indicates that the slave is ready
+    		-- to accept an address and associated control signals.
+		S_AXI_AWREADY	: out std_logic;
+		-- Write data (issued by master, acceped by Slave) 
+		S_AXI_WDATA	: in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		-- Write strobes. This signal indicates which byte lanes hold
+    		-- valid data. There is one write strobe bit for each eight
+    		-- bits of the write data bus.    
+		S_AXI_WSTRB	: in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+		-- Write valid. This signal indicates that valid write
+    		-- data and strobes are available.
+		S_AXI_WVALID	: in std_logic;
+		-- Write ready. This signal indicates that the slave
+    		-- can accept the write data.
+		S_AXI_WREADY	: out std_logic;
+		-- Write response. This signal indicates the status
+    		-- of the write transaction.
+		S_AXI_BRESP	: out std_logic_vector(1 downto 0);
+		-- Write response valid. This signal indicates that the channel
+    		-- is signaling a valid write response.
+		S_AXI_BVALID	: out std_logic;
+		-- Response ready. This signal indicates that the master
+    		-- can accept a write response.
+		S_AXI_BREADY	: in std_logic;
+		-- Read address (issued by master, acceped by Slave)
+		S_AXI_ARADDR	: in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+		-- Protection type. This signal indicates the privilege
+    		-- and security level of the transaction, and whether the
+    		-- transaction is a data access or an instruction access.
+		S_AXI_ARPROT	: in std_logic_vector(2 downto 0);
+		-- Read address valid. This signal indicates that the channel
+    		-- is signaling valid read address and control information.
+		S_AXI_ARVALID	: in std_logic;
+		-- Read address ready. This signal indicates that the slave is
+    		-- ready to accept an address and associated control signals.
+		S_AXI_ARREADY	: out std_logic;
+		-- Read data (issued by slave)
+		S_AXI_RDATA	: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+		-- Read response. This signal indicates the status of the
+    		-- read transfer.
+		S_AXI_RRESP	: out std_logic_vector(1 downto 0);
+		-- Read valid. This signal indicates that the channel is
+    		-- signaling the required read data.
+		S_AXI_RVALID	: out std_logic;
+		-- Read ready. This signal indicates that the master can
+    		-- accept the read data and response information.
+		S_AXI_RREADY	: in std_logic
+	);
+end axi_regs_32;
+
+architecture arch_imp of axi_regs_32 is
+
+	-- AXI4LITE signals
+	signal axi_awaddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+	signal axi_awready	: std_logic;
+	signal axi_wready	: std_logic;
+	signal axi_bresp	: std_logic_vector(1 downto 0);
+	signal axi_bvalid	: std_logic;
+	signal axi_araddr	: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+	signal axi_arready	: std_logic;
+	signal axi_rdata	: std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal axi_rresp	: std_logic_vector(1 downto 0);
+	signal axi_rvalid	: std_logic;
+
+	-- Example-specific design signals
+	-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+	-- ADDR_LSB is used for addressing 32/64 bit registers/memories
+	-- ADDR_LSB = 2 for 32 bits (n downto 2)
+	-- ADDR_LSB = 3 for 64 bits (n downto 3)
+	constant ADDR_LSB  : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
+	constant OPT_MEM_ADDR_BITS : integer := 4;
+	------------------------------------------------
+	---- Signals for user logic register space example
+	--------------------------------------------------
+	---- Number of Slave Registers 32
+	signal slv_reg0	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg1	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg2	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg3	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg4	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg5	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg6	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg7	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg8	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg9	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg10	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg11	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg12	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg13	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg14	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg15	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg16	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg17	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg18	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg19	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg20	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg21	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg22	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg23	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg24	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg25	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg26	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg27	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg28	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg29	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg30	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg31	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal slv_reg_rden	: std_logic;
+	signal slv_reg_wren	: std_logic;
+	signal reg_data_out	:std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+	signal byte_index	: integer;
+	signal aw_en	: std_logic;
+
+begin
+	-- I/O Connections assignments
+
+	S_AXI_AWREADY	<= axi_awready;
+	S_AXI_WREADY	<= axi_wready;
+	S_AXI_BRESP	<= axi_bresp;
+	S_AXI_BVALID	<= axi_bvalid;
+	S_AXI_ARREADY	<= axi_arready;
+	S_AXI_RDATA	<= axi_rdata;
+	S_AXI_RRESP	<= axi_rresp;
+	S_AXI_RVALID	<= axi_rvalid;
+	-- Implement axi_awready generation
+	-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+	-- de-asserted when reset is low.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_awready <= '0';
+	      aw_en <= '1';
+	    else
+	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+	        -- slave is ready to accept write address when
+	        -- there is a valid write address and write data
+	        -- on the write address and data bus. This design 
+	        -- expects no outstanding transactions. 
+	           axi_awready <= '1';
+	           aw_en <= '0';
+	        elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
+	           aw_en <= '1';
+	           axi_awready <= '0';
+	      else
+	        axi_awready <= '0';
+	      end if;
+	    end if;
+	  end if;
+	end process;
+
+	-- Implement axi_awaddr latching
+	-- This process is used to latch the address when both 
+	-- S_AXI_AWVALID and S_AXI_WVALID are valid. 
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_awaddr <= (others => '0');
+	    else
+	      if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
+	        -- Write Address latching
+	        axi_awaddr <= S_AXI_AWADDR;
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_wready generation
+	-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+	-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
+	-- de-asserted when reset is low. 
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_wready <= '0';
+	    else
+	      if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
+	          -- slave is ready to accept write data when 
+	          -- there is a valid write address and write data
+	          -- on the write address and data bus. This design 
+	          -- expects no outstanding transactions.           
+	          axi_wready <= '1';
+	      else
+	        axi_wready <= '0';
+	      end if;
+	    end if;
+	  end if;
+	end process; 
+
+	-- Implement memory mapped register select and write logic generation
+	-- The write data is accepted and written to memory mapped registers when
+	-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+	-- select byte enables of slave registers while writing.
+	-- These registers are cleared when reset (active low) is applied.
+	-- Slave register write enable is asserted when valid address and data are available
+	-- and the slave is ready to accept the write address and write data.
+	slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
+
+	process (S_AXI_ACLK)
+	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); 
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      slv_reg0 <= (others => '0');
+	      slv_reg1 <= (others => '0');
+	      slv_reg2 <= (others => '0');
+	      slv_reg3 <= (others => '0');
+	      slv_reg4 <= (others => '0');
+	      slv_reg5 <= (others => '0');
+	      slv_reg6 <= (others => '0');
+	      slv_reg7 <= (others => '0');
+	      slv_reg8 <= (others => '0');
+	      slv_reg9 <= (others => '0');
+	      slv_reg10 <= (others => '0');
+	      slv_reg11 <= (others => '0');
+	      slv_reg12 <= (others => '0');
+	      slv_reg13 <= (others => '0');
+	      slv_reg14 <= (others => '0');
+	      slv_reg15 <= (others => '0');
+	      slv_reg16 <= (others => '0');
+	      slv_reg17 <= (others => '0');
+	      slv_reg18 <= (others => '0');
+	      slv_reg19 <= (others => '0');
+	      slv_reg20 <= (others => '0');
+	      slv_reg21 <= (others => '0');
+	      slv_reg22 <= (others => '0');
+	      slv_reg23 <= (others => '0');
+	      slv_reg24 <= (others => '0');
+	      slv_reg25 <= (others => '0');
+	      slv_reg26 <= (others => '0');
+	      slv_reg27 <= (others => '0');
+	      slv_reg28 <= (others => '0');
+	      slv_reg29 <= (others => '0');
+	      slv_reg30 <= (others => '0');
+	      slv_reg31 <= (others => '0');
+	    else
+	      loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+	      if (slv_reg_wren = '1') then
+	        case loc_addr is
+	          when b"00000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 0
+	                slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 1
+	                slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 2
+	                slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 3
+	                slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 4
+	                slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 5
+	                slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 6
+	                slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"00111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 7
+	                slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 8
+	                slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 9
+	                slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 10
+	                slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 11
+	                slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 12
+	                slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 13
+	                slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 14
+	                slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"01111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 15
+	                slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 16
+	                slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 17
+	                slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 18
+	                slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 19
+	                slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 20
+	                slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 21
+	                slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 22
+	                slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"10111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 23
+	                slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11000" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 24
+	                slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11001" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 25
+	                slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11010" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 26
+	                slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11011" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 27
+	                slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11100" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 28
+	                slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11101" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 29
+	                slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11110" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 30
+	                slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when b"11111" =>
+	            for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+	              if ( S_AXI_WSTRB(byte_index) = '1' ) then
+	                -- Respective byte enables are asserted as per write strobes                   
+	                -- slave registor 31
+	                slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+	              end if;
+	            end loop;
+	          when others =>
+	            slv_reg0 <= slv_reg0;
+	            slv_reg1 <= slv_reg1;
+	            slv_reg2 <= slv_reg2;
+	            slv_reg3 <= slv_reg3;
+	            slv_reg4 <= slv_reg4;
+	            slv_reg5 <= slv_reg5;
+	            slv_reg6 <= slv_reg6;
+	            slv_reg7 <= slv_reg7;
+	            slv_reg8 <= slv_reg8;
+	            slv_reg9 <= slv_reg9;
+	            slv_reg10 <= slv_reg10;
+	            slv_reg11 <= slv_reg11;
+	            slv_reg12 <= slv_reg12;
+	            slv_reg13 <= slv_reg13;
+	            slv_reg14 <= slv_reg14;
+	            slv_reg15 <= slv_reg15;
+	            slv_reg16 <= slv_reg16;
+	            slv_reg17 <= slv_reg17;
+	            slv_reg18 <= slv_reg18;
+	            slv_reg19 <= slv_reg19;
+	            slv_reg20 <= slv_reg20;
+	            slv_reg21 <= slv_reg21;
+	            slv_reg22 <= slv_reg22;
+	            slv_reg23 <= slv_reg23;
+	            slv_reg24 <= slv_reg24;
+	            slv_reg25 <= slv_reg25;
+	            slv_reg26 <= slv_reg26;
+	            slv_reg27 <= slv_reg27;
+	            slv_reg28 <= slv_reg28;
+	            slv_reg29 <= slv_reg29;
+	            slv_reg30 <= slv_reg30;
+	            slv_reg31 <= slv_reg31;
+	        end case;
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement write response logic generation
+	-- The write response and response valid signals are asserted by the slave 
+	-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
+	-- This marks the acceptance of address and indicates the status of 
+	-- write transaction.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_bvalid  <= '0';
+	      axi_bresp   <= "00"; --need to work more on the responses
+	    else
+	      if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0'  ) then
+	        axi_bvalid <= '1';
+	        axi_bresp  <= "00"; 
+	      elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then   --check if bready is asserted while bvalid is high)
+	        axi_bvalid <= '0';                                 -- (there is a possibility that bready is always asserted high)
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_arready generation
+	-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
+	-- S_AXI_ARVALID is asserted. axi_awready is 
+	-- de-asserted when reset (active low) is asserted. 
+	-- The read address is also latched when S_AXI_ARVALID is 
+	-- asserted. axi_araddr is reset to zero on reset assertion.
+
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then 
+	    if S_AXI_ARESETN = '0' then
+	      axi_arready <= '0';
+	      axi_araddr  <= (others => '1');
+	    else
+	      if (axi_arready = '0' and S_AXI_ARVALID = '1') then
+	        -- indicates that the slave has acceped the valid read address
+	        axi_arready <= '1';
+	        -- Read Address latching 
+	        axi_araddr  <= S_AXI_ARADDR;           
+	      else
+	        axi_arready <= '0';
+	      end if;
+	    end if;
+	  end if;                   
+	end process; 
+
+	-- Implement axi_arvalid generation
+	-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
+	-- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
+	-- data are available on the axi_rdata bus at this instance. The 
+	-- assertion of axi_rvalid marks the validity of read data on the 
+	-- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
+	-- is deasserted on reset (active low). axi_rresp and axi_rdata are 
+	-- cleared to zero on reset (active low).  
+	process (S_AXI_ACLK)
+	begin
+	  if rising_edge(S_AXI_ACLK) then
+	    if S_AXI_ARESETN = '0' then
+	      axi_rvalid <= '0';
+	      axi_rresp  <= "00";
+	    else
+	      if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
+	        -- Valid read data is available at the read data bus
+	        axi_rvalid <= '1';
+	        axi_rresp  <= "00"; -- 'OKAY' response
+	      elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
+	        -- Read data is accepted by the master
+	        axi_rvalid <= '0';
+	      end if;            
+	    end if;
+	  end if;
+	end process;
+
+	-- Implement memory mapped register select and read logic generation
+	-- Slave register read enable is asserted when valid address is available
+	-- and the slave is ready to accept the read address.
+	slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
+
+	process (reg0_in, reg1_in, reg2_in, reg3_in, reg4_in, reg5_in, reg6_in, reg7_in, reg8_in, reg9_in, reg10_in, reg11_in, reg12_in, reg13_in, reg14_in, reg15_in, reg16_in, reg17_in, reg18_in, reg19_in, reg20_in, reg21_in, reg22_in, reg23_in, reg24_in, reg25_in, reg26_in, reg27_in, reg28_in, reg29_in, reg30_in, reg31_in, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
+	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+	begin
+	    -- Address decoding for reading registers
+	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+	    case loc_addr is
+	      when b"00000" =>
+	        reg_data_out <= reg0_in;
+	      when b"00001" =>
+	        reg_data_out <= reg1_in;
+	      when b"00010" =>
+	        reg_data_out <= reg2_in;
+	      when b"00011" =>
+	        reg_data_out <= reg3_in;
+	      when b"00100" =>
+	        reg_data_out <= reg4_in;
+	      when b"00101" =>
+	        reg_data_out <= reg5_in;
+	      when b"00110" =>
+	        reg_data_out <= reg6_in;
+	      when b"00111" =>
+	        reg_data_out <= reg7_in;
+	      when b"01000" =>
+	        reg_data_out <= reg8_in;
+	      when b"01001" =>
+	        reg_data_out <= reg9_in;
+	      when b"01010" =>
+	        reg_data_out <= reg10_in;
+	      when b"01011" =>
+	        reg_data_out <= reg11_in;
+	      when b"01100" =>
+	        reg_data_out <= reg12_in;
+	      when b"01101" =>
+	        reg_data_out <= reg13_in;
+	      when b"01110" =>
+	        reg_data_out <= reg14_in;
+	      when b"01111" =>
+	        reg_data_out <= reg15_in;
+	      when b"10000" =>
+	        reg_data_out <= reg16_in;
+	      when b"10001" =>
+	        reg_data_out <= reg17_in;
+	      when b"10010" =>
+	        reg_data_out <= reg18_in;
+	      when b"10011" =>
+	        reg_data_out <= reg19_in;
+	      when b"10100" =>
+	        reg_data_out <= reg20_in;
+	      when b"10101" =>
+	        reg_data_out <= reg21_in;
+	      when b"10110" =>
+	        reg_data_out <= reg22_in;
+	      when b"10111" =>
+	        reg_data_out <= reg23_in;
+	      when b"11000" =>
+	        reg_data_out <= reg24_in;
+	      when b"11001" =>
+	        reg_data_out <= reg25_in;
+	      when b"11010" =>
+	        reg_data_out <= reg26_in;
+	      when b"11011" =>
+	        reg_data_out <= reg27_in;
+	      when b"11100" =>
+	        reg_data_out <= reg28_in;
+	      when b"11101" =>
+	        reg_data_out <= reg29_in;
+	      when b"11110" =>
+	        reg_data_out <= reg30_in;
+	      when b"11111" =>
+	        reg_data_out <= reg31_in;
+	      when others =>
+	        reg_data_out  <= (others => '0');
+	    end case;
+	end process; 
+
+	-- Output register or memory read data
+	process( S_AXI_ACLK ) is
+	begin
+	  if (rising_edge (S_AXI_ACLK)) then
+	    if ( S_AXI_ARESETN = '0' ) then
+	      axi_rdata  <= (others => '0');
+	    else
+	      if (slv_reg_rden = '1') then
+	        -- When there is a valid read address (S_AXI_ARVALID) with 
+	        -- acceptance of read address by the slave (axi_arready), 
+	        -- output the read dada 
+	        -- Read address mux
+	          axi_rdata <= reg_data_out;     -- register read data
+	      end if;   
+	    end if;
+	  end if;
+	end process;
+
+  reg0_out  <=  slv_reg0;
+  reg1_out  <=  slv_reg1;
+  reg2_out  <=  slv_reg2;
+  reg3_out  <=  slv_reg3;
+  reg4_out  <=  slv_reg4;
+  reg5_out  <=  slv_reg5;
+  reg6_out  <=  slv_reg6;
+  reg7_out  <=  slv_reg7;
+  reg8_out  <=  slv_reg8;
+  reg9_out  <=  slv_reg9;
+  reg10_out <=  slv_reg10;
+  reg11_out <=  slv_reg11;
+  reg12_out <=  slv_reg12;
+  reg13_out <=  slv_reg13;
+  reg14_out <=  slv_reg14;
+  reg15_out <=  slv_reg15;
+  reg16_out <=  slv_reg16;
+  reg17_out <=  slv_reg17;
+  reg18_out <=  slv_reg18;
+  reg19_out <=  slv_reg19;
+  reg20_out <=  slv_reg20;
+  reg21_out <=  slv_reg21;
+  reg22_out <=  slv_reg22;
+  reg23_out <=  slv_reg23;
+  reg24_out <=  slv_reg24;
+  reg25_out <=  slv_reg25;
+  reg26_out <=  slv_reg26;
+  reg27_out <=  slv_reg27;
+  reg28_out <=  slv_reg28;
+  reg29_out <=  slv_reg29;
+  reg30_out <=  slv_reg30;
+  reg31_out <=  slv_reg31;
+
+end arch_imp;

ip_repo/axi_regs_32/axi_regs_32_ooc.xdc

@@ -0,0 +1,10 @@
+
+
+
+
+create_clock -period 10.000 -name S_AXI_ACLK [get_ports S_AXI_ACLK]; 
+ 
+ 
+
+ 
+ 

ip_repo/axi_regs_32/xgui/axi_regs_32_v1_0.tcl

@@ -0,0 +1,38 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S_AXI_DATA_WIDTH
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
+}
+

ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc

@@ -1,6 +0,0 @@
-###############################################################################################################
-# Core-Level Timing Constraints for axi_register_slice Component "axis_register_slice_32"
-###############################################################################################################
-#
-# This component is not configured in a multi-SLR crossing or auto-pipelining mode.
-# No timing core-level constraints are needed.

ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc

@@ -1,57 +0,0 @@
-# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of AMD and is protected under U.S. and international copyright
-# and other intellectual property laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# AMD, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) AMD shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or AMD had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# AMD products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of AMD products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-# DO NOT MODIFY THIS FILE.
-# #########################################################
-#
-# This XDC is used only in OOC mode for synthesis, implementation
-#
-# #########################################################
-
-
-create_clock -period 100 -name aclk [get_ports aclk]
-
-

ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v

@@ -1,30 +0,0 @@
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
-// Date        : Thu Apr 23 10:08:03 2026
-// Host        : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
-// Command     : write_verilog -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
-//               axis_register_slice_32_ axis_register_slice_32_stub.v
-// Design      : axis_register_slice_32
-// Purpose     : Stub declaration of top-level module interface
-// Device      : xczu19eg-ffvc1760-2-i
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
-module axis_register_slice_32(aclk, aresetn, s_axis_tvalid, s_axis_tready, 
-  s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata)
-/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]" */
-/* synthesis syn_force_seq_prim="aclk" */;
-  input aclk /* synthesis syn_isclock = 1 */;
-  input aresetn;
-  input s_axis_tvalid;
-  output s_axis_tready;
-  input [31:0]s_axis_tdata;
-  output m_axis_tvalid;
-  input m_axis_tready;
-  output [31:0]m_axis_tdata;
-endmodule

ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl

@@ -1,38 +0,0 @@
--- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
--- Date        : Thu Apr 23 10:08:04 2026
--- Host        : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
--- Command     : write_vhdl -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
---               axis_register_slice_32_ axis_register_slice_32_stub.vhdl
--- Design      : axis_register_slice_32
--- Purpose     : Stub declaration of top-level module interface
--- Device      : xczu19eg-ffvc1760-2-i
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity axis_register_slice_32 is
-  Port ( 
-    aclk : in STD_LOGIC;
-    aresetn : in STD_LOGIC;
-    s_axis_tvalid : in STD_LOGIC;
-    s_axis_tready : out STD_LOGIC;
-    s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    m_axis_tvalid : out STD_LOGIC;
-    m_axis_tready : in STD_LOGIC;
-    m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
-  );
-
-end axis_register_slice_32;
-
-architecture stub of axis_register_slice_32 is
-attribute syn_black_box : boolean;
-attribute black_box_pad_pin : string;
-attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]";
-attribute X_CORE_INFO : string;
-attribute X_CORE_INFO of stub : architecture is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2";
-begin
-end;

ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh

@@ -1,336 +0,0 @@
-// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of AMD and is protected under U.S. and international copyright
-// and other intellectual property laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// AMD, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) AMD shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or AMD had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// AMD products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of AMD products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-////////////////////////////////////////////////////////////
-//
-// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
-//
-// Verilog-standard:  Verilog 2001
-//--------------------------------------------------------------------------
-// Global Parameters:
-//
-// Functions:
-//   f_clogb2
-//   f_gcd
-//   f_lcm
-//   f_get_tdata_indx
-//   f_get_tstrb_indx
-//   f_get_tkeep_indx
-//   f_get_tlast_indx
-//   f_get_tid_indx
-//   f_get_tdest_indx
-//   f_get_tuser_indx
-//   f_payload_width
-// Tasks:
-//   t_display_tdata_error
-//--------------------------------------------------------------------------
-///////////////////////////////////////////////////////////////////////////////
-// BEGIN Global Parameters
-///////////////////////////////////////////////////////////////////////////////
-// Define Signal Set indices
-localparam G_INDX_SS_TREADY = 0;
-localparam G_INDX_SS_TDATA  = 1;
-localparam G_INDX_SS_TSTRB  = 2;
-localparam G_INDX_SS_TKEEP  = 3;
-localparam G_INDX_SS_TLAST  = 4;
-localparam G_INDX_SS_TID    = 5;
-localparam G_INDX_SS_TDEST  = 6;
-localparam G_INDX_SS_TUSER  = 7;
-localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
-localparam G_MASK_SS_TDATA  = 32'h1 << G_INDX_SS_TDATA;
-localparam G_MASK_SS_TSTRB  = 32'h1 << G_INDX_SS_TSTRB;
-localparam G_MASK_SS_TKEEP  = 32'h1 << G_INDX_SS_TKEEP;
-localparam G_MASK_SS_TLAST  = 32'h1 << G_INDX_SS_TLAST;
-localparam G_MASK_SS_TID    = 32'h1 << G_INDX_SS_TID  ;
-localparam G_MASK_SS_TDEST  = 32'h1 << G_INDX_SS_TDEST;
-localparam G_MASK_SS_TUSER  = 32'h1 << G_INDX_SS_TUSER;
-
-// Task DRC error levels
-localparam G_TASK_SEVERITY_ERR   = 2;
-localparam G_TASK_SEVERITY_WARNING = 1;
-localparam G_TASK_SEVERITY_INFO    = 0;
-
-///////////////////////////////////////////////////////////////////////////////
-// BEGIN Functions
-///////////////////////////////////////////////////////////////////////////////
-// ceiling logb2
-  function integer f_clogb2 (input integer size);
-    integer s;
-    begin
-      s = size;
-      s = s - 1;
-      for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
-            s = s >> 1;
-    end
-  endfunction // clogb2
-
-  // Calculates the Greatest Common Divisor between two integers using the
-  // euclidean algorithm.
-  function automatic integer f_gcd (
-    input integer a,
-    input integer b
-    );
-    begin : main
-      if (a == 0) begin
-        f_gcd = b;
-      end else if (b == 0) begin
-        f_gcd = a;
-      end else if (a > b) begin
-        f_gcd = f_gcd(a % b, b);
-      end else begin
-        f_gcd = f_gcd(a, b % a);
-      end
-    end
-  endfunction
-
-  // Calculates the Lowest Common Denominator between two integers
-  function integer f_lcm (
-    input integer a,
-    input integer b
-    );
-    begin : main
-      f_lcm = ( a / f_gcd(a, b)) * b; 
-    end
-  endfunction
-
-  // Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
-  // signal is not enabled.
-  function integer f_get_tdata_indx (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      f_get_tdata_indx = 0;
-    end
-  endfunction
-
-  // Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
-  // signal is not enabled.
-  function integer f_get_tstrb_indx (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      integer cur_indx;
-      cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
-      // If TDATA exists, then add its width to its base to get the tstrb index
-      f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
-    end
-  endfunction
-
-  // Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
-  // signal is not enabled.
-  function integer f_get_tkeep_indx (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      integer cur_indx;
-      cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
-      f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
-    end
-  endfunction
-
-  // Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
-  // signal is not enabled.
-  function integer f_get_tlast_indx (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      integer cur_indx;
-      cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
-      f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
-    end
-  endfunction
-
-  // Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
-  // signal is not enabled.
-  function integer f_get_tid_indx (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      integer cur_indx;
-      cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
-      f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
-    end
-  endfunction
-
-  // Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
-  // signal is not enabled.
-  function integer f_get_tdest_indx (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      integer cur_indx;
-      cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
-      f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
-    end
-  endfunction
-
-  // Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
-  // signal is not enabled.
-  function integer f_get_tuser_indx (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      integer cur_indx;
-      cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
-      f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
-    end
-  endfunction
-
-  // Payload is the sum of all the AXIS signals present except for
-  // TREADY/TVALID
-  function integer f_payload_width (
-    input integer DAW,  // TDATA Width
-    input integer IDW,  // TID Width
-    input integer DEW,  // TDEST Width
-    input integer USW,  // TUSER Width
-    input [31:0]  SST   // Signal Set
-    );
-    begin : main
-      integer cur_indx;
-      cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
-      f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
-      // Ensure that the return value is never less than 1
-      f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
-    end
-  endfunction
-
-  task t_check_tdata_width(
-    input  integer    data_width,
-    input  [8*80-1:0] var_name,
-    input  [8*80-1:0] inst_name,
-    input  integer    severity_lvl,
-    output integer    ret_val
-  );
-    // Severity levels:
-    // 0 = INFO
-    // 1 = WARNING
-    // 2 = ERROR
-    begin : t_check_tdata_width
-      if (data_width%8 != 0) begin  
-        //       000       1          2         3         4         5         6         7         8
-        //       012       0          0         0         0         0         0         0         0
-        if (severity_lvl >= 2) begin
-        $display("ERROR: %m::%s", inst_name);
-        end else if (severity_lvl == 1) begin
-        $display("WARNING: %m::%s", inst_name);
-        end else begin
-        $display("INFO: %m::%s", inst_name);
-        end
-        $display("       Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
-        $display("       AXI4-Stream data width is only defined for byte multiples. See the ");
-        $display("       AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
-        $display("       information.");
-        ret_val = 1;
-      end else begin
-        ret_val = 0;
-      end
-    end
-  endtask
-
-  task t_check_tuser_width(
-    input  integer    tuser_width,
-    input  [8*80-1:0] tuser_name,
-    input  integer    tdata_width,
-    input  [8*80-1:0] tdata_name,
-    input  [8*80-1:0] inst_name,
-    input  integer    severity_lvl,
-    output integer    ret_val
-  );
-    // Severity levels:
-    // 0 = INFO
-    // 1 = WARNING
-    // 2 = ERROR
-    begin : t_check_tuser_width
-      integer tdata_bytes; 
-      tdata_bytes = tdata_width/8;
-      if ((tuser_width%tdata_bytes) != 0) begin  
-        //       000       1          2         3         4         5         6         7         8
-        //       012       0          0         0         0         0         0         0         0
-        if (severity_lvl >= 2) begin
-        $display("ERROR: %m::%s", inst_name);
-        end else if (severity_lvl == 1) begin
-        $display("WARNING: %m::%s", inst_name);
-        end else begin
-        $display("INFO: %m::%s", inst_name);
-        end
-        $display("       Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
-        $display("       multiple of the width of the interface (%s == %2d) in bytes.'  AXI4-Stream", tdata_name, tdata_width);
-        $display("       TUSER width in this module is only defined when the TUSER is the");
-        $display("       recommended value.  See the AMBA4 AXI4-Stream Protocol Specification v1.0");
-        $display("       Section 2.1, 2.3.3 and 2.8 for more information.  ");
-        ret_val = 1;
-      end else begin
-        ret_val = 0;
-      end
-    end
-  endtask
-

ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v

@@ -1,125 +0,0 @@
-// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of AMD and is protected under U.S. and international copyright
-// and other intellectual property laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// AMD, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) AMD shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or AMD had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// AMD products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of AMD products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:axis_register_slice:1.1
-// IP Revision: 29
-
-(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
-(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *)
-(* CORE_GENERATION_INFO = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_register_slice,x_ipVersion=1.1,x_ipCoreRevision=29,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011,C_REG_CONFIG=8,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER=0,C_PIPELINES_SLAVE=0,C_PIPELINES_MIDDLE=0}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module axis_register_slice_32 (
-  aclk,
-  aresetn,
-  s_axis_tvalid,
-  s_axis_tready,
-  s_axis_tdata,
-  m_axis_tvalid,
-  m_axis_tready,
-  m_axis_tdata
-);
-
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
-input wire aclk;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
-input wire aresetn;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
-input wire s_axis_tvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
-output wire s_axis_tready;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
-input wire [31 : 0] s_axis_tdata;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
-output wire m_axis_tvalid;
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
-input wire m_axis_tready;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
-output wire [31 : 0] m_axis_tdata;
-
-  axis_register_slice_v1_1_29_axis_register_slice #(
-    .C_FAMILY("zynquplus"),
-    .C_AXIS_TDATA_WIDTH(32),
-    .C_AXIS_TID_WIDTH(1),
-    .C_AXIS_TDEST_WIDTH(1),
-    .C_AXIS_TUSER_WIDTH(1),
-    .C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011),
-    .C_REG_CONFIG(8),
-    .C_NUM_SLR_CROSSINGS(0),
-    .C_PIPELINES_MASTER(0),
-    .C_PIPELINES_SLAVE(0),
-    .C_PIPELINES_MIDDLE(0)
-  ) inst (
-    .aclk(aclk),
-    .aclk2x(1'H0),
-    .aresetn(aresetn),
-    .aclken(1'H1),
-    .s_axis_tvalid(s_axis_tvalid),
-    .s_axis_tready(s_axis_tready),
-    .s_axis_tdata(s_axis_tdata),
-    .s_axis_tstrb(4'HF),
-    .s_axis_tkeep(4'HF),
-    .s_axis_tlast(1'H1),
-    .s_axis_tid(1'H0),
-    .s_axis_tdest(1'H0),
-    .s_axis_tuser(1'H0),
-    .m_axis_tvalid(m_axis_tvalid),
-    .m_axis_tready(m_axis_tready),
-    .m_axis_tdata(m_axis_tdata),
-    .m_axis_tstrb(),
-    .m_axis_tkeep(),
-    .m_axis_tlast(),
-    .m_axis_tid(),
-    .m_axis_tdest(),
-    .m_axis_tuser()
-  );
-endmodule

ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci

@@ -4,7 +4,7 @@
     "xci_name": "addsub",
     "component_reference": "xilinx.com:ip:c_addsub:12.0",
     "ip_revision": "16",
-    "gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/addsub",
+    "gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/addsub",
     "parameters": {
       "component_parameters": {
         "Component_Name": [ { "value": "addsub", "resolve_type": "user", "usage": "all" } ],

ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd

@@ -35,7 +35,6 @@ entity qsfp_intfc_v1_0 is
 --    sysref_in                                 : in  std_logic;
     ref_clk_div2_in                           : in  std_logic;
     qsfp2_clk_in                              : in  std_logic;
-    qsfp3_clk_in                              : in  std_logic;
     pl_clk3_0                                 : in  std_logic;
 
     QSFP1_SI570_CLOCK_P                       : in  std_logic;
@@ -63,6 +62,14 @@ entity qsfp_intfc_v1_0 is
     QSFP1_RESETL_LS                           : out std_logic;     
     QSFP1_MODPRSL_LS                          : in  std_logic;      
     QSFP1_INTL_LS                             : in  std_logic;     
+-----------------
+    QSFP2_RESETL_LS                           : out std_logic;     
+    QSFP2_MODPRSL_LS                          : in  std_logic;      
+    QSFP2_INTL_LS                             : in  std_logic;     
+-----------------
+    QSFP3_RESETL_LS                           : out std_logic;     
+    QSFP3_MODPRSL_LS                          : in  std_logic;      
+    QSFP3_INTL_LS                             : in  std_logic;     
 -----------------
     QSFP4_SI570_CLOCK_P                       : in  std_logic;
     QSFP4_SI570_CLOCK_N                       : in  std_logic;
@@ -107,7 +114,7 @@ entity qsfp_intfc_v1_0 is
     qsfp1_capture_tvalid_512b_cnt_in          : in  std_logic_vector(31 downto 0);
     qsfp1_tx_fifo_128_aempty_cnt_in           : in  std_logic_vector(31 downto 0);
     qsfp1_capture_rx_data_ready_cnt_in        : in  std_logic_vector(31 downto 0);
-    qsfp1_tx_fifo_tvalid_128b_cnt_in                     : in  std_logic_vector(31 downto 0);
+    qsfp1_tx_fifo_tvalid_128b_cnt_in          : in  std_logic_vector(31 downto 0);
     mem_xfer_tx_upload_tvalid_128b_cnt_in     : in  std_logic_vector(31 downto 0);
     dac_tx_tvalid_128b_cnt_in                 : in  std_logic_vector(31 downto 0);
 
@@ -117,43 +124,14 @@ entity qsfp_intfc_v1_0 is
     qsfp4_playback_tvalid_240b_cnt_in         : in  std_logic_vector(31 downto 0);
     
     fiber_tx_tvalid_128b_cnt_in               : in  std_logic_vector(31 downto 0);
+    cmac_0_tx_tvalid_512b_cnt_in              : in  std_logic_vector(31 downto 0);
+    cmac_0_rx_tvalid_512b_cnt_in              : in  std_logic_vector(31 downto 0);
 
     cnt_reset_out                             : out std_logic;
 
     slv_reg9_out                              : out std_logic_vector(31 downto 0);
     slv_reg10_out                             : out std_logic_vector(31 downto 0);
    
-    slv_reg21_out                             : out std_logic_vector(31 downto 0);
-    slv_reg22_out                             : out std_logic_vector(31 downto 0);
-    slv_reg23_out                             : out std_logic_vector(31 downto 0);
-    slv_reg24_out                             : out std_logic_vector(31 downto 0);
-    slv_reg25_out                             : out std_logic_vector(31 downto 0);
-    slv_reg26_out                             : out std_logic_vector(31 downto 0);
-    slv_reg27_out                             : out std_logic_vector(31 downto 0);
-    slv_reg28_out                             : out std_logic_vector(31 downto 0);
-    slv_reg29_out                             : out std_logic_vector(31 downto 0);
-    slv_reg30_out                             : out std_logic_vector(31 downto 0);
-
-    slv_reg31_out                             : out std_logic_vector(31 downto 0);
-    slv_reg32_out                             : out std_logic_vector(31 downto 0);
-    slv_reg33_out                             : out std_logic_vector(31 downto 0);
-    slv_reg34_out                             : out std_logic_vector(31 downto 0);
-    slv_reg35_out                             : out std_logic_vector(31 downto 0);
-    slv_reg36_out                             : out std_logic_vector(31 downto 0);
-    slv_reg37_out                             : out std_logic_vector(31 downto 0);
-    slv_reg38_out                             : out std_logic_vector(31 downto 0);
-    slv_reg39_out                             : out std_logic_vector(31 downto 0);
-    slv_reg40_out                             : out std_logic_vector(31 downto 0);
-
-    slv_reg41_out                             : out std_logic_vector(31 downto 0);
-    slv_reg42_out                             : out std_logic_vector(31 downto 0);
-    slv_reg43_out                             : out std_logic_vector(31 downto 0);
-    slv_reg44_out                             : out std_logic_vector(31 downto 0);
-    slv_reg45_out                             : out std_logic_vector(31 downto 0);
-    slv_reg46_out                             : out std_logic_vector(31 downto 0);
-    slv_reg47_out                             : out std_logic_vector(31 downto 0);
-    slv_reg48_out                             : out std_logic_vector(31 downto 0);
-   
     -- User ports ends
     -- Do not modify the ports beyond this line
 
@@ -226,6 +204,16 @@ architecture arch_imp of qsfp_intfc_v1_0 is
 
   signal qsfp1_m_axis_tdata               : std_logic_vector(239 downto 0);
   signal qsfp1_m_axis_tvalid              : std_logic;
+--
+  signal qsfp2_reset_n_i                  : std_logic;   
+  signal qsfp2_modprsl                    : std_logic;   
+  signal qsfp2_intl                       : std_logic;   
+  signal qsfp2_reset_n                    : std_logic;   
+--
+  signal qsfp3_reset_n_i                  : std_logic;   
+  signal qsfp3_modprsl                    : std_logic;   
+  signal qsfp3_intl                       : std_logic;   
+  signal qsfp3_reset_n                    : std_logic;   
 --
   signal qsfp4_axis_aclk                  : std_logic;
   signal qsfp4_axis_aresetn               : std_logic;
@@ -284,10 +272,6 @@ architecture arch_imp of qsfp_intfc_v1_0 is
   signal qsfp2_clk_freq_r                 : std_logic_vector(31 downto 0) := (others => '0');
   signal qsfp2_clk_cnt_r                  : std_logic_vector(31 downto 0) := (others => '0');
 
-  signal qsfp3_clk_tick_1ms_r             : std_logic_vector(0 to 2) := (others => '0');
-  signal qsfp3_clk_freq_r                 : std_logic_vector(31 downto 0) := (others => '0');
-  signal qsfp3_clk_cnt_r                  : std_logic_vector(31 downto 0) := (others => '0');
-
   signal slv_reg0                         : std_logic_vector(31 downto 0);
   signal slv_reg1                         : std_logic_vector(31 downto 0);
   signal slv_reg2                         : std_logic_vector(31 downto 0);
@@ -375,39 +359,39 @@ begin
     slv_reg19_in                => clk_250_freq_r,                          -- 0x8000_004C 
     slv_reg20_in                => clk_250_cnt_r,                           -- 0x8000_0050
 
-    slv_reg21_out               => slv_reg21_out,                           -- 0x8000_0054  
+    slv_reg21_out               => open,                                    -- 0x8000_0054  
-    slv_reg22_out               => slv_reg22_out,                           -- 0x8000_0058
+    slv_reg22_out               => open,                                    -- 0x8000_0058
-    slv_reg23_out               => slv_reg23_out,                           -- 0x8000_005C  *
+    slv_reg23_out               => open,                                    -- 0x8000_005C  
-    slv_reg24_out               => slv_reg24_out,                           -- 0x8000_0060
+    slv_reg24_out               => open,                                    -- 0x8000_0060
-    slv_reg25_out               => slv_reg25_out,                           -- 0x8000_0064  *
+    slv_reg25_out               => open,                                    -- 0x8000_0064  
-    slv_reg26_out               => slv_reg26_out,                           -- 0x8000_0068  *
+    slv_reg26_out               => open,                                    -- 0x8000_0068  
-    slv_reg27_out               => slv_reg27_out,                           -- 0x8000_006C
+    slv_reg27_out               => open,                                    -- 0x8000_006C
-    slv_reg28_out               => slv_reg28_out,                           -- 0x8000_0070
+    slv_reg28_out               => open,                                    -- 0x8000_0070
 
-    slv_reg29_out               => slv_reg29_out,                           -- 0x8000_0074 
+    slv_reg29_out               => open,                                    -- 0x8000_0074 
-    slv_reg30_out               => slv_reg30_out,                           -- 0x8000_0078
+    slv_reg30_out               => open,                                    -- 0x8000_0078
-    slv_reg31_out               => slv_reg31_out,                           -- 0x8000_007C   *
+    slv_reg31_out               => open,                                    -- 0x8000_007C  
-    slv_reg32_out               => slv_reg32_out,                           -- 0x8000_0080
+    slv_reg32_out               => open,                                    -- 0x8000_0080
-    slv_reg33_out               => slv_reg33_out,                           -- 0x8000_0084   *
+    slv_reg33_out               => open,                                    -- 0x8000_0084  
-    slv_reg34_out               => slv_reg34_out,                           -- 0x8000_0088   *
+    slv_reg34_out               => open,                                    -- 0x8000_0088  
-    slv_reg35_out               => slv_reg35_out,                           -- 0x8000_008C
+    slv_reg35_out               => open,                                    -- 0x8000_008C
-    slv_reg36_out               => slv_reg36_out,                           -- 0x8000_0090
+    slv_reg36_out               => open,                                    -- 0x8000_0090
 
-    slv_reg37_out               => slv_reg37_out,                           -- 0x8000_0094 
+    slv_reg37_out               => open,                         --         0x8000_0094 
-    slv_reg38_out               => slv_reg38_out,                           -- 0x8000_0098
+    slv_reg38_out               => open,                         --         0x8000_0098
-    slv_reg39_out               => slv_reg39_out,                           -- 0x8000_009C   *
+    slv_reg39_out               => open,                         --         0x8000_009C  
-    slv_reg40_out               => slv_reg40_out,                           -- 0x8000_00A0
+    slv_reg40_out               => open,                         --         0x8000_00A0
-    slv_reg41_out               =>  slv_reg41_out,                          -- 0x8000_00A4   *
+    slv_reg41_out               => open,                         --         0x8000_00A4  
-    slv_reg42_out               =>  slv_reg42_out,                          -- 0x8000_00A8   *
+    slv_reg42_out               => open,                         --         0x8000_00A8  
-    slv_reg43_out               =>  slv_reg43_out,                          -- 0x8000_00AC
+    slv_reg43_out               => open,                         --         0x8000_00AC
-    slv_reg44_out               =>  slv_reg44_out,                          -- 0x8000_00B0
+    slv_reg44_out               => open,                         --         0x8000_00B0
                                                                    
-    slv_reg45_out               =>  slv_reg45_out,                          -- 0x8000_00B4 
+    slv_reg45_out               =>  open,                                   -- 0x8000_00B4 
-    slv_reg46_out               =>  slv_reg46_out,                          -- 0x8000_00B8
+    slv_reg46_out               =>  open,                                   -- 0x8000_00B8
-    slv_reg47_out               =>  slv_reg47_out,                          -- 0x8000_00BC   *
+    slv_reg47_in                =>  cmac_0_tx_tvalid_512b_cnt_in,           -- 0x8000_00BC  
-    slv_reg48_out               =>  slv_reg48_out,                          -- 0x8000_00C0
+    slv_reg48_in                =>  cmac_0_rx_tvalid_512b_cnt_in,           -- 0x8000_00C0
-    slv_reg49_in                =>  qsfp1_capture_tvalid_512b_cnt_in,       -- 0x8000_00C4   *
+    slv_reg49_in                =>  qsfp1_capture_tvalid_512b_cnt_in,       -- 0x8000_00C4  
-    slv_reg50_in                =>  dig_iq_interface_ready_0_cnt_r,         -- 0x8000_00C8   *
+    slv_reg50_in                =>  dig_iq_interface_ready_0_cnt_r,         -- 0x8000_00C8  
     slv_reg51_in                =>  dig_iq_interface_ready_1_cnt_r,         -- 0x8000_00CC
     slv_reg52_in                =>  adc_rx_tvalid_128b_overflow_cnt_in,     -- 0x8000_00D0
 
@@ -415,7 +399,7 @@ begin
     slv_reg54_in                =>  qsfp1_capture_overflow_240b_cnt_in,     --  0x8000_00D8
 
     slv_reg55_in                =>  qsfp4_playback_tvalid_128b_cnt_in,      --  0x8000_00DC
-    slv_reg56_in                =>  qsfp1_tx_fifo_tvalid_128b_cnt_in,                  --  0x8000_00E0
+    slv_reg56_in                =>  qsfp1_tx_fifo_tvalid_128b_cnt_in,       --  0x8000_00E0
     slv_reg57_in                =>  mem_xfer_tx_upload_tvalid_128b_cnt_in,  --  0x8000_00E4
     slv_reg58_in                =>  adc_rx_tvalid_128b_cnt_in,              --  0x8000_00E8
     slv_reg59_in                =>  fiber_tx_tvalid_128b_cnt_in,            --  0x8000_00EC
@@ -455,12 +439,12 @@ begin
   slv_reg1(2)               <= qsfp1_intl;    
   slv_reg1(3)               <= '0';
   slv_reg1(4)               <= '0';     --dig_iq_interface_ready_1(0);              
-  slv_reg1(5)               <= '1';     --qsfp2_modprsl;
+  slv_reg1(5)               <= qsfp2_modprsl;
-  slv_reg1(6)               <= '1';     --qsfp2_intl;   
+  slv_reg1(6)               <= qsfp2_intl;   
   slv_reg1(7)               <= '0';
   slv_reg1(8)               <= '0';     --dig_iq_interface_ready_1(1);          
-  slv_reg1(9)               <= '1';     --qsfp3_modprsl; 
+  slv_reg1(9)               <= qsfp3_modprsl; 
-  slv_reg1(10)              <= '1';     --qsfp3_intl;    
+  slv_reg1(10)              <= qsfp3_intl;    
   slv_reg1(11)              <= '0';
   slv_reg1(12)              <= dig_iq_interface_ready(1);               
   slv_reg1(13)              <= qsfp4_modprsl; 
@@ -477,7 +461,9 @@ begin
 --
   dig_iq_cmd_strb_i         <= slv_reg5(0);                  -- 0x8000_0014 
   qsfp1_reset_n_i           <= slv_reg5(16);
-  qsfp4_reset_n_i           <= slv_reg5(24);
+  qsfp2_reset_n_i           <= slv_reg5(20);
+  qsfp3_reset_n_i           <= slv_reg5(24);
+  qsfp4_reset_n_i           <= slv_reg5(28);
 --
   dig_iq_cmd_wdata_i        <= slv_reg6(31 downto 0);        -- 0x8000_0018 
 --
@@ -512,6 +498,14 @@ begin
   QSFP1_RESETL_LS     <= qsfp1_reset_n; 
   qsfp1_modprsl       <= QSFP1_MODPRSL_LS;
   qsfp1_intl          <= QSFP1_INTL_LS;    
+-------
+  QSFP2_RESETL_LS     <= qsfp2_reset_n; 
+  qsfp2_modprsl       <= QSFP2_MODPRSL_LS;
+  qsfp2_intl          <= QSFP2_INTL_LS;    
+-------
+  QSFP3_RESETL_LS     <= qsfp3_reset_n; 
+  qsfp3_modprsl       <= QSFP3_MODPRSL_LS;
+  qsfp3_intl          <= QSFP3_INTL_LS;    
 -------
   QSFP4_TX1_P         <= qsfp4_tx_txp(0);
   QSFP4_TX1_N         <= qsfp4_tx_txn(0);
@@ -545,6 +539,8 @@ begin
     
   qsfp1_reset_n               <= qsfp1_reset_n_i; 
   dig_iq_interface_reset(0)   <= not qsfp1_reset_n;
+  qsfp2_reset_n               <= qsfp2_reset_n_i; 
+  qsfp3_reset_n               <= qsfp3_reset_n_i; 
   qsfp4_reset_n               <= qsfp4_reset_n_i; 
   dig_iq_interface_reset(1)   <= not qsfp4_reset_n;
     
@@ -870,20 +866,6 @@ begin
     end if;
   end process;
   
-  process(qsfp3_clk_in)
-  begin
-    if (rising_edge(qsfp3_clk_in)) then
-      qsfp3_clk_tick_1ms_r      <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms;
-      if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then 
-        qsfp3_clk_freq_r        <= qsfp3_clk_cnt_r;
-        qsfp3_clk_cnt_r         <= (others => '0');
-      else
-        qsfp3_clk_cnt_r         <= qsfp3_clk_cnt_r + 1;
-      end if;
-    end if;
-  end process;
-
-  
   process(pl_clk3_0)
   begin
     if (rising_edge(pl_clk3_0)) then

ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd

@@ -68,8 +68,8 @@ entity qsfp_intfc_v1_0_S00_AXI is
    slv_reg44_out        :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    slv_reg45_out        :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    slv_reg46_out        :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-   slv_reg47_out        :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+   slv_reg47_in         :in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-   slv_reg48_out        :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+   slv_reg48_in         :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    slv_reg49_in         :in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    slv_reg50_in         :in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
    slv_reg51_in         :in  std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
@@ -374,41 +374,41 @@ begin
         slv_reg19 <= (others => '0');
         slv_reg20 <= (others => '0');
 
-        slv_reg21 <= x"00008000";     --(UP-SWEEP)   from 1MHz to 5MHz in 5uS
+        slv_reg21 <= (others => '0');
-        slv_reg22 <= x"00000000";
+        slv_reg22 <= (others => '0');
-        slv_reg23 <= x"0000D6BF";
+        slv_reg23 <= (others => '0');
-        slv_reg24 <= x"00000000";
+        slv_reg24 <= (others => '0');
-        slv_reg25 <= x"000004E2";     --(~5 us)
+        slv_reg25 <= (others => '0');
-        slv_reg26 <= x"010624DD";     --(~1 MHz)
+        slv_reg26 <= (others => '0');
-        slv_reg27 <= x"00000000";
+        slv_reg27 <= (others => '0');
-        slv_reg28 <= x"00008000";
+        slv_reg28 <= (others => '0');
 
-        slv_reg29 <= x"00008000";     --(DOWN-SWEEP)
+        slv_reg29 <= (others => '0');
-        slv_reg30 <= x"00000000";
+        slv_reg30 <= (others => '0');
-        slv_reg31 <= x"00FEF391";   
+        slv_reg31 <= (others => '0');
-        slv_reg32 <= x"00000000";
+        slv_reg32 <= (others => '0');
-        slv_reg33 <= x"000004E2";     --(~5 us)
+        slv_reg33 <= (others => '0');
-        slv_reg34 <= x"0624DD2F";     --(~6 MHz)
+        slv_reg34 <= (others => '0');
-        slv_reg35 <= x"00000000";
+        slv_reg35 <= (others => '0');
-        slv_reg36 <= x"00008000";
+        slv_reg36 <= (others => '0');
 
-        slv_reg37 <= x"00008000";     --(CW)
+        slv_reg37 <= (others => '0');
-        slv_reg38 <= x"00000000";
+        slv_reg38 <= (others => '0');
-        slv_reg39 <= x"00000000";
+        slv_reg39 <= (others => '0');
-        slv_reg40 <= x"00000000";
+        slv_reg40 <= (others => '0');
-        slv_reg41 <= x"000004E2";    --(~5 us)
+        slv_reg41 <= (others => '0');
-        slv_reg42 <= x"0A3D70A3";    --(~10 MHz)
+        slv_reg42 <= (others => '0');
-        slv_reg43 <= x"00000000";
+        slv_reg43 <= (others => '0');
-        slv_reg44 <= x"00008000";
+        slv_reg44 <= (others => '0');
 
-        slv_reg45 <= x"00008000";    --(CW)
+        slv_reg45 <= (others => '0');
-        slv_reg46 <= x"00000000";
+        slv_reg46 <= (others => '0');
-        slv_reg47 <= x"00000000";
+        slv_reg47 <= (others => '0');
-        slv_reg48 <= x"00000000";
+        slv_reg48 <= (others => '0');
-        slv_reg49 <= x"000004E2";   --(~5 us)
+        slv_reg49 <= (others => '0');
-        slv_reg50 <= x"0F5C28F5";    --(~15 MHz)
+        slv_reg50 <= (others => '0');
-        slv_reg51 <= x"00000000";
+        slv_reg51 <= (others => '0');
-        slv_reg52 <= x"00008000";
+        slv_reg52 <= (others => '0');
 
         slv_reg53 <= (others => '0');
         slv_reg54 <= (others => '0');
@@ -1202,9 +1202,9 @@ begin
         when b"101110" =>
           reg_data_out <= slv_reg46;   
         when b"101111" =>
-          reg_data_out <= slv_reg47;   
+          reg_data_out <= slv_reg47_in;   
         when b"110000" =>
-          reg_data_out <= slv_reg48;   
+          reg_data_out <= slv_reg48_in;   
         when b"110001" =>
           reg_data_out <= slv_reg49_in;  --slv_reg49;   
         when b"110010" =>
@@ -1314,8 +1314,6 @@ begin
   slv_reg44_out   <= slv_reg44;
   slv_reg45_out   <= slv_reg45;
   slv_reg46_out   <= slv_reg46;
-  slv_reg47_out   <= slv_reg47;
-  slv_reg48_out   <= slv_reg48;
       
   -- User logic ends
 

sim/dds_wrapper_tb.vhd

@@ -1,316 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   16:53:22 03/24/2017
--- Design Name:   
--- Module Name:   
--- Project Name:  xem7350
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: dac_interface
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE IEEE.STD_LOGIC_arith.ALL;
-USE IEEE.STD_LOGIC_unsigned.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
-
-Library xpm;
-use xpm.vcomponents.all;
-
---library UNISIM;
---use UNISIM.VComponents.all;
- 
-entity dds_wrapper_tb is
-end dds_wrapper_tb;
- 
-architecture behavior of dds_wrapper_tb is 
- 
-   -- Clock period definitions
-  constant CLK_125_PERIOD           : time := 8 ns;    -- 125 MHz
-  constant CLK_250_PERIOD           : time := 4 ns;    -- 250 MHz        
-  constant CLK_100_PERIOD           : time := 10 ns;   -- 100 MHz
-  constant S_AXI_ACLK_PERIOD        : time := 10 ns;   -- 100 MHz
-  constant M_AXI_ACLK_PERIOD        : time := 4 ns;    -- 250 MHz       2.58 ns;  -- 387 MHz    
-  constant QSFP4_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     
-  constant QSFP1_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     
-
-  signal clk_100                    : std_logic :=  '0';
-  signal clk_100_aresetn            : std_logic_vector(0 to 15) := (others => '0');
-  signal clk_250                    : std_logic :=  '0';
-  signal clk_250_aresetn            : std_logic_vector(0 to 63) := x"0000_FFFF_0000_0000";--(others => '0');
-
-   signal m_axis_tready_r           : std_logic := '0';
-   signal m_axis_tdata                              : std_logic_vector(127 downto 0);
-   signal m_axis_tvalid                             : std_logic;
-   signal m_axis_tready                             : std_logic;
- 
-  signal util_mxfe_upack_s_axis_tdata_pipe          : std_logic_vector(127 downto 0);
-    signal util_mxfe_upack_s_axis_tvalid_pipe       : std_logic;
-
-    signal m_axis_tdata_1                           : std_logic_vector(127 downto 0);
-   signal m_axis_tvalid_1                           : std_logic;
-   signal m_axis_tready_1                           : std_logic;  
-
-   signal cmd_send_i                                : std_logic_vector(0 to 3) := (others => '0');
-   signal dac_holdoff_r                             : std_logic := '1';
-
-    signal chan1_i                           : std_logic_vector(15 downto 0);
-    signal chan1_q                           : std_logic_vector(15 downto 0);
-    signal chan2_i                           : std_logic_vector(15 downto 0);
-    signal chan2_q                           : std_logic_vector(15 downto 0);
-    signal chan3_i                           : std_logic_vector(15 downto 0);
-    signal chan3_q                           : std_logic_vector(15 downto 0);
-    signal chan4_i                           : std_logic_vector(15 downto 0);
-    signal chan4_q                           : std_logic_vector(15 downto 0);
-  
-  signal cmd_send_0_r                   : std_logic_vector(0 to 2) := (others => '0');
-  signal cmd_send_1_r                   : std_logic_vector(0 to 2) := (others => '0');
-  signal cmd_send_2_r                   : std_logic_vector(0 to 2) := (others => '0');
-  signal cmd_send_3_r                   : std_logic_vector(0 to 2) := (others => '0');
-  signal cnt_reset                      : std_logic := '0';
-
-begin
- 
-  clk_100  <= not clk_100 after CLK_100_PERIOD/2;
-  clk_250  <= not clk_250 after CLK_250_PERIOD/2;
-
-
---
-  process(clk_100)
-  begin
-    if (rising_edge(clk_100)) then
-      clk_100_aresetn     <= clk_100_aresetn(1 to 15) & '1';
-    end if;
-  end process;
-
---
-  process(clk_250)
-  begin
-    if (rising_edge(clk_250)) then
-      clk_250_aresetn     <= clk_250_aresetn(1 to 63) & '1';
-    end if;
-  end process;      
-
-
-  process (clk_100)
-  begin
-    if rising_edge(clk_100) then
-      if (cmd_send_i(0) = '1') then                                     
-        cmd_send_0_r      <= "111";
-      else
-        cmd_send_0_r      <= cmd_send_0_r(1 to 2) & '0';
-      end if;
-
-      if (cmd_send_i(1) = '1') then
-        cmd_send_1_r      <= "111";
-      else
-        cmd_send_1_r      <= cmd_send_1_r(1 to 2) & '0';
-      end if;
-
-      if (cmd_send_i(2) = '1') then
-        cmd_send_2_r      <= "111";
-      else
-        cmd_send_2_r      <= cmd_send_2_r(1 to 2) & '0';
-      end if;
-
-      if (cmd_send_i(3) = '1') then
-        cmd_send_3_r      <= "111";
-      else
-        cmd_send_3_r      <= cmd_send_3_r(1 to 2) & '0';
-      end if;
-    end if;
-  end process;
-
-      
-  i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4 
-    port map ( 
-      s_axi_aclk_in                     => clk_100,          
-      s_axi_aresetn_in                  => clk_100_aresetn(0),    
-
-      cmd_idx_in                        => "000",
-      dac_holdoff_in                    => dac_holdoff_r,
-      dds_chan_en_in                    => "1111",
-
-      cmd_send_0_in                     => cmd_send_0_r(0),  
-      scale_0_in                        => x"8000",
-      dds_phase_inc_dwell_time_0_in     => x"00000000",
-      dds_phase_inc_step_size_0_in      => x"0000D6BF",
-      idle_samples_0_in                 => x"00000000",
-      dds_samples_0_in                  => x"000004E2",
-      phase_inc_0_in                    => x"010624DD",
-      phase_off_0_in                    => x"00000000",
-      swap_sf_0_in                      => x"00008000",
-
-      cmd_send_1_in                     => cmd_send_1_r(0),  
-      scale_1_in                        => x"8000",
-      dds_phase_inc_dwell_time_1_in     => x"00000000",
-      dds_phase_inc_step_size_1_in      => x"0000D6BF",
-      idle_samples_1_in                 => x"00000000",
-      dds_samples_1_in                  => x"000014E2",    --x"000004E2",
-      phase_inc_1_in                    => x"010624DD",
-      phase_off_1_in                    => x"00000000",
-      swap_sf_1_in                      => x"00008000",
-
-      cmd_send_2_in                     => cmd_send_2_r(0),  
-      scale_2_in                        => x"8000",
-      dds_phase_inc_dwell_time_2_in     => x"00000000",
-      dds_phase_inc_step_size_2_in      => x"0000D6BF",
-      idle_samples_2_in                 => x"00000000",
-      dds_samples_2_in                  => x"000004E2",
-      phase_inc_2_in                    => x"010624DD",
-      phase_off_2_in                    => x"00000000",
-      swap_sf_2_in                      => x"00008000",
-
-      cmd_send_3_in                     => cmd_send_3_r(0),  
-      scale_3_in                        => x"8000",
-      dds_phase_inc_dwell_time_3_in     => x"00000000",
-      dds_phase_inc_step_size_3_in      => x"0000D6BF",
-      idle_samples_3_in                 => x"00000000",
-      dds_samples_3_in                  => x"000004E2",
-      phase_inc_3_in                    => x"010624DD",
-      phase_off_3_in                    => x"00000000",
-      swap_sf_3_in                      => x"00008000",
-
-      m_axis_aclk_in                    => clk_250,     
-      m_axis_aresetn_in                 => clk_250_aresetn(0),
-      m_axis_tdata_out                  => m_axis_tdata,            
-      m_axis_tvalid_out                 => m_axis_tvalid,         
-      m_axis_tready_in                  => m_axis_tready,          
-      
-      cnt_reset_in                      => cnt_reset,
-      m_axis_tvalid_cnt_out             => open,        
-      dds_pulse_data_cnt_out            => open
-      );
-
-  
-   -- big FIFO before JESD TX PORT
-  i_dac_data_fifo_32kx128 : entity work.axis_data_fifo_32kx128  
-    port map (
-    s_axis_aclk                   => clk_250,                       -- in
-    s_axis_aresetn                => clk_250_aresetn(0),                 -- in
-    s_axis_tdata                  => m_axis_tdata,          -- in
-    s_axis_tvalid                 => m_axis_tvalid,         -- in
-    s_axis_tready                 => m_axis_tready,    -- out
-
-    m_axis_tdata                  => m_axis_tdata_1,     -- out                       
-    m_axis_tvalid                 => m_axis_tvalid_1,    -- out                       
-    m_axis_tready                 => m_axis_tready_1        -- in                        
-    );
-
-   -- big FIFO before JESD TX PORT
-  i_dac_data_fifo_32kx128_1 : entity work.axis_data_fifo_32kx128  
-    port map (
-    s_axis_aclk                   => clk_250,                       -- in
-    s_axis_aresetn                => clk_250_aresetn(0),                 -- in
-    s_axis_tdata                  => m_axis_tdata_1,          -- in
-    s_axis_tvalid                 => m_axis_tvalid_1,         -- in
-    s_axis_tready                 => m_axis_tready_1,    -- out
-
-    m_axis_tdata                  => util_mxfe_upack_s_axis_tdata_pipe,     -- out                       
-    m_axis_tvalid                 => util_mxfe_upack_s_axis_tvalid_pipe,    -- out                       
-    m_axis_tready                 => m_axis_tready_r        -- in                        
-    );
-
-
-  chan1_i <= util_mxfe_upack_s_axis_tdata_pipe(15  downto 0);
-  chan1_q <= util_mxfe_upack_s_axis_tdata_pipe(31  downto 16);
-
-  chan2_i <= util_mxfe_upack_s_axis_tdata_pipe(47  downto 32);
-  chan2_q <= util_mxfe_upack_s_axis_tdata_pipe(63  downto 48);
-
-  chan3_i <= util_mxfe_upack_s_axis_tdata_pipe(79  downto 64);
-  chan3_q <= util_mxfe_upack_s_axis_tdata_pipe(95  downto 80);
-
-  chan4_i <= util_mxfe_upack_s_axis_tdata_pipe(111 downto 96);
-  chan4_q <= util_mxfe_upack_s_axis_tdata_pipe(127 downto 112);
-   
-    -- Stimulus process
-  stim_proc: process
-  begin   
-
-    wait until clk_100_aresetn(0) = '1';
-
-   -- wait for 24 us;
-
-    wait until rising_edge(clk_250);
-    m_axis_tready_r   <= '1';
-    wait for 1 us;   
-    
-    wait until rising_edge(clk_100);
-    cmd_send_i(0)     <= '1';
-    wait for 200 ns;   
-    wait until rising_edge(clk_100);
-    cmd_send_i(0)     <= '0';
-    wait for 1 us;   
-    wait until rising_edge(clk_100);
-    cmd_send_i(1)     <= '1';
-    wait for 200 ns;   
-    wait until rising_edge(clk_100);
-    cmd_send_i(1)     <= '0';
-
-    wait for 1 us;   
-    wait until rising_edge(clk_100);
-    cmd_send_i(2)     <= '1';
-    wait for 200 ns;   
-    wait until rising_edge(clk_100);
-    cmd_send_i(2)     <= '0';
-
-    wait for 1 us;   
-    wait until rising_edge(clk_100);
-    cmd_send_i(3)     <= '1';
-    wait for 200 ns;   
-    wait until rising_edge(clk_100);
-    cmd_send_i(3)     <= '0';   
-    
-    wait for 1 us;   
-    wait until rising_edge(clk_100);
-    dac_holdoff_r  <= '0';           
-
-    
-    wait for 8 us;   
-    cnt_reset     <= '1';
-    wait until rising_edge(clk_100);
-    cnt_reset     <= '0';
-
- --    m_axis_tready_r   <= '0';  
- --    wait until rising_edge(clk_250);    
-  
-
- --    m_axis_tready_r   <= '1';         
- --    wait until rising_edge(clk_250);    
-  
-
- --    m_axis_tready_r   <= '0';           
- --     wait until rising_edge(clk_250);    
-  
-
- --    m_axis_tready_r   <= '1';             
-                
-    wait until rising_edge(clk_100);
-    
-    wait;  -- wait here forever
-  end process;
-  
-  
-
-end;

sim/tb_cap_plybk.vhd

@@ -1,286 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   16:53:22 03/24/2017
--- Design Name:   
--- Module Name:   
--- Project Name:  xem7350
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: dac_interface
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE IEEE.STD_LOGIC_arith.ALL;
-USE IEEE.STD_LOGIC_unsigned.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
-entity tb_cap_plybk is
-end tb_cap_plybk;
- 
-architecture behavior of tb_cap_plybk is 
- 
-  constant C_M_AXI_DATA_WIDTH             : integer := 32;
-  constant C_M_AXI_ADDR_WIDTH             : integer := 32;
-
-   -- Clock period definitions
-  constant CLK_125_PERIOD           : time := 8 ns;    -- 125 MHz
-  constant CLK_250_PERIOD           : time := 4 ns;    -- 250 MHz        
-  constant S_AXI_ACLK_PERIOD        : time := 10 ns;   -- 100 MHz
-  constant M_AXI_ACLK_PERIOD        : time := 4 ns;    -- 250 MHz       2.58 ns;  -- 387 MHz    
-  constant QSFP4_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     
-  constant QSFP1_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     
-
-  signal clk_125                    : std_logic :=  '0';
-  signal clk_125_aresetn            : std_logic_vector(0 to 15) := (others => '0');
-  signal clk_125_reset              : std_logic;
-  
-  signal clk_250                    : std_logic :=  '0';
-  signal clk_250_aresetn            : std_logic_vector(0 to 15) := (others => '0');
-  signal clk_250_areset             : std_logic;
-
-  signal tx_device_clk_1            : std_logic :=  '0';
-  signal tx_device_clk_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
-  signal tx_device_clk_aresetn      : std_logic;
-
-  signal rx_device_clk_1            : std_logic :=  '0';
-  signal rx_device_clk_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
-  signal rx_device_clk_aresetn      : std_logic;
-  signal rx_device_clk_areset       : std_logic;
-
-  signal qsfp4_playback_aclk        : std_logic :=  '0';
-  signal qsfp4_axis_aresetn_r       : std_logic_vector(0 to 15) := (others => '0');
-  signal qsfp4_playback_aresetn     : std_logic;
-
-  signal qsfp1_capture_aclk         : std_logic;
-  signal qsfp1_axis_aresetn_r       : std_logic_vector(0 to 15) := (others => '0');
-  signal qsfp1_capture_aresetn      : std_logic;
-
-  
---
-  signal tick_1ms                         : std_logic;
-
-  signal clk_125_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
-  signal clk_125_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
-  signal clk_125_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');
-
-  signal clk_250_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
-  signal clk_250_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
-  signal clk_250_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');
-
-
-  signal adc_rx_tdata_128b            : std_logic_vector(127 downto 0) := (others => '0');
-  signal adc_rx_tvalid_128b           : std_logic := '0';
-  signal adc_rx_tready_128b           : std_logic;
-  signal adc_rx_tvalid_128b_cnt       : std_logic_vector(31 downto 0);  
-
-
-
-  signal qsfp4_playback_tdata_240b    : std_logic_vector(239 downto 0); 
-  signal qsfp4_playback_tvalid_240b   : std_logic;
-  signal qsfp4_playback_tready_240b   : std_logic := '1';
-  
-
-  signal qsfp1_capture_tdata_240b    : std_logic_vector(239 downto 0); 
-  signal qsfp1_capture_tvalid_240b   : std_logic;
-
-
-  signal tx_tdata_128b   : std_logic_vector(127 downto 0);                 
-  signal tx_tvalid_128b  : std_logic;              
-  signal tx_tready_128b  : std_logic := '1';                
-
-  signal qsfp1_capture_rx_data_ready  : std_logic;
-  
-  signal playback_data_path_enable_n   : std_logic := '1';   
-
-  signal adc_rx_tvalid_128b_ena         : std_logic;
-
-begin
- 
-  clk_125  <= not clk_125 after CLK_125_PERIOD/2;
-  clk_250  <= not clk_250 after CLK_250_PERIOD/2; 
-  tx_device_clk_1  <= not tx_device_clk_1 after CLK_250_PERIOD/2; 
-  rx_device_clk_1  <= not rx_device_clk_1 after CLK_250_PERIOD/2; 
-
-  qsfp4_playback_aclk  <= not qsfp4_playback_aclk after QSFP4_AXIS_ACLK_PERIOD/2; 
---  qsfp1_capture_aclk  <= not qsfp1_capture_aclk after QSFP1_AXIS_ACLK_PERIOD/2; 
-
---
-  process(clk_125)
-  begin
-    if (rising_edge(clk_125)) then
-      clk_125_aresetn     <= clk_125_aresetn(1 to 15) & '1';
-    end if;
-  end process;
-
-  process(clk_125)
-  begin
-    if (rising_edge(clk_125)) then
-      clk_125_aresetn     <= clk_125_aresetn(1 to 15) & '1';
-    end if;
-  end process;
-  
-  clk_125_reset  <= not clk_125_aresetn(0);
---  
-  process(clk_250)
-  begin
-    if (rising_edge(clk_250)) then
-      clk_250_aresetn     <= clk_250_aresetn(1 to 15) & '1';
-    end if;
-  end process;
-  
-  clk_250_areset  <= not clk_250_aresetn(0);
---
-  process(tx_device_clk_1)
-  begin
-    if (rising_edge(tx_device_clk_1)) then
-      tx_device_clk_aresetn_r     <= tx_device_clk_aresetn_r(1 to 15) & '1';
-    end if;
-  end process;
-
-  tx_device_clk_aresetn  <= tx_device_clk_aresetn_r(0);
-
---
-  process(rx_device_clk_1)
-  begin
-    if (rising_edge(rx_device_clk_1)) then
-      rx_device_clk_aresetn_r     <= rx_device_clk_aresetn_r(1 to 15) & '1';
-    end if;
-  end process;
-
-  rx_device_clk_aresetn  <= rx_device_clk_aresetn_r(0);
-
---
-  process(qsfp4_playback_aclk)
-  begin
-    if (rising_edge(qsfp4_playback_aclk)) then
-      qsfp4_axis_aresetn_r     <= qsfp4_axis_aresetn_r(1 to 15) & '1';
-    end if;
-  end process;
-
-  qsfp4_playback_aresetn  <= qsfp4_axis_aresetn_r(0);
-
-
---
-  process(rx_device_clk_1)
-  begin
-    if (rising_edge(rx_device_clk_1)) then
-      adc_rx_tdata_128b     <= adc_rx_tdata_128b + x"0003_0002_0001_0004_0005_0006_0007_0008";
-    end if;
-  end process;
-
---
-  process(qsfp1_capture_aclk)
-  begin
-    if (rising_edge(qsfp1_capture_aclk)) then
-      qsfp1_axis_aresetn_r     <= qsfp1_axis_aresetn_r(1 to 15) & '1';
-    end if;
-  end process;
-
-  qsfp1_capture_aresetn  <= qsfp1_axis_aresetn_r(0);
-
-  adc_rx_tvalid_128b_ena <= adc_rx_tvalid_128b and qsfp1_capture_rx_data_ready;
-   
-  i_qsfp4_playback_intfc : entity work.qsfp4_playback_intfc  
-  port map (
-    rx_device_clk_in                      => rx_device_clk_1,    
-    rx_device_clk_aresetn_in              => rx_device_clk_aresetn, 
-    rx_tdata_128b_in                      => adc_rx_tdata_128b,
-    rx_tvalid_128b_in                     => adc_rx_tvalid_128b_ena,
-    rx_tready_128b_out                    => adc_rx_tready_128b,
-    rx_tvalid_128b_cnt_out                => adc_rx_tvalid_128b_cnt,
-    rx_tvalid_128b_en_cnt_out             => open,
-    playback_data_path_enable_n_in        => playback_data_path_enable_n,
-
-    qsfp4_playback_aclk_in                => qsfp4_playback_aclk,  
-    qsfp4_playback_aresetn_in             => qsfp4_playback_aresetn, 
-    qsfp4_playback_tdata_240b_out         => qsfp4_playback_tdata_240b, 
-    qsfp4_playback_tvalid_240b_out        => qsfp4_playback_tvalid_240b,
-    qsfp4_playback_tready_240b_in         => qsfp4_playback_tready_240b,            
-    qsfp4_playback_tvalid_240b_cnt_out    => open,               
-
-    cnt_reset_in                          => '0'
-    );
-
---///////////////////////////////
-
-    qsfp1_capture_aclk            <= qsfp4_playback_aclk;       --   
-    qsfp1_capture_tdata_240b      <= qsfp4_playback_tdata_240b; --   
-    qsfp1_capture_tvalid_240b     <= qsfp4_playback_tvalid_240b; --  
-
-
---///////////////////////////////
---// ****>>>> FROM QSFP1 CAPTURE INTERFACE
-  i_qsfp1_capture_intfc : entity work.qsfp1_capture_intfc  
-  port map (
-    qsfp1_capture_aclk_in                           => qsfp1_capture_aclk,   
-    qsfp1_capture_aresetn_in                        => qsfp1_capture_aresetn,
-    qsfp1_capture_tdata_240b_in                     => qsfp1_capture_tdata_240b,
-    qsfp1_capture_tvalid_240b_in                    => qsfp1_capture_tvalid_240b,
-    qsfp1_capture_tvalid_240b_cnt_out               => open,                      
-    qsfp1_capture_fifo_aempty_512b_cnt_out          => open,                 
-    qsfp1_capture_iq_240b_to_512b_overflow_cnt_out  => open,               
-
-    qsfp1_capture_rx_data_ready_out                 => qsfp1_capture_rx_data_ready,                              
-    qsfp1_capture_rx_data_ready_cnt_out             => open,                          
-
-    tx_device_clk_in                                => tx_device_clk_1,
-    tx_device_clk_aresetn_in                        => tx_device_clk_aresetn,
-    tx_tdata_128b_out                               => tx_tdata_128b,     -- out         
-    tx_tvalid_128b_out                              => tx_tvalid_128b,    -- out         
-    tx_tready_128b_in                               => tx_tready_128b,        -- in  
-    tx_tvalid_128b_cnt_out                          => open,                   
-
-    cnt_reset_in                                    => '0'
-    );
-
-
-  
-    -- Stimulus process
-  stim_proc: process
-  begin   
-
-    wait until rx_device_clk_aresetn = '1';
-
-    wait for 200 ns;
-
-      
-    wait until rising_edge(rx_device_clk_1);
-    adc_rx_tvalid_128b     <= '1';
-    
-    wait for 500 ns;
-    wait until rising_edge(rx_device_clk_1);
-    playback_data_path_enable_n  <= '0';
-
-    wait for 5 us;
-    wait until rising_edge(qsfp4_playback_aclk);
-    playback_data_path_enable_n  <='0';
-    
-    wait for 5 us;
-    wait until rising_edge(qsfp4_playback_aclk);
-    qsfp4_playback_tready_240b  <='1';
-    
-    wait;  -- wait here forever
-  end process;
-  
-
-end;

sim/tb_cap_plybk_behav.wcfg

@@ -1,141 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<wave_config>
-   <wave_state>
-   </wave_state>
-   <db_ref_list>
-      <db_ref path="tb_cap_plybk_behav.wdb" id="1">
-         <top_modules>
-            <top_module name="\$unit_xpm_cdc_sv_220102727 " />
-            <top_module name="glbl" />
-            <top_module name="tb_cap_plybk" />
-            <top_module name="vcomponents" />
-         </top_modules>
-      </db_ref>
-   </db_ref_list>
-   <zoom_setting>
-      <ZoomStartTime time="0.000000 us"></ZoomStartTime>
-      <ZoomEndTime time="16.000001 us"></ZoomEndTime>
-      <Cursor1Time time="1.268070 us"></Cursor1Time>
-   </zoom_setting>
-   <column_width_setting>
-      <NameColumnWidth column_width="375"></NameColumnWidth>
-      <ValueColumnWidth column_width="73"></ValueColumnWidth>
-   </column_width_setting>
-   <WVObjectSize size="29" />
-   <wvobject type="logic" fp_name="/tb_cap_plybk/rx_device_clk_1">
-      <obj_property name="ElementShortName">rx_device_clk_1</obj_property>
-      <obj_property name="ObjectShortName">rx_device_clk_1</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/rx_device_clk_aresetn_r">
-      <obj_property name="ElementShortName">rx_device_clk_aresetn_r[0:15]</obj_property>
-      <obj_property name="ObjectShortName">rx_device_clk_aresetn_r[0:15]</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/rx_device_clk_aresetn">
-      <obj_property name="ElementShortName">rx_device_clk_aresetn</obj_property>
-      <obj_property name="ObjectShortName">rx_device_clk_aresetn</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_aclk">
-      <obj_property name="ElementShortName">qsfp4_playback_aclk</obj_property>
-      <obj_property name="ObjectShortName">qsfp4_playback_aclk</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/qsfp4_axis_aresetn_r">
-      <obj_property name="ElementShortName">qsfp4_axis_aresetn_r[0:15]</obj_property>
-      <obj_property name="ObjectShortName">qsfp4_axis_aresetn_r[0:15]</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_aresetn">
-      <obj_property name="ElementShortName">qsfp4_playback_aresetn</obj_property>
-      <obj_property name="ObjectShortName">qsfp4_playback_aresetn</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/adc_rx_tdata_128b">
-      <obj_property name="ElementShortName">adc_rx_tdata_128b[127:0]</obj_property>
-      <obj_property name="ObjectShortName">adc_rx_tdata_128b[127:0]</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tvalid_128b">
-      <obj_property name="ElementShortName">adc_rx_tvalid_128b</obj_property>
-      <obj_property name="ObjectShortName">adc_rx_tvalid_128b</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tready_128b">
-      <obj_property name="ElementShortName">adc_rx_tready_128b</obj_property>
-      <obj_property name="ObjectShortName">adc_rx_tready_128b</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tdata_128b_overflow">
-      <obj_property name="ElementShortName">adc_rx_tdata_128b_overflow</obj_property>
-      <obj_property name="ObjectShortName">adc_rx_tdata_128b_overflow</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/rx_tvalid_128b_cnt_out">
-      <obj_property name="ElementShortName">rx_tvalid_128b_cnt_out[31:0]</obj_property>
-      <obj_property name="ObjectShortName">rx_tvalid_128b_cnt_out[31:0]</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/rx_tvalid_128b_en_cnt_out">
-      <obj_property name="ElementShortName">rx_tvalid_128b_en_cnt_out[31:0]</obj_property>
-      <obj_property name="ObjectShortName">rx_tvalid_128b_en_cnt_out[31:0]</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/qsfp4_playback_tdata_240b">
-      <obj_property name="ElementShortName">qsfp4_playback_tdata_240b[239:0]</obj_property>
-      <obj_property name="ObjectShortName">qsfp4_playback_tdata_240b[239:0]</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/qsfp4_playback_tvalid_240b">
-      <obj_property name="ElementShortName">qsfp4_playback_tvalid_240b</obj_property>
-      <obj_property name="ObjectShortName">qsfp4_playback_tvalid_240b</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_tready_240b">
-      <obj_property name="ElementShortName">qsfp4_playback_tready_240b</obj_property>
-      <obj_property name="ObjectShortName">qsfp4_playback_tready_240b</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/qsfp4_playback_tvalid_240b_cnt_out">
-      <obj_property name="ElementShortName">qsfp4_playback_tvalid_240b_cnt_out[31:0]</obj_property>
-      <obj_property name="ObjectShortName">qsfp4_playback_tvalid_240b_cnt_out[31:0]</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/playback_data_path_enable_n">
-      <obj_property name="ElementShortName">playback_data_path_enable_n</obj_property>
-      <obj_property name="ObjectShortName">playback_data_path_enable_n</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/qsfp1_capture_tdata_240b">
-      <obj_property name="ElementShortName">qsfp1_capture_tdata_240b[239:0]</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_capture_tdata_240b[239:0]</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/qsfp1_capture_tvalid_240b">
-      <obj_property name="ElementShortName">qsfp1_capture_tvalid_240b</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_capture_tvalid_240b</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/qsfp1_capture_rx_data_ready">
-      <obj_property name="ElementShortName">qsfp1_capture_rx_data_ready</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_capture_rx_data_ready</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_rx_data_ready_cnt_out">
-      <obj_property name="ElementShortName">qsfp1_capture_rx_data_ready_cnt_out[31:0]</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_capture_rx_data_ready_cnt_out[31:0]</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_fifo_aempty_512b_cnt_out">
-      <obj_property name="ElementShortName">qsfp1_capture_fifo_aempty_512b_cnt_out[31:0]</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_capture_fifo_aempty_512b_cnt_out[31:0]</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_iq_240b_to_512b_overflow_cnt_out">
-      <obj_property name="ElementShortName">qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0]</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0]</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="/tb_cap_plybk/tx_tdata_128b">
-      <obj_property name="ElementShortName">tx_tdata_128b[127:0]</obj_property>
-      <obj_property name="ObjectShortName">tx_tdata_128b[127:0]</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/tx_tvalid_128b">
-      <obj_property name="ElementShortName">tx_tvalid_128b</obj_property>
-      <obj_property name="ObjectShortName">tx_tvalid_128b</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/tx_tready_128b">
-      <obj_property name="ElementShortName">tx_tready_128b</obj_property>
-      <obj_property name="ObjectShortName">tx_tready_128b</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_512b">
-      <obj_property name="ElementShortName">qsfp1_tready_512b</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_tready_512b</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_512b_pipe">
-      <obj_property name="ElementShortName">qsfp1_tready_512b_pipe</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_tready_512b_pipe</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_128b">
-      <obj_property name="ElementShortName">qsfp1_tready_128b</obj_property>
-      <obj_property name="ObjectShortName">qsfp1_tready_128b</obj_property>
-   </wvobject>
-</wave_config>

sim/test_bench.vhd

@@ -1,188 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   16:53:22 03/24/2017
--- Design Name:   
--- Module Name:   
--- Project Name:  xem7350
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: dac_interface
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE IEEE.STD_LOGIC_arith.ALL;
-USE IEEE.STD_LOGIC_unsigned.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
-entity test_bench is
-end test_bench;
- 
-architecture behavior of test_bench is 
- 
-  constant C_M_AXI_DATA_WIDTH             : integer := 32;
-  constant C_M_AXI_ADDR_WIDTH             : integer := 32;
-
-   -- Clock period definitions
-  constant CLK_125_PERIOD           : time := 8 ns;    -- 125 MHz
-  constant CLK_250_PERIOD           : time := 4 ns;    -- 250 MHz        
-  constant S_AXI_ACLK_PERIOD        : time := 10 ns;   -- 100 MHz
-  constant M_AXI_ACLK_PERIOD        : time := 4 ns;    -- 250 MHz       2.58 ns;  -- 387 MHz    
-  constant QSFP4_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     
-  constant QSFP1_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     
-
-  signal clk_125                    : std_logic :=  '0';
-  signal clk_125_aresetn            : std_logic_vector(0 to 15) := (others => '0');
-  signal clk_125_reset              : std_logic;
-  
-  signal clk_250                    : std_logic :=  '0';
-  signal clk_250_aresetn            : std_logic_vector(0 to 15) := (others => '0');
-  signal clk_250_areset             : std_logic;
-
-  signal tx_device_clk_1            : std_logic :=  '0';
-  signal tx_device_clk_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
-  signal tx_device_clk_aresetn      : std_logic;
-
-  signal rx_device_clk_1            : std_logic :=  '0';
-  signal rx_device_clk_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
-  signal rx_device_clk_aresetn      : std_logic;
-  signal rx_device_clk_areset       : std_logic;
-
-  signal qsfp4_axis_aclk            : std_logic :=  '0';
-  signal qsfp4_axis_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
-  signal qsfp4_axis_aresetn      : std_logic;
-
-  signal qsfp1_axis_aclk            : std_logic :=  '0';
-  signal qsfp1_axis_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
-  signal qsfp1_axis_aresetn      : std_logic;
-
-  
---
-  signal tick_1ms                         : std_logic;
-
-  signal clk_125_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
-  signal clk_125_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
-  signal clk_125_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');
-
-  signal clk_250_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
-  signal clk_250_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
-  signal clk_250_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');
-
-  
-  
-begin
- 
-  clk_125  <= not clk_125 after CLK_125_PERIOD/2;
-  clk_250  <= not clk_250 after CLK_250_PERIOD/2; 
-  tx_device_clk_1  <= not tx_device_clk_1 after CLK_250_PERIOD/2; 
-  rx_device_clk_1  <= not rx_device_clk_1 after CLK_250_PERIOD/2; 
-
-  qsfp4_axis_aclk  <= not qsfp4_axis_aclk after QSFP4_AXIS_ACLK_PERIOD/2; 
-  qsfp1_axis_aclk  <= not qsfp1_axis_aclk after QSFP1_AXIS_ACLK_PERIOD/2; 
-
---
-  process(clk_125)
-  begin
-    if (rising_edge(clk_125)) then
-      clk_125_aresetn     <= clk_125_aresetn(1 to 15) & '1';
-    end if;
-  end process;
-
-  process(clk_125)
-  begin
-    if (rising_edge(clk_125)) then
-      clk_125_aresetn     <= clk_125_aresetn(1 to 15) & '1';
-    end if;
-  end process;
-  
-  clk_125_reset  <= not clk_125_aresetn(0);
---  
-  process(clk_250)
-  begin
-    if (rising_edge(clk_250)) then
-      clk_250_aresetn     <= clk_250_aresetn(1 to 15) & '1';
-    end if;
-  end process;
-  
-  clk_250_areset  <= not clk_250_aresetn(0);
---
-  process(tx_device_clk_1)
-  begin
-    if (rising_edge(tx_device_clk_1)) then
-      tx_device_clk_aresetn_r     <= tx_device_clk_aresetn_r(1 to 15) & '1';
-    end if;
-  end process;
-
-  tx_device_clk_aresetn  <= tx_device_clk_aresetn_r(0);
-
-
-------------------------------------------------
-  i_tick_gen : entity work.tick_gen
-    generic map (
-      CLOCK_SPEED_MHZ                       => 125
-      ) 
-    port map (
-      clk_in                                => clk_125,
-
-      tick_1us_out                          => open,
-      tick_1ms_out                          => tick_1ms,
-      tick_500ms_out                        => open,
-      tick_750ms_out                        => open,
-      tick_1s_out                           => open,
-
-      prog_us_tick_rate_in                  => x"0000_0000",
-      prog_us_tick_out                      => open,  
-
-      reset_in                              => clk_125_reset   
-      );
-
-
-  process(clk_125)
-  begin
-    if (rising_edge(clk_125)) then
-      clk_125_tick_1ms_r      <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
-      if (clk_125_tick_1ms_r(0 to 1) = "01") then 
-        clk_125_freq_r        <= clk_125_cnt_r;
-        clk_125_cnt_r         <= (others => '0');
-      else
-        clk_125_cnt_r         <= clk_125_cnt_r + 1;
-      end if;
-    end if;
-  end process;
-
-  process(clk_250)
-  begin
-    if (rising_edge(clk_250)) then
-      clk_250_tick_1ms_r      <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
-      if (clk_250_tick_1ms_r(0 to 1) = "01") then 
-        clk_250_freq_r        <= clk_250_cnt_r;
-        clk_250_cnt_r         <= (others => '0');
-      else
-        clk_250_cnt_r         <= clk_250_cnt_r + 1;
-      end if;
-    end if;
-  end process;
-
-
-  
-
-end;

source/axis_demux_128b.vhd

@@ -0,0 +1,46 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+Library xpm;
+use xpm.vcomponents.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity axis_demux_128b is
+  port ( 
+    aselect                     : in  std_logic;
+
+    s_axis_tdata                : in  std_logic_vector(127 downto 0);
+    s_axis_tvalid               : in  std_logic;
+    s_axis_tready               : out std_logic;
+
+    m0_axis_tdata               : out std_logic_vector(127 downto 0);
+    m0_axis_tvalid              : out std_logic;
+    m0_axis_tready              : in  std_logic;
+
+    m1_axis_tdata               : out std_logic_vector(127 downto 0);
+    m1_axis_tvalid              : out std_logic;
+    m1_axis_tready              : in  std_logic
+    );
+end entity axis_demux_128b;
+
+architecture imp of axis_demux_128b is
+
+begin
+     
+  m0_axis_tdata    <= s_axis_tdata;
+  m0_axis_tvalid   <= s_axis_tvalid  when aselect = '0' else '0';
+
+  m1_axis_tdata    <= s_axis_tdata; 
+  m1_axis_tvalid   <= s_axis_tvalid  when aselect = '1' else '0';
+    
+  s_axis_tready    <= m0_axis_tready when aselect = '0' else m1_axis_tready;
+
+end imp;
+

source/axis_mux_128b.vhd

@@ -14,9 +14,7 @@ use xpm.vcomponents.all;
 
 entity axis_mux_128b is
   port ( 
-    aclk                : in STD_LOGIC;
+    aselect             : in std_logic_vector(2 downto 0);
-    aresetn             : in std_logic;
-    aselect             : in std_logic_vector(1 downto 0);
 
     s0_axis_tdata       : in std_logic_vector(127 downto 0);
     s0_axis_tvalid      : in std_logic;
@@ -34,6 +32,10 @@ entity axis_mux_128b is
     s3_axis_tvalid      : in std_logic;
     s3_axis_tready      : out std_logic;
 
+    s4_axis_tdata       : in std_logic_vector(127 downto 0);
+    s4_axis_tvalid      : in std_logic;
+    s4_axis_tready      : out std_logic;
+
     m_axis_tdata        : out std_logic_vector(127 downto 0);
     m_axis_tvalid       : out std_logic;
     m_axis_tready       : in  std_logic
@@ -44,22 +46,23 @@ architecture imp of axis_mux_128b is
 
 begin
      
+  m_axis_tdata    <= s0_axis_tdata  when aselect = "000" else 
+                     s1_axis_tdata  when aselect = "001" else 
+                     s2_axis_tdata  when aselect = "010" else 
+                     s3_axis_tdata  when aselect = "011" else 
+                     s4_axis_tdata;
  
-  m_axis_tdata    <= s0_axis_tdata  when aselect = "00" else 
+  m_axis_tvalid   <= s0_axis_tvalid when aselect = "000" else 
-                     s1_axis_tdata  when aselect = "01" else 
+                     s1_axis_tvalid when aselect = "001" else
-                     s2_axis_tdata  when aselect = "10" else 
+                     s2_axis_tvalid when aselect = "010" else
-                     s3_axis_tdata; 
+                     s3_axis_tvalid when aselect = "011" else
- 
+                     s4_axis_tvalid;
-  m_axis_tvalid   <= s0_axis_tvalid when aselect = "00" else 
-                     s1_axis_tvalid when aselect = "01" else
-                     s2_axis_tvalid when aselect = "10" else
-                     s3_axis_tvalid;
-    
-  s0_axis_tready  <= m_axis_tready  when aselect = "00" else '0';
-  s1_axis_tready  <= m_axis_tready  when aselect = "01" else '0';
-  s2_axis_tready  <= m_axis_tready  when aselect = "10" else '0';
-  s3_axis_tready  <= m_axis_tready  when aselect = "11" else '0';
     
+  s0_axis_tready  <= m_axis_tready  when aselect = "000" else '0';
+  s1_axis_tready  <= m_axis_tready  when aselect = "001" else '0';
+  s2_axis_tready  <= m_axis_tready  when aselect = "010" else '0';
+  s3_axis_tready  <= m_axis_tready  when aselect = "011" else '0';
+  s4_axis_tready  <= m_axis_tready  when aselect = "100" else '0';
 
 end imp;
 

source/axis_mux_512b.vhd

@@ -0,0 +1,47 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+Library xpm;
+use xpm.vcomponents.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity axis_mux_512b is
+  port ( 
+    aselect             : in std_logic;
+
+    s0_axis_tdata       : in std_logic_vector(511 downto 0);
+    s0_axis_tvalid      : in std_logic;
+    s0_axis_tready      : out std_logic;
+
+    s1_axis_tdata       : in std_logic_vector(511 downto 0);
+    s1_axis_tvalid      : in std_logic;
+    s1_axis_tready      : out std_logic;
+
+    m_axis_tdata        : out std_logic_vector(511 downto 0);
+    m_axis_tvalid       : out std_logic;
+    m_axis_tready       : in  std_logic
+    );
+end entity axis_mux_512b;
+
+architecture imp of axis_mux_512b is
+
+begin
+     
+  m_axis_tdata    <= s0_axis_tdata  when aselect = '0' else 
+                     s1_axis_tdata; 
+ 
+  m_axis_tvalid   <= s0_axis_tvalid when aselect = '0' else 
+                     s1_axis_tvalid;
+    
+  s0_axis_tready  <= m_axis_tready  when aselect = '0' else '0';
+  s1_axis_tready  <= m_axis_tready  when aselect = '1' else '0';
+
+end imp;
+

source/axis_mux_s2_128b.vhd

@@ -14,8 +14,6 @@ use xpm.vcomponents.all;
 
 entity axis_mux_s2_128b is
   port ( 
-    aclk                : in STD_LOGIC;
-    aresetn             : in std_logic;
     aselect             : in std_logic;
 
     s0_axis_tdata       : in std_logic_vector(127 downto 0);

source/eth_flowctrl_rx.vhd

@@ -0,0 +1,79 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:    Jason M Blevins
+-- 
+-- Create Date: 01/05/2026 11:59:12 AM
+-- Design Name: 
+-- Module Name: eth_flowctrl_rx - behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eth_flowctrl_rx is
+  Port (
+    clk                 : in STD_LOGIC;
+    resetn              : in STD_LOGIC;
+    rx_pause            : in STD_LOGIC;
+    rx_pause_quanta8    : in STD_LOGIC_VECTOR(15 downto 0);
+    rx_pause_cnt        : out std_logic_vector(31 downto 0);
+    pause               : out STD_LOGIC
+    );
+end eth_flowctrl_rx;
+
+architecture behavioral of eth_flowctrl_rx is
+
+  signal pause_r          : std_logic := '0';
+  signal cnt_r            : unsigned(15 downto 0) := (others => '0');
+  signal rx_pause_cnt_r   : unsigned(31 downto 0) := (others => '0');
+
+begin
+
+  pause         <= pause_r;
+  rx_pause_cnt  <= std_logic_vector(rx_pause_cnt_r);
+
+  process(clk)
+  begin
+    if(rising_edge(clk))then 
+      if(resetn = '0')then
+        cnt_r           <= (others => '0');
+        pause_r         <= '0';
+        rx_pause_cnt_r  <= (others => '0');
+      else
+        if(rx_pause = '1')then
+          rx_pause_cnt_r  <= rx_pause_cnt_r +1;
+          cnt_r           <= unsigned(rx_pause_quanta8);
+          if(unsigned(rx_pause_quanta8) = 0)then
+            pause_r <= '0';
+          else
+            pause_r <= '1';
+          end if;
+        else
+          if(cnt_r > 0)then
+            cnt_r <= cnt_r -1;
+          end if;
+          if(cnt_r = 1)then
+            pause_r <= '0';
+          end if;
+        end if;         
+      end if;
+    end if;
+  end process;
+
+
+end behavioral;

source/eth_flowctrl_tx.vhd

@@ -0,0 +1,135 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:    Jason M Blevins
+-- 
+-- Create Date: 01/05/2026 11:59:12 AM
+-- Design Name: 
+-- Module Name: eth_flowctrl_tx - behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eth_flowctrl_tx is
+  Port (
+    clk                 : in STD_LOGIC;
+    resetn              : in STD_LOGIC;
+    prog_full_manual    : in STD_LOGIC;
+    data_cnt            : in STD_LOGIC_VECTOR(31 downto 0);
+    prog_full_on        : in STD_LOGIC_VECTOR(31 downto 0);
+    prog_full_off       : in STD_LOGIC_VECTOR(31 downto 0);
+    ctl_tx_resend_pause : out STD_LOGIC;
+    ctl_tx_pause_req    : out STD_LOGIC_VECTOR (8 downto 0);
+    tx_pause_cnt        : out std_logic_vector(31 downto 0)
+    );
+end eth_flowctrl_tx;
+
+architecture behavioral of eth_flowctrl_tx is
+
+  signal cnt              : unsigned(3 downto 0);
+  signal cnt_r            : unsigned(3 downto 0) := (others => '0');
+  signal tx_pause_cnt_i   : unsigned(31 downto 0);
+  signal tx_pause_cnt_r   : unsigned(31 downto 0) := (others => '0');
+  type state_type is (s0, s1, s2, s3);
+  signal state            : state_type;
+  signal state_r          : state_type := s0;
+  signal resend_pause     : std_logic;
+  signal pause_req        : std_logic_vector(8 downto 0);
+  signal resend_pause_r   : std_logic := '0';
+  signal pause_req_r      : std_logic_vector(8 downto 0) := (others => '0');
+  signal prog_full_r      : std_logic := '0';
+
+begin
+
+  ctl_tx_resend_pause <= resend_pause_r;
+  ctl_tx_pause_req    <= pause_req_r;
+  tx_pause_cnt        <= std_logic_vector(tx_pause_cnt_r);
+
+  process(clk)
+  begin
+    if(rising_edge(clk))then 
+      if(resetn = '0')then
+        resend_pause_r  <= '0';
+        pause_req_r     <= (others => '0');
+        state_r         <= s0;
+        cnt_r           <= (others => '0');
+        prog_full_r     <= '0';
+        tx_pause_cnt_r  <= (others => '0');
+      else
+        resend_pause_r  <= resend_pause;
+        pause_req_r     <= pause_req;
+        state_r         <= state;
+        cnt_r           <= cnt;
+        tx_pause_cnt_r  <= tx_pause_cnt_i;
+        if(unsigned(data_cnt) > unsigned(prog_full_on) or prog_full_manual = '1')then
+          prog_full_r <= '1';
+        elsif (unsigned(data_cnt) <= unsigned(prog_full_off) and prog_full_manual = '0')then
+          prog_full_r <= '0';
+        end if;         
+      end if;
+    end if;
+  end process;
+
+  process(state_r, cnt_r, prog_full_r, resend_pause_r, pause_req_r, tx_pause_cnt_r)
+  begin
+    -- defaults
+    state           <= state_r;
+    cnt             <= cnt_r;
+    resend_pause    <= resend_pause_r;
+    pause_req       <= pause_req_r;
+    tx_pause_cnt_i  <= tx_pause_cnt_r;
+  
+    case state_r is
+      when s0 =>
+        if(prog_full_r = '1')then
+          state           <= s1;
+          tx_pause_cnt_i  <= tx_pause_cnt_r +1;
+        end if;
+
+      when s1 =>
+        pause_req <= "100000000";
+        cnt <= cnt_r +1;
+        if(cnt_r = 15)then
+          state <= s2;
+        end if;
+
+      when s2 =>
+        if(prog_full_r = '0')then
+          state           <= s3;
+          tx_pause_cnt_i  <= tx_pause_cnt_r +1;
+        end if;
+
+      when s3 =>
+        pause_req     <= (others => '0');
+        cnt           <= cnt_r +1;
+        if(cnt_r = 0)then
+          resend_pause  <= '1';
+        else
+          resend_pause  <= '0';
+        end if;
+        if(cnt_r = 15)then
+          state <= s0;
+        end if;
+
+      when others =>
+    end case;
+
+  end process;  
+
+
+end behavioral;

source/eth_frame_packer.vhd

@@ -0,0 +1,258 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09/30/2025 05:40:20 PM
+-- Design Name: 
+-- Module Name: eth_frame_packer - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity eth_frame_packer is
+  port (
+    clk           : in  std_logic;
+    resetn        : in  std_logic;
+
+    pause         : in  std_logic := '0';
+    cfg_dst_mac   : in  std_logic_vector(47 downto 0);  -- DA
+    cfg_src_mac   : in  std_logic_vector(47 downto 0);  -- SA
+    cfg_eth_type  : in  std_logic_vector(15 downto 0);  -- EtherType/Length
+
+    -- AXIS payload in (512-bit, 64B beats; multiples of 64B, aligned)
+    s_axis_tdata  : in  std_logic_vector(511 downto 0);
+    s_axis_tvalid : in  std_logic;
+    s_axis_tready : out std_logic;
+    s_axis_tlast  : in  std_logic;
+
+    -- AXIS to CMAC TX client (512-bit)
+    m_axis_tdata  : out std_logic_vector(511 downto 0);
+    m_axis_tkeep  : out std_logic_vector(63 downto 0);
+    m_axis_tvalid : out std_logic;
+    m_axis_tready : in  std_logic;
+    m_axis_tlast  : out std_logic;
+    m_axis_tuser  : out std_logic;   -- error flag to CMAC
+    
+    tx_cnt        : out std_logic_vector(31 downto 0);
+    underrun_cnt  : out std_logic_vector(31 downto 0) := (others => '0')
+  );
+end entity;
+
+architecture rtl of eth_frame_packer is
+
+  ---------------------------------------------------------------------------
+  -- Functions (VHDL-93 safe)
+  ---------------------------------------------------------------------------
+  function mk_header(
+    da  : std_logic_vector(47 downto 0);
+    sa  : std_logic_vector(47 downto 0);
+    ety : std_logic_vector(15 downto 0)
+  ) return std_logic_vector is
+    variable h : std_logic_vector(111 downto 0);
+  begin
+    -- DA [0..5]
+    h(  7 downto   0) := da(47 downto 40);
+    h( 15 downto   8) := da(39 downto 32);
+    h( 23 downto  16) := da(31 downto 24);
+    h( 31 downto  24) := da(23 downto 16);
+    h( 39 downto  32) := da(15 downto  8);
+    h( 47 downto  40) := da( 7 downto  0);
+    -- SA [6..11]
+    h( 55 downto  48) := sa(47 downto 40);
+    h( 63 downto  56) := sa(39 downto 32);
+    h( 71 downto  64) := sa(31 downto 24);
+    h( 79 downto  72) := sa(23 downto 16);
+    h( 87 downto  80) := sa(15 downto  8);
+    h( 95 downto  88) := sa( 7 downto  0);
+    -- Type/Len [12..13]
+    h(103 downto  96) := ety(15 downto 8);
+    h(111 downto 104) := ety( 7 downto 0);
+    return h;
+  end function;
+
+  ---------------------------------------------------------------------------
+  -- 
+  ---------------------------------------------------------------------------
+  type state_type is (IDLE, RUN, FLUSH);
+  signal state          : state_type;
+  signal state_r        : state_type := IDLE;
+  signal carry_r        : std_logic_vector(111 downto 0) := (others => '0');
+  signal carry          : std_logic_vector(111 downto 0);
+  signal m_tdata_r      : std_logic_vector(511 downto 0) := (others => '0');
+  signal m_tdata        : std_logic_vector(511 downto 0);
+  signal m_tkeep_r      : std_logic_vector(63 downto 0) := (others => '1');
+  signal m_tkeep        : std_logic_vector(63 downto 0);
+  signal m_tlast_r      : std_logic := '0';
+  signal m_tlast        : std_logic;
+  signal m_tvalid_r     : std_logic := '0';
+  signal m_tvalid       : std_logic;
+  signal m_tuser_r      : std_logic := '0';
+  signal m_tuser        : std_logic;
+  signal header         : std_logic_vector(111 downto 0);
+  signal underrun_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
+  signal tx_cnt_r       : std_logic_vector(31 downto 0) := (others => '0');
+
+begin
+
+  header         <= mk_header(cfg_dst_mac, cfg_src_mac, cfg_eth_type);
+
+  ---------------------------------------------------------------------------
+  -- Drive Outputs
+  ---------------------------------------------------------------------------
+  m_axis_tuser   <= m_tuser_r;
+  m_axis_tdata   <= m_tdata_r;
+  m_axis_tkeep   <= m_tkeep_r;
+  m_axis_tlast   <= m_tlast_r;
+  m_axis_tvalid  <= m_tvalid_r;
+  underrun_cnt   <= underrun_cnt_r;
+  tx_cnt         <= tx_cnt_r;
+
+  ---------------------------------------------------------------------------
+  -- Combinational next-state / next-data 
+  ---------------------------------------------------------------------------
+  process(state_r, carry_r, s_axis_tlast, s_axis_tvalid, m_axis_tready, m_tvalid_r,
+          m_tdata_r, m_tkeep_r, m_tlast_r, m_tuser_r, header, s_axis_tdata, pause)
+  begin
+    -- Defaults
+    state         <=  state_r;
+    carry         <=  carry_r;
+    m_tdata       <=  m_tdata_r;
+    m_tkeep       <=  m_tkeep_r;
+    m_tlast       <=  m_tlast_r;
+    m_tuser       <=  m_tuser_r;
+    m_tvalid      <=  m_tvalid_r;
+    s_axis_tready <= '0';
+
+    case state_r is
+      -----------------------------------------------------------------------
+      when IDLE =>
+      
+        --s_axis_tready <= m_axis_tready or not(m_tvalid_r);
+       
+        --m_tvalid <= (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0')) or (not(m_axis_tready) and m_tvalid_r);
+        if(m_axis_tready = '1')then
+          m_tvalid <= '0';
+        end if;
+
+        if (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0') and pause = '0') then
+        
+          s_axis_tready <= '1';
+        
+          -- Emit first beat = [14B header] ++ [first 50B payload]
+          m_tdata   <= s_axis_tdata(399 downto 0) & header;
+          m_tkeep   <= (others => '1');
+          m_tvalid  <= '1';
+          m_tuser   <= '0';
+          m_tlast   <= '0';
+
+          -- Next carry = bytes 50..63
+          carry <= s_axis_tdata(511 downto 400);
+
+          if s_axis_tlast = '1' then
+            state <= FLUSH;
+          else
+            state <= RUN;
+          end if;
+          
+        end if;
+
+      -----------------------------------------------------------------------
+      when RUN =>
+      
+        s_axis_tready <= m_axis_tready;
+      
+        if(s_axis_tvalid = '0')then
+          m_tuser <= '1'; -- s_axis_tvalid must be '1' or else this is an error condition, tx data underrun.
+        end if;
+      
+        if (m_axis_tready = '1') then 
+        
+          -- Steady-state emit = [prev carry 14B] ++ [new payload 0..49]
+          m_tdata   <= s_axis_tdata(399 downto 0) & carry_r;
+          --m_tkeep   <= (others => '1');
+          --m_tvalid  <= '1';
+          --m_tlast   <= '0';
+
+          -- Next carry = bytes 50..63
+          carry <= s_axis_tdata(511 downto 400);
+
+          if s_axis_tlast = '1' then
+            state <= FLUSH;
+          else
+            state <= RUN;
+          end if;
+        end if;
+
+      -----------------------------------------------------------------------
+      when FLUSH =>
+      
+        --s_axis_tready <= '0';
+      
+        -- if(s_axis_tvalid = '0')then
+          -- m_tuser <= '1';
+        -- end if;
+      
+        if (m_axis_tready = '1') then
+        
+          -- Emit the final 14B tail
+          m_tdata   <= std_logic_vector(to_unsigned(0, 400)) & carry_r;
+          m_tkeep   <= x"0000000000003FFF";
+          m_tlast   <= '1';
+          --m_tvalid  <= '1';
+
+          state <= IDLE;
+        end if;
+        
+      --when others =>
+
+    end case;
+  end process;
+
+  ---------------------------------------------------------------------------
+  -- Registers
+  ---------------------------------------------------------------------------
+  seq_proc : process(clk)
+  begin
+    if rising_edge(clk) then
+      if resetn = '0' then
+        state_r         <= IDLE;
+        m_tvalid_r      <= '0';
+        underrun_cnt_r  <= (others => '0');
+        tx_cnt_r        <= (others => '0');
+      else
+        state_r         <= state;
+        m_tvalid_r      <= m_tvalid;
+        
+        if(m_tlast_r = '1' and m_tvalid_r = '1' and m_tuser_r = '1' and m_axis_tready = '1')then
+          underrun_cnt_r  <= std_logic_vector(unsigned(underrun_cnt_r)  +1);
+        end if;
+
+        if(m_tlast_r = '1' and m_tvalid_r = '1' and m_axis_tready = '1')then
+          tx_cnt_r  <= std_logic_vector(unsigned(tx_cnt_r)  +1);
+        end if;
+        
+      end if;
+      carry_r   <= carry;
+      m_tdata_r <= m_tdata;
+      m_tkeep_r <= m_tkeep;
+      m_tlast_r <= m_tlast;
+      m_tuser_r <= m_tuser;             
+    end if;
+  end process;
+
+end architecture;
+

source/eth_frame_unpacker.vhd

@@ -0,0 +1,145 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09/30/2025 05:47:45 PM
+-- Design Name: 
+-- Module Name: eth_frame_unpacker - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity eth_frame_unpacker is
+  port (
+    clk           : in  std_logic;
+    resetn        : in  std_logic;  -- active-low synchronous reset
+
+    s_axis_tdata  : in  std_logic_vector(511 downto 0);
+    s_axis_tvalid : in  std_logic;
+    s_axis_tlast  : in  std_logic;
+    s_axis_tkeep  : in  std_logic_vector(63 downto 0);
+    s_axis_tuser  : in  std_logic; -- frame error indicator (qualified by s_axis_tvalid and s_axis_tlast)
+
+    m_axis_tdata  : out std_logic_vector(511 downto 0);
+    m_axis_tvalid : out std_logic;
+    m_axis_tlast  : out std_logic;
+    m_axis_tuser  : out std_logic;  -- frame error indicator (qualified by m_axis_tvalid and m_axis_tlast)
+
+    rx_frame_err_cnt : out std_logic_vector(31 downto 0);
+    rx_frame_cnt     : out std_logic_vector(31 downto 0)
+  );
+end entity;
+
+architecture rtl of eth_frame_unpacker is
+
+  type state_type is (IDLE, RUN);
+
+  signal state_r          : state_type := IDLE;
+  signal state            : state_type;
+  signal carry            : std_logic_vector(399 downto 0);
+  signal carry_r          : std_logic_vector(399 downto 0) := (others => '0');
+  signal frame_err_cnt_i  : std_logic_vector(31 downto 0);
+  signal frame_err_cnt_r  : std_logic_vector(31 downto 0) := (others => '0');
+  signal frame_cnt_i      : std_logic_vector(31 downto 0);
+  signal frame_cnt_r      : std_logic_vector(31 downto 0) := (others => '0');
+  signal m_tvalid         : std_logic;
+  signal m_tvalid_r       : std_logic := '0';
+  signal m_tdata          : std_logic_vector(511 downto 0);
+  signal m_tdata_r        : std_logic_vector(511 downto 0) := (others => '0');
+  signal m_tuser          : std_logic;
+  signal m_tuser_r        : std_logic := '0';
+  signal m_tlast          : std_logic;
+  signal m_tlast_r        : std_logic := '0';
+
+begin
+
+  -- Drive outputs
+  m_axis_tuser      <= m_tuser_r;
+  m_axis_tdata      <= m_tdata_r;
+  m_axis_tlast      <= m_tlast_r;
+  m_axis_tvalid     <= m_tvalid_r;
+  rx_frame_err_cnt  <= frame_err_cnt_r;
+  rx_frame_cnt      <= frame_cnt_r;
+
+  -----------------------------------------------------------------------------
+  -- Combinational next-state / next-data
+  -----------------------------------------------------------------------------
+  process(state_r, carry_r, m_tdata_r, m_tuser_r, m_tlast_r, frame_err_cnt_r,
+          s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser, frame_cnt_r)
+  begin
+    -- Defaults
+    state           <= state_r;
+    carry           <= carry_r;
+    frame_err_cnt_i <= frame_err_cnt_r;
+    frame_cnt_i     <= frame_cnt_r; 
+    m_tvalid        <= '0';
+    m_tdata         <= m_tdata_r;
+    m_tuser         <= m_tuser_r; 
+    m_tlast         <= m_tlast_r;
+
+    case state_r is
+      -------------------------------------------------------------------------
+      when IDLE =>     
+        if s_axis_tvalid = '1' then
+          -- cache high 50B; no output yet (need second beat to form first 64B payload)
+          carry(399 downto 0) <= s_axis_tdata(511 downto 112);
+          state               <= RUN;
+        end if;
+      -------------------------------------------------------------------------
+      when RUN =>
+        if s_axis_tvalid = '1' then
+          carry(399 downto 0) <= s_axis_tdata(511 downto 112);
+          m_tdata             <= s_axis_tdata(111 downto 0) & carry_r;
+          m_tvalid            <= '1';
+          m_tuser             <= s_axis_tuser;
+          m_tlast             <= s_axis_tlast;          
+          if(s_axis_tlast = '1')then
+            state <= IDLE;
+            frame_cnt_i <= std_logic_vector(unsigned(frame_cnt_r) +1);
+          end if;         
+          if(s_axis_tlast = '1' and s_axis_tuser = '1')then
+            frame_err_cnt_i <= std_logic_vector(unsigned(frame_err_cnt_r) +1);
+          end if;
+        end if;
+      -------------------------------------------------------------------------
+    end case;
+  end process;
+
+  -----------------------------------------------------------------------------
+  -- Regs
+  -----------------------------------------------------------------------------
+  seq_proc : process(clk)
+  begin
+    if rising_edge(clk) then   
+      if resetn = '0' then
+        state_r         <= IDLE;       
+        frame_err_cnt_r <= (others => '0');
+        frame_cnt_r     <= (others => '0');
+        m_tvalid_r      <= '0';       
+      else
+        state_r         <= state;
+        frame_err_cnt_r <= frame_err_cnt_i;
+        frame_cnt_r     <= frame_cnt_i;
+        m_tvalid_r      <= m_tvalid;
+      end if;      
+      carry_r           <= carry;
+      m_tdata_r         <= m_tdata;        
+      m_tuser_r         <= m_tuser;        
+      m_tlast_r         <= m_tlast;     
+    end if;
+  end process;
+end architecture;
+

source/system_top.v

@@ -37,8 +37,8 @@
 
 
 module system_top  #(
-  parameter FPGA_REVISION_DATE = 32'h05282026, 
+  parameter FPGA_REVISION_DATE = 32'h07162026, 
-  parameter MINOR_REV = 8'h04,
+  parameter MINOR_REV = 8'h01,
   parameter TX_JESD_L = 8,
   parameter TX_NUM_LINKS = 1,
   parameter RX_JESD_L = 8,
@@ -69,6 +69,35 @@ module system_top  #(
   output                              QSFP1_TX3_P,
   output                              QSFP1_TX4_N,
   output                              QSFP1_TX4_P,
+//
+  input                               QSFP2_INTL_LS,
+  input                               QSFP2_MODPRSL_LS,
+  output                              QSFP2_RESETL_LS,
+  input                               QSFP2_SI570_CLOCK_N,//CLK3_N  
+  input                               QSFP2_SI570_CLOCK_P,
+//
+  input                               QSFP3_INTL_LS,
+  input                               QSFP3_MODPRSL_LS,
+  output                              QSFP3_RESETL_LS,
+  input                               QSFP3_RX1_N,
+  input                               QSFP3_RX1_P,
+  input                               QSFP3_RX2_N,
+  input                               QSFP3_RX2_P,
+  input                               QSFP3_RX3_N,
+  input                               QSFP3_RX3_P,
+  input                               QSFP3_RX4_N,
+  input                               QSFP3_RX4_P,
+  input                               QSFP3_SI570_CLOCK_N,//CLK1_N  
+  input                               QSFP3_SI570_CLOCK_P,
+  output                              QSFP3_TX1_N,
+  output                              QSFP3_TX1_P,
+  output                              QSFP3_TX2_N,
+  output                              QSFP3_TX2_P,
+  output                              QSFP3_TX3_N,
+  output                              QSFP3_TX3_P,
+  output                              QSFP3_TX4_N,
+  output                              QSFP3_TX4_P,
+//
   input                               QSFP4_INTL_LS,
   input                               QSFP4_MODPRSL_LS,
   output                              QSFP4_RESETL_LS,
@@ -90,14 +119,7 @@ module system_top  #(
   output                              QSFP4_TX3_P,
   output                              QSFP4_TX4_N,
   output                              QSFP4_TX4_P,
-
+//  
-  input                               QSFP2_SI570_CLOCK_N,//CLK3_N  
-  input                               QSFP2_SI570_CLOCK_P,
-  
-  input                               QSFP3_SI570_CLOCK_N,//CLK1_N  
-  input                               QSFP3_SI570_CLOCK_P,
-
-
   inout                               pll_scl,
   inout                               pll_sda,
 
@@ -220,13 +242,13 @@ module system_top  #(
   wire            qsfp1_capture_tvalid_240b;
 
   wire  [31:0]    qsfp1_capture_tvalid_240b_cnt;
-  wire  [31:0]    qsfp1_tx_fifo_128_aempty_cnt;
+  wire  [31:0]    qsfp1_fifo_128_aempty_cnt;
 
-  wire  [127:0]   tx_tdata_128b;                
+  wire  [127:0]   qsfp1_tdata_128b;                
-  wire            tx_tvalid_128b;               
+  wire            qsfp1_tvalid_128b;               
-  wire            tx_tready_128b;                
+  wire            qsfp1_tready_128b;                
 
-  wire  [31:0]    qsfp1_tx_fifo_tvalid_128b_cnt;
+  wire  [31:0]    qsfp1_fifo_tvalid_128b_cnt;
 
   wire            qsfp1_capture_rx_data_ready; 
   wire  [31:0]    qsfp1_capture_rx_data_ready_cnt;
@@ -253,38 +275,7 @@ module system_top  #(
   wire  [31:0]    slv_reg9;
   wire  [31:0]    slv_reg10;
 
-  wire  [31:0]    slv_reg21;
+  wire  [2:0]     dac_src_data_sel;
-  wire  [31:0]    slv_reg22;
-  wire  [31:0]    slv_reg23;
-  wire  [31:0]    slv_reg24;
-  wire  [31:0]    slv_reg25;
-  wire  [31:0]    slv_reg26;
-  wire  [31:0]    slv_reg27;
-  wire  [31:0]    slv_reg28;
-  wire  [31:0]    slv_reg29;
-  wire  [31:0]    slv_reg30;
-
-  wire  [31:0]    slv_reg31;
-  wire  [31:0]    slv_reg32;
-  wire  [31:0]    slv_reg33;
-  wire  [31:0]    slv_reg34;
-  wire  [31:0]    slv_reg35;
-  wire  [31:0]    slv_reg36;
-  wire  [31:0]    slv_reg37;
-  wire  [31:0]    slv_reg38;
-  wire  [31:0]    slv_reg39;
-  wire  [31:0]    slv_reg40;
-
-  wire  [31:0]    slv_reg41;
-  wire  [31:0]    slv_reg42;
-  wire  [31:0]    slv_reg43;
-  wire  [31:0]    slv_reg44;
-  wire  [31:0]    slv_reg45;
-  wire  [31:0]    slv_reg46;
-  wire  [31:0]    slv_reg47;
-  wire  [31:0]    slv_reg48;
-
-  wire  [1:0]     dac_src_data_sel;
   
   wire            chan1to4_mode_sel;
   wire            qsfp4_playback_path_data_enable_n;
@@ -292,9 +283,6 @@ module system_top  #(
   wire            qsfp2_clk;
   wire            qsfp2_clk_bufg;
   
-  wire            qsfp3_clk;
-  wire            qsfp3_clk_bufg;
-  
   wire            clk_100;
   wire            clk_100_aresetn;
   wire   [31:0]   M11_AXI_0_araddr;
@@ -337,6 +325,26 @@ module system_top  #(
   wire   [3:0]    M12_AXI_0_wstrb;
   wire            M12_AXI_0_wvalid;
 
+  wire   [31:0]   M13_AXI_0_araddr;
+  wire   [2:0]    M13_AXI_0_arprot;
+  wire            M13_AXI_0_arready;
+  wire            M13_AXI_0_arvalid;
+  wire   [31:0]   M13_AXI_0_awaddr;
+  wire   [2:0]    M13_AXI_0_awprot;
+  wire            M13_AXI_0_awready;
+  wire            M13_AXI_0_awvalid;
+  wire            M13_AXI_0_bready;
+  wire   [1:0]    M13_AXI_0_bresp;
+  wire            M13_AXI_0_bvalid;
+  wire   [31:0]   M13_AXI_0_rdata;
+  wire            M13_AXI_0_rready;
+  wire   [1:0]    M13_AXI_0_rresp;
+  wire            M13_AXI_0_rvalid;
+  wire   [31:0]   M13_AXI_0_wdata;
+  wire            M13_AXI_0_wready;
+  wire   [3:0]    M13_AXI_0_wstrb;
+  wire            M13_AXI_0_wvalid;
+
   wire            sda_i;
   wire            sda_o;
   wire            sda_t;
@@ -357,6 +365,10 @@ module system_top  #(
   wire            m1_dds_pulse_tvalid_128b;               
   wire            m1_dds_pulse_tready_128b;                
   
+  wire  [127:0]   m1_dds_pulse_fifo_tdata_128b;                
+  wire            m1_dds_pulse_fifo_tvalid_128b;               
+  wire            m1_dds_pulse_fifo_tready_128b;                
+
   wire  [127:0]   fiber_tx_tdata_128b;
   wire            fiber_tx_tvalid_128b;
   wire            fiber_tx_tready_128b;
@@ -369,6 +381,47 @@ module system_top  #(
   wire            qsfp1_capture_en_n;
   wire            qsfp1_capture_rst;
   
+
+  wire [3:0]      cmac_gt_0_grx_n;
+  wire [3:0]      cmac_gt_0_grx_p;
+  wire [3:0]      cmac_gt_0_gtx_n;
+  wire [3:0]      cmac_gt_0_gtx_p;
+  wire            cmac_refclk_0_clk_n;
+  wire            cmac_refclk_0_clk_p;
+
+  wire            cmac_tx_intfc_en; 
+  wire            cmac_rx_intfc_en; 
+
+////
+  wire [511:0]    cmac_0_tx_tdata_512b;
+  wire            cmac_0_tx_tvalid_512b; 
+  wire            cmac_0_tx_tvalid_512b_en; 
+  wire            cmac_0_tx_tready_512b;    
+  wire            cmac_0_tx_tready_512b_en;    
+  reg  [31:0]     cmac_0_tx_tvalid_512b_cnt_r = 32'h0;
+
+  wire  [511:0]   cmac_0_rx_tdata_512b;                
+  wire            cmac_0_rx_tvalid_512b;               
+  wire            cmac_0_rx_tvalid_512b_en;               
+  wire            cmac_0_rx_tready_512b;                
+  wire            cmac_0_rx_tready_512b_en;                
+  reg   [31:0]    cmac_0_rx_tvalid_512b_cnt_r = 32'h0; 
+  
+  wire  [127:0]   cmac_0_rx_tdata_128b;                
+  wire            cmac_0_rx_tvalid_128b;               
+  wire            cmac_0_rx_tready_128b;
+  
+  wire  [127:0]   dds2cmac_fifo_tdata_128b;  
+  wire            dds2cmac_fifo_tvalid_128b; 
+  wire            dds2cmac_fifo_tready_128b;  
+  
+  wire            dds_out_dest_sel;
+  wire            cmac_tx_src_data_sel;
+
+  wire  [511:0]   adc_tdata_512b; 
+  wire            adc_tvalid_512b;
+  wire            adc_tready_512b; 
+
 ////////////////////////////////////////////////////////////////
 
   // instantiations
@@ -473,27 +526,6 @@ module system_top  #(
     .O                                    (qsfp2_clk_bufg)
     );
   
-//////////
-  IBUFDS_GTE4 i_ibufds_qsfp3 (
-    .I                                    (QSFP3_SI570_CLOCK_P),
-    .IB                                   (QSFP3_SI570_CLOCK_N),
-    .CEB                                  (1'b0),
-    .O                                    (),
-    .ODIV2                                (qsfp3_clk)
-    );
-
-  BUFG_GT i_bufgt_qsfp3 (
-    .I                                    (qsfp3_clk),
-    .CE                                   (1'b1),
-    .CEMASK                               (1'b0),
-    .CLR                                  (1'b0),
-    .CLRMASK                              (1'b0),
-    .DIV                                  (3'b000),
-    .O                                    (qsfp3_clk_bufg)
-    );
-
-
-  
 //  assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
 
   // spi
@@ -736,6 +768,26 @@ module system_top  #(
     .M12_AXI_0_wstrb                      (M12_AXI_0_wstrb),
     .M12_AXI_0_wvalid                     (M12_AXI_0_wvalid),
     
+    .M13_AXI_0_araddr                     (M13_AXI_0_araddr),
+    .M13_AXI_0_arprot                     (M13_AXI_0_arprot),
+    .M13_AXI_0_arready                    (M13_AXI_0_arready),
+    .M13_AXI_0_arvalid                    (M13_AXI_0_arvalid),
+    .M13_AXI_0_awaddr                     (M13_AXI_0_awaddr),
+    .M13_AXI_0_awprot                     (M13_AXI_0_awprot),
+    .M13_AXI_0_awready                    (M13_AXI_0_awready),
+    .M13_AXI_0_awvalid                    (M13_AXI_0_awvalid),
+    .M13_AXI_0_bready                     (M13_AXI_0_bready),
+    .M13_AXI_0_bresp                      (M13_AXI_0_bresp),
+    .M13_AXI_0_bvalid                     (M13_AXI_0_bvalid),
+    .M13_AXI_0_rdata                      (M13_AXI_0_rdata),
+    .M13_AXI_0_rready                     (M13_AXI_0_rready),
+    .M13_AXI_0_rresp                      (M13_AXI_0_rresp),
+    .M13_AXI_0_rvalid                     (M13_AXI_0_rvalid),
+    .M13_AXI_0_wdata                      (M13_AXI_0_wdata),
+    .M13_AXI_0_wready                     (M13_AXI_0_wready),
+    .M13_AXI_0_wstrb                      (M13_AXI_0_wstrb),
+    .M13_AXI_0_wvalid                     (M13_AXI_0_wvalid),
+    
     .Res_0                               (),          //mxfe_rx_data_offload_s_axis_tready from Rx DMA engine
 
     .pl_clk3_0                            (pl_clk3_0),
@@ -781,7 +833,6 @@ module system_top  #(
 //    .sysref_in                                (sysref),
     .ref_clk_div2_in                          (ref_clk_div2_bufg),
     .qsfp2_clk_in                             (qsfp2_clk_bufg),
-    .qsfp3_clk_in                             (qsfp3_clk_bufg),
     .pl_clk3_0                                (pl_clk3_0),
 
     .QSFP1_INTL_LS                            (QSFP1_INTL_LS),
@@ -805,6 +856,15 @@ module system_top  #(
     .QSFP1_TX3_P                              (QSFP1_TX3_P),
     .QSFP1_TX4_N                              (QSFP1_TX4_N),
     .QSFP1_TX4_P                              (QSFP1_TX4_P),
+///////////
+    .QSFP2_RESETL_LS                          (QSFP2_RESETL_LS),
+    .QSFP2_MODPRSL_LS                         (QSFP2_MODPRSL_LS),
+    .QSFP2_INTL_LS                            (QSFP2_INTL_LS),
+///////////                                                  
+    .QSFP3_RESETL_LS                          (QSFP3_RESETL_LS),
+    .QSFP3_MODPRSL_LS                         (QSFP3_MODPRSL_LS),
+    .QSFP3_INTL_LS                            (QSFP3_INTL_LS),
+///////////
     .QSFP4_INTL_LS                            (QSFP4_INTL_LS),
     .QSFP4_MODPRSL_LS                         (QSFP4_MODPRSL_LS),
     .QSFP4_RESETL_LS                          (QSFP4_RESETL_LS),
@@ -842,9 +902,9 @@ module system_top  #(
     .qsfp1_capture_tvalid_240b_cnt_in         (qsfp1_capture_tvalid_240b_cnt),
     .qsfp1_capture_overflow_240b_cnt_in       (qsfp1_capture_overflow_240b_cnt),
     .qsfp1_capture_tvalid_512b_cnt_in         (qsfp1_capture_tvalid_512b_cnt),
-    .qsfp1_tx_fifo_128_aempty_cnt_in          (qsfp1_tx_fifo_128_aempty_cnt),
+    .qsfp1_tx_fifo_128_aempty_cnt_in          (qsfp1_fifo_128_aempty_cnt),
     .qsfp1_capture_rx_data_ready_cnt_in       (qsfp1_capture_rx_data_ready_cnt),
-    .qsfp1_tx_fifo_tvalid_128b_cnt_in                    (qsfp1_tx_fifo_tvalid_128b_cnt),
+    .qsfp1_tx_fifo_tvalid_128b_cnt_in         (qsfp1_fifo_tvalid_128b_cnt),
     .mem_xfer_tx_upload_tvalid_128b_cnt_in    (mem_xfer_tx_upload_tvalid_128b_cnt_r), 
     .dac_tx_tvalid_128b_cnt_in                (dac_tx_tvalid_128b_cnt_r),
 
@@ -854,43 +914,16 @@ module system_top  #(
     .qsfp4_playback_tvalid_240b_cnt_in        (qsfp4_playback_tvalid_240b_cnt),
     
     .fiber_tx_tvalid_128b_cnt_in              (fiber_tx_tvalid_128b_cnt_r),                    
+    .cmac_0_tx_tvalid_512b_cnt_in             (cmac_0_tx_tvalid_512b_cnt_r),                                                                                        
+    .cmac_0_rx_tvalid_512b_cnt_in             (cmac_0_rx_tvalid_512b_cnt_r),
+        
+        
 
     .cnt_reset_out                            (cnt_reset),
 
     .slv_reg9_out                             (slv_reg9),
     .slv_reg10_out                            (slv_reg10),
 
-    .slv_reg21_out                            (slv_reg21),
-    .slv_reg22_out                            (slv_reg22),
-    .slv_reg23_out                            (slv_reg23),
-    .slv_reg24_out                            (slv_reg24),
-    .slv_reg25_out                            (slv_reg25),
-    .slv_reg26_out                            (slv_reg26),
-    .slv_reg27_out                            (slv_reg27),
-    .slv_reg28_out                            (slv_reg28),
-    .slv_reg29_out                            (slv_reg29),
-    .slv_reg30_out                            (slv_reg30),
-
-    .slv_reg31_out                            (slv_reg31),
-    .slv_reg32_out                            (slv_reg32),
-    .slv_reg33_out                            (slv_reg33),
-    .slv_reg34_out                            (slv_reg34),
-    .slv_reg35_out                            (slv_reg35),
-    .slv_reg36_out                            (slv_reg36),
-    .slv_reg37_out                            (slv_reg37),
-    .slv_reg38_out                            (slv_reg38),
-    .slv_reg39_out                            (slv_reg39),
-    .slv_reg40_out                            (slv_reg40),
-
-    .slv_reg41_out                            (slv_reg41),
-    .slv_reg42_out                            (slv_reg42),
-    .slv_reg43_out                            (slv_reg43),
-    .slv_reg44_out                            (slv_reg44),
-    .slv_reg45_out                            (slv_reg45),
-    .slv_reg46_out                            (slv_reg46),
-    .slv_reg47_out                            (slv_reg47),
-    .slv_reg48_out                            (slv_reg48),
-
     .sys_cpu_clk_in                           (clk_100),
     .s00_axi_aresetn                          (clk_100_aresetn),
     .s00_axi_awaddr                           (M11_AXI_0_awaddr[7:0]),
@@ -918,12 +951,19 @@ module system_top  #(
 //assign                                    = slv_reg10[3:1];
   assign  qsfp1_capture_rst                 = slv_reg10[4];            
 //assign                                    = slv_reg10[7:5];
-  assign  dac_src_data_sel                  = slv_reg10[9:8];   
+  assign  dac_src_data_sel                  = slv_reg10[10:8];   
-//assign                                    = slv_reg10[11:10];         
+//assign                                    = slv_reg10[11];         
   assign  chan1to4_mode_sel                 = slv_reg10[12];            
 //assign                                    = slv_reg10[14:13]; 
   assign  qsfp1_capture_en_n                = slv_reg10[15];
-//assign                                    = slv_reg10[30:16];
+//assign                                    = slv_reg10[18:16];
+  assign  cmac_tx_src_data_sel              = slv_reg10[19];
+//assign                                    = slv_reg10[23:20];
+  assign  dds_out_dest_sel                  = slv_reg10[24];
+//assign                                    = slv_reg10[27:25];
+  assign  cmac_tx_intfc_en                  = slv_reg10[28];
+  assign  cmac_rx_intfc_en                  = slv_reg10[29];
+//assign                                    = slv_reg10[30];
   assign  qsfp4_playback_path_data_enable_n = slv_reg10[31];
 
 ///////////////////////////////
@@ -942,11 +982,11 @@ module system_top  #(
 
     .tx_device_clk_in                               (tx_device_clk_1),
     .tx_device_clk_aresetn_in                       (tx_device_clk_aresetn),
-    .tx_fifo_tdata_128b_out                         (tx_tdata_128b),     // out         
+    .tx_fifo_tdata_128b_out                         (qsfp1_tdata_128b),     // out         
-    .tx_fifo_tvalid_128b_out                        (tx_tvalid_128b),    // out         
+    .tx_fifo_tvalid_128b_out                        (qsfp1_tvalid_128b),    // out         
-    .tx_fifo_tready_128b_in                         (tx_tready_128b),        // in  
+    .tx_fifo_tready_128b_in                         (qsfp1_tready_128b),        // in  
-    .qsfp1_tx_fifo_tvalid_128b_cnt_out              (qsfp1_tx_fifo_tvalid_128b_cnt),                   
+    .qsfp1_tx_fifo_tvalid_128b_cnt_out              (qsfp1_fifo_tvalid_128b_cnt),                   
-    .qsfp1_tx_fifo_128_aempty_cnt_out               (qsfp1_tx_fifo_128_aempty_cnt),                 
+    .qsfp1_tx_fifo_128_aempty_cnt_out               (qsfp1_fifo_128_aempty_cnt),                 
 
     .qsfp1_capture_en_n_in                          (qsfp1_capture_en_n),
     .qsfp1_capture_rst_in                           (qsfp1_capture_rst),
@@ -957,17 +997,15 @@ module system_top  #(
 ////   to DAC - data source from DMA Tx axis data, QSFP1 and ADC_INTFC
 /////////////////////////////////////////////    
   axis_mux_128b i_dac_axis_mux_128b (
-      .aclk                         (tx_device_clk_1),                  // input 
-      .aresetn                      (tx_device_clk_aresetn),            // input 
       .aselect                      (dac_src_data_sel),                 // input 
 
       .s0_axis_tdata                (mem_xfer_tx_upload_tdata_128b),    // input 
       .s0_axis_tvalid               (mem_xfer_tx_upload_tvalid_128b),   // input 
       .s0_axis_tready               (mem_xfer_tx_upload_tready_128b),   // output
 
-      .s1_axis_tdata                (tx_tdata_128b),                    // input 
+      .s1_axis_tdata                (qsfp1_tdata_128b),                    // input 
-      .s1_axis_tvalid               (tx_tvalid_128b),                   // input 
+      .s1_axis_tvalid               (qsfp1_tvalid_128b),                   // input 
-      .s1_axis_tready               (tx_tready_128b),                   // output
+      .s1_axis_tready               (qsfp1_tready_128b),                   // output
 
       .s2_axis_tdata                (adc_loopback_tdata_128b_mux),      // input 
       .s2_axis_tvalid               (adc_loopback_tvalid_128b),         // input 
@@ -977,6 +1015,10 @@ module system_top  #(
       .s3_axis_tvalid               (m0_dds_pulse_tvalid_128b),         // input 
       .s3_axis_tready               (m0_dds_pulse_tready_128b),         // output
 
+      .s4_axis_tdata                (cmac_0_rx_tdata_128b),          // input 
+      .s4_axis_tvalid               (cmac_0_rx_tvalid_128b),         // input 
+      .s4_axis_tready               (cmac_0_rx_tready_128b),          // output
+
       .m_axis_tdata                 (dac_tx_tdata_128b),                // output
       .m_axis_tvalid                (dac_tx_tvalid_128b),               // output
       .m_axis_tready                (dac_tx_tready_128b)                // input 
@@ -1004,14 +1046,28 @@ module system_top  #(
     .s_axis_tready                (m1_dds_pulse_tready_128b),        // out
 
     .m_axis_aclk                  (rx_device_clk_1),              // in
-    .m_axis_tdata                 (dds2fiber_fifo_tdata_128b),    // out                       
+    .m_axis_tdata                 (m1_dds_pulse_fifo_tdata_128b),    // out                       
-    .m_axis_tvalid                (dds2fiber_fifo_tvalid_128b),   // out                       
+    .m_axis_tvalid                (m1_dds_pulse_fifo_tvalid_128b),   // out                       
-    .m_axis_tready                (dds2fiber_fifo_tready_128b)    // in                      
+    .m_axis_tready                (m1_dds_pulse_fifo_tready_128b)    // in                      
+    );
+            
+  axis_demux_128b i_axis_demux_128b (  
+    .aselect                       (dds_out_dest_sel),                 // in
+
+    .s_axis_tdata                  (m1_dds_pulse_fifo_tdata_128b),        // in
+    .s_axis_tvalid                 (m1_dds_pulse_fifo_tvalid_128b),       // in
+    .s_axis_tready                 (m1_dds_pulse_fifo_tready_128b),        // out
+
+    .m0_axis_tdata                 (dds2fiber_fifo_tdata_128b),    // out                       
+    .m0_axis_tvalid                (dds2fiber_fifo_tvalid_128b),   // out                       
+    .m0_axis_tready                (dds2fiber_fifo_tready_128b),    // in                      
+
+    .m1_axis_tdata                 (dds2cmac_fifo_tdata_128b),    // out                       
+    .m1_axis_tvalid                (dds2cmac_fifo_tvalid_128b),   // out                       
+    .m1_axis_tready                (dds2cmac_fifo_tready_128b)    // in                      
     );
 
   axis_mux_s2_128b i_axis_mux_s2_128b (
-    .aclk                         (rx_device_clk_1),            // input 
-    .aresetn                      (rx_device_clk_aresetn),      // input 
     .aselect                      (fiber_tx_src_data_sel),      // input 
 
     .s0_axis_tdata                (adc_rx_tdata_128b),          // input 
@@ -1151,6 +1207,145 @@ module system_top  #(
     .s00_axi_rready             (M12_AXI_0_rready)  
   );
 
+///////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////
+
+  assign cmac_refclk_0_clk_p = QSFP3_SI570_CLOCK_P;
+  assign cmac_refclk_0_clk_n = QSFP3_SI570_CLOCK_N;
+  
+  assign cmac_gt_0_grx_p[0]  = QSFP3_RX1_P;
+  assign cmac_gt_0_grx_n[0]  = QSFP3_RX1_N;
+  assign cmac_gt_0_grx_p[1]  = QSFP3_RX2_P;
+  assign cmac_gt_0_grx_n[1]  = QSFP3_RX2_N;
+  assign cmac_gt_0_grx_p[2]  = QSFP3_RX3_P;
+  assign cmac_gt_0_grx_n[2]  = QSFP3_RX3_N;
+  assign cmac_gt_0_grx_p[3]  = QSFP3_RX4_P;
+  assign cmac_gt_0_grx_n[3]  = QSFP3_RX4_N;
+  
+  assign QSFP3_TX1_P =  cmac_gt_0_gtx_p[0];   
+  assign QSFP3_TX1_N =  cmac_gt_0_gtx_n[0];   
+  assign QSFP3_TX2_P =  cmac_gt_0_gtx_p[1];   
+  assign QSFP3_TX2_N =  cmac_gt_0_gtx_n[1];   
+  assign QSFP3_TX3_P =  cmac_gt_0_gtx_p[2];   
+  assign QSFP3_TX3_N =  cmac_gt_0_gtx_n[2];   
+  assign QSFP3_TX4_P =  cmac_gt_0_gtx_p[3];   
+  assign QSFP3_TX4_N =  cmac_gt_0_gtx_n[3];   
+  
+  raw_eth_wrapper i_raw_eth_cmac_0 (    
+    .clk_100_0              (clk_100),
+    .clk_100_reset_0        (clk_100_areset),
+    
+    .cmac_gt_0_grx_n        (cmac_gt_0_grx_n),      //in
+    .cmac_gt_0_grx_p        (cmac_gt_0_grx_p),      //in
+    .cmac_gt_0_gtx_n        (cmac_gt_0_gtx_n),      //out
+    .cmac_gt_0_gtx_p        (cmac_gt_0_gtx_p),      //out
+    .cmac_refclk_0_clk_n    (cmac_refclk_0_clk_n),
+    .cmac_refclk_0_clk_p    (cmac_refclk_0_clk_p),
+    
+    .m_axis_aclk            (tx_device_clk_1),
+    .m_axis_aresetn         (tx_device_clk_aresetn),
+    .m_axis_tdata           (cmac_0_rx_tdata_512b),  // out
+    .m_axis_tvalid          (cmac_0_rx_tvalid_512b), // out
+    .m_axis_tready          (cmac_0_rx_tready_512b_en),  // in
+    
+    .axil_clk_0             (clk_100),
+    .axil_resetn_0          (clk_100_aresetn),
+
+    .s_axil_0_awaddr        (M13_AXI_0_awaddr),          
+    .s_axil_0_awprot        (M13_AXI_0_awprot),          
+    .s_axil_0_awvalid       (M13_AXI_0_awvalid),         
+    .s_axil_0_awready       (M13_AXI_0_awready),         
+                                                         
+    .s_axil_0_wdata         (M13_AXI_0_wdata),           
+    .s_axil_0_wstrb         (M13_AXI_0_wstrb),           
+    .s_axil_0_wvalid        (M13_AXI_0_wvalid),          
+    .s_axil_0_wready        (M13_AXI_0_wready),          
+                                                         
+    .s_axil_0_bresp         (M13_AXI_0_bresp),           
+    .s_axil_0_bvalid        (M13_AXI_0_bvalid),          
+    .s_axil_0_bready        (M13_AXI_0_bready),          
+                                                         
+    .s_axil_0_araddr        (M13_AXI_0_araddr),          
+    .s_axil_0_arprot        (M13_AXI_0_arprot),          
+    .s_axil_0_arvalid       (M13_AXI_0_arvalid),         
+    .s_axil_0_arready       (M13_AXI_0_arready),         
+                                                         
+    .s_axil_0_rdata         (M13_AXI_0_rdata), 
+    .s_axil_0_rresp         (M13_AXI_0_rresp),
+    .s_axil_0_rvalid        (M13_AXI_0_rvalid), 
+    .s_axil_0_rready        (M13_AXI_0_rready),
+
+    .s_axis_clk             (rx_device_clk_1),
+    .s_axis_aresetn         (rx_device_clk_aresetn),
+    .s_axis_tdata           (cmac_0_tx_tdata_512b),     // in 
+    .s_axis_tvalid          (cmac_0_tx_tvalid_512b_en),    // in
+    .s_axis_tready          (cmac_0_tx_tready_512b)     // out
+    );
+
+  axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b (  
+    .aclk                                 (rx_device_clk_1),            // in
+    .aresetn                              (rx_device_clk_aresetn),      // in
+
+    .s_axis_tdata                         (adc_rx_tdata_128b),              // in
+    .s_axis_tvalid                        (adc_rx_tvalid_128b),             // in
+    .s_axis_tready                        ( ),                          // out
+
+    .m_axis_tdata                         (adc_tdata_512b),       // out
+    .m_axis_tvalid                        (adc_tvalid_512b),      // out
+    .m_axis_tready                        (adc_tready_512b)          // in
+    );
+
+  axis_mux_512b i_axis_mux_512b (
+    .aselect                              (cmac_tx_src_data_sel),      // input 
+
+    .s0_axis_tdata                        (adc_tdata_512b),          // input 
+    .s0_axis_tvalid                       (adc_tvalid_512b),         // input 
+    .s0_axis_tready                       (adc_tready_512b),    // output
+
+    .s1_axis_tdata                        (dds2cmac_fifo_tdata_128b),  // input           
+    .s1_axis_tvalid                       (dds2cmac_fifo_tvalid_128b), // input          
+    .s1_axis_tready                       (dds2cmac_fifo_tready_128b),  // output        
+
+    .m_axis_tdata                         (cmac_0_tx_tdata_512b),        // output
+    .m_axis_tvalid                        (cmac_0_tx_tvalid_512b),       // output
+    .m_axis_tready                        (cmac_0_tx_tready_512b_en)        // input 
+    );
+
+  assign cmac_0_tx_tvalid_512b_en  = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tvalid_512b : 1'b0;
+  assign cmac_0_tx_tready_512b_en  = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tready_512b : 1'b0;
+
+  always @(posedge rx_device_clk_1)  
+  begin
+    if (rx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
+      cmac_0_tx_tvalid_512b_cnt_r   <= 32'h0;
+    else if (cmac_0_tx_tvalid_512b_en == 1'b1 && cmac_0_tx_tready_512b_en == 1'b1)
+      cmac_0_tx_tvalid_512b_cnt_r   <= cmac_0_tx_tvalid_512b_cnt_r + 1;
+  end
+//////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////
+  assign cmac_0_rx_tvalid_512b_en  = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tvalid_512b : 1'b0;
+  assign cmac_0_rx_tready_512b_en  = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tready_512b : 1'b0;
+  
+  axis_dwidth_converter_512b_to_128b i_axis_dwidth_converter_512b_to_128b_cmac_0 (  
+    .aclk                                 (tx_device_clk_1),            // in
+    .aresetn                              (tx_device_clk_aresetn),      // in
+
+    .s_axis_tdata                         (cmac_0_rx_tdata_512b),      // in
+    .s_axis_tvalid                        (cmac_0_rx_tvalid_512b_en),     // in
+    .s_axis_tready                        (cmac_0_rx_tready_512b),       // out
+
+    .m_axis_tdata                         (cmac_0_rx_tdata_128b),  // out
+    .m_axis_tvalid                        (cmac_0_rx_tvalid_128b), // out
+    .m_axis_tready                        (cmac_0_rx_tready_128b)  // in
+  );
+  
+  always @(posedge tx_device_clk_1)  
+  begin
+    if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
+      cmac_0_rx_tvalid_512b_cnt_r   <= 32'h0;
+    else if (cmac_0_rx_tvalid_512b_en == 1'b1 && cmac_0_rx_tready_512b_en == 1'b1)
+      cmac_0_rx_tvalid_512b_cnt_r   <= cmac_0_rx_tvalid_512b_cnt_r + 1;
+  end
 
 //////////////////////////
   si5332_wrapper i_si5332_wrapper ( 
@@ -1163,10 +1358,7 @@ module system_top  #(
 
     .scl_in                                   (scl_i),
     .scl_out                                  (scl_o),
-    .scl_t_out                                (scl_t),
+    .scl_t_out                                (scl_t)     
-
-    .qsfp2_clk_in                             (qsfp2_clk_bufg),  
-    .qsfp3_clk_in                             (qsfp3_clk_bufg)       
     );
 
   IOBUF i_scl_iobuf (