diff --git a/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260616044053.wic.gz b/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260717174139.wic.gz similarity index 90% rename from bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260616044053.wic.gz rename to bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260717174139.wic.gz index 0abf7e4..533d1d2 100644 Binary files a/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260616044053.wic.gz and b/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260717174139.wic.gz differ diff --git a/bin/boot.bin b/bin/boot.bin index 755943c..f71aacb 100644 Binary files a/bin/boot.bin and b/bin/boot.bin differ diff --git a/constraints/qsfp_constr.xdc b/constraints/qsfp_constr.xdc index ae5078c..63fceda 100644 --- a/constraints/qsfp_constr.xdc +++ b/constraints/qsfp_constr.xdc @@ -1,7 +1,6 @@ ##################################### # -# VCU128 Rev1.0 XDC -# Date: 01/24/2018 +# ALINX Z19 BOARD # #################################### ################################### @@ -37,45 +36,54 @@ set_property PACKAGE_PIN R33 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 130 set_property PACKAGE_PIN R32 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 130 - MGTREFCLK0P_130 CLK1_P # set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 130 - MGTREFCLK1N_130 # set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 130 - MGTREFCLK1P_130 -# set_property PACKAGE_PIN U54 [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130 -# set_property PACKAGE_PIN U50 [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130 -# set_property PACKAGE_PIN T52 [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130 -# set_property PACKAGE_PIN R54 [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130 -# set_property PACKAGE_PIN U53 [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130 -# set_property PACKAGE_PIN U49 [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130 -# set_property PACKAGE_PIN T51 [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130 -# set_property PACKAGE_PIN R53 [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130 -# set_property PACKAGE_PIN V47 [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130 -# set_property PACKAGE_PIN U45 [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130 -# set_property PACKAGE_PIN T47 [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130 -# set_property PACKAGE_PIN R45 [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130 -# set_property PACKAGE_PIN V46 [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130 -# set_property PACKAGE_PIN U44 [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130 -# set_property PACKAGE_PIN T46 [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130 -# set_property PACKAGE_PIN R44 [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130 + set_property PACKAGE_PIN L42 [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130 + set_property PACKAGE_PIN L41 [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130 + set_property PACKAGE_PIN K40 [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130 + set_property PACKAGE_PIN K39 [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130 + set_property PACKAGE_PIN J42 [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130 + set_property PACKAGE_PIN J41 [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130 + set_property PACKAGE_PIN H40 [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130 + set_property PACKAGE_PIN H39 [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130 + + set_property PACKAGE_PIN M35 [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130 + set_property PACKAGE_PIN M34 [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130 + set_property PACKAGE_PIN L37 [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130 + set_property PACKAGE_PIN L36 [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130 + set_property PACKAGE_PIN K35 [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130 + set_property PACKAGE_PIN K34 [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130 + set_property PACKAGE_PIN J37 [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130 + set_property PACKAGE_PIN J36 [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130 + +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_INTL_LS"] ;# +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_RESETL_LS"] ;# +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_MODPRSL_LS"] ;# ### J77 set_property PACKAGE_PIN W33 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 129 - MGTREFCLK0N_129 CLK3_N set_property PACKAGE_PIN W32 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 129 - MGTREFCLK0P_129 CLK3_P # set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK1N_129 # set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK1P_129 -# set_property PACKAGE_PIN L54 [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129 -# set_property PACKAGE_PIN K52 [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129 -# set_property PACKAGE_PIN J54 [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129 -# set_property PACKAGE_PIN H52 [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129 -# set_property PACKAGE_PIN L53 [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129 -# set_property PACKAGE_PIN K51 [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129 -# set_property PACKAGE_PIN J53 [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129 -# set_property PACKAGE_PIN H51 [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129 -# set_property PACKAGE_PIN L49 [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129 -# set_property PACKAGE_PIN L45 [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129 -# set_property PACKAGE_PIN K47 [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129 -# set_property PACKAGE_PIN J49 [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129 -# set_property PACKAGE_PIN L48 [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129 -# set_property PACKAGE_PIN L44 [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129 -# set_property PACKAGE_PIN K46 [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129 -# set_property PACKAGE_PIN J48 [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129 +# set_property PACKAGE_PIN R42 [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129 +# set_property PACKAGE_PIN R41 [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129 +# set_property PACKAGE_PIN P40 [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129 +# set_property PACKAGE_PIN P39 [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129 +# set_property PACKAGE_PIN N42 [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129 +# set_property PACKAGE_PIN N41 [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129 +# set_property PACKAGE_PIN M40 [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129 +# set_property PACKAGE_PIN M39 [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129 +# set_property PACKAGE_PIN T35 [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129 +# set_property PACKAGE_PIN T34 [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129 +# set_property PACKAGE_PIN R37 [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129 +# set_property PACKAGE_PIN R36 [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129 +# set_property PACKAGE_PIN P35 [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129 +# set_property PACKAGE_PIN P34 [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129 +# set_property PACKAGE_PIN N37 [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129 +# set_property PACKAGE_PIN N36 [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129 + +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_INTL_LS"] ;# +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_RESETL_LS"] ;# +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_MODPRSL_LS"] ;# # set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ; # set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ; # set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ; diff --git a/constraints/timing_constr.xdc b/constraints/timing_constr.xdc index 0f60f39..03977f8 100644 --- a/constraints/timing_constr.xdc +++ b/constraints/timing_constr.xdc @@ -13,8 +13,8 @@ create_clock -name clkin8 -period 2.0 [get_ports clkin8_p] ##create_clock -name sysref2 -period 4.0 [get_ports sysref2_p] # not a clock create_clock -period 2.640 -name QSFP1_SI570_CLOCK_P [get_ports QSFP1_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz -create_clock -period 2.640 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P] -create_clock -period 2.640 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P] +create_clock -period 6.400 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P] +create_clock -period 6.400 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P] create_clock -period 2.640 -name QSFP4_SI570_CLOCK_P [get_ports QSFP4_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz diff --git a/create_proj.tcl b/create_proj.tcl index 1564acc..9afeccc 100644 --- a/create_proj.tcl +++ b/create_proj.tcl @@ -3,7 +3,7 @@ # # create_proj.tcl: Tcl script for re-creating project 'alinx_z19_ad9081' # -# Generated by Vivado on Tue Jun 02 12:21:15 EDT 2026 +# Generated by Vivado on Fri Jul 17 15:54:45 EDT 2026 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -27,61 +27,67 @@ # # 3. The following remote source files that were added to the original project:- # -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_register_slice_128/axis_register_slice_128.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_latency10/dds_latency10.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_register_slice_240/axis_register_slice_240.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_register_slice_512/axis_register_slice_512.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/ad_3w_spi.v" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/ad_iobuf.v" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/axis_mux_128b.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/axis_mux_s2_128b.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/global_types.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_gen_cfg.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/clk_gen_cfg_2.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_cmd_gen.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_2x_top.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_gen.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0_S00_AXI.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/tick_gen.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_wrapper.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_intfc_x4.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/i2c.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/i2c_st.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/qsfp1_capture_intfc.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/qsfp4_playback_intfc.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_clk_configurator.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/si5332_wrapper.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/system_top.v" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_32b/axis_dwidth_converter_512b_to_32b.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/ila_3/ila_3.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/constraints/qsfp_constr.xdc" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/constraints/system_constr.xdc" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/constraints/timing_constr.xdc" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/sim/tb_cap_plybk.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/sim/dds_wrapper_tb.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/sim/test_bench.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_rx.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_packer.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_tx.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_unpacker.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_register_slice_128/axis_register_slice_128.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_latency10/dds_latency10.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/ila_3/ila_3.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_register_slice_240/axis_register_slice_240.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_register_slice_512/axis_register_slice_512.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/ad_3w_spi.v" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/ad_iobuf.v" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_demux_128b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_mux_128b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_mux_512b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_mux_s2_128b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/global_types.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_gen_cfg.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/clk_gen_cfg_2.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_cmd_gen.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_2x_top.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_gen.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0_S00_AXI.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/tick_gen.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_wrapper.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_intfc_x4.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/i2c.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/i2c_st.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/qsfp1_capture_intfc.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/qsfp4_playback_intfc.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_clk_configurator.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/si5332_wrapper.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/system_top.v" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_32b/axis_dwidth_converter_512b_to_32b.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/constraints/qsfp_constr.xdc" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/constraints/system_constr.xdc" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/constraints/timing_constr.xdc" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/sim/dds_wrapper_tb.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/sim/tb_cap_plybk.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/sim/test_bench.vhd" # #***************************************************************************************** @@ -89,6 +95,12 @@ proc checkRequiredFiles { origin_dir} { set status true set files [list \ + "[file normalize "$origin_dir/source/eth_flowctrl_rx.vhd"]"\ + "[file normalize "$origin_dir/source/eth_frame_packer.vhd"]"\ + "[file normalize "$origin_dir/source/eth_flowctrl_tx.vhd"]"\ + "[file normalize "$origin_dir/source/eth_frame_unpacker.vhd"]"\ + "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"]"\ + "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_register_slice_128/axis_register_slice_128.xci"]"\ "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci"]"\ "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci"]"\ @@ -98,17 +110,19 @@ proc checkRequiredFiles { origin_dir} { "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci"]"\ "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci"]"\ + "[file normalize "$origin_dir/ip_repo/ila_3/ila_3.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_register_slice_240/axis_register_slice_240.xci"]"\ "[file normalize "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_register_slice_512/axis_register_slice_512.xci"]"\ - "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"]"\ - "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"]"\ + "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"]"\ "[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"]"\ "[file normalize "$origin_dir/source/ad_3w_spi.v"]"\ "[file normalize "$origin_dir/source/ad_iobuf.v"]"\ + "[file normalize "$origin_dir/source/axis_demux_128b.vhd"]"\ "[file normalize "$origin_dir/source/axis_mux_128b.vhd"]"\ + "[file normalize "$origin_dir/source/axis_mux_512b.vhd"]"\ "[file normalize "$origin_dir/source/axis_mux_s2_128b.vhd"]"\ "[file normalize "$origin_dir/ip_repo/Si5332/src/global_types.vhd"]"\ "[file normalize "$origin_dir/ip_repo/Si5332/src/si5341_gen_cfg.vhd"]"\ @@ -136,13 +150,11 @@ proc checkRequiredFiles { origin_dir} { "[file normalize "$origin_dir/ip_repo/Si5332/src/si5332_wrapper.vhd"]"\ "[file normalize "$origin_dir/source/system_top.v"]"\ "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_32b/axis_dwidth_converter_512b_to_32b.xci"]"\ - "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"]"\ - "[file normalize "$origin_dir/ip_repo/ila_3/ila_3.xci"]"\ "[file normalize "$origin_dir/constraints/qsfp_constr.xdc"]"\ "[file normalize "$origin_dir/constraints/system_constr.xdc"]"\ "[file normalize "$origin_dir/constraints/timing_constr.xdc"]"\ - "[file normalize "$origin_dir/sim/tb_cap_plybk.vhd"]"\ "[file normalize "$origin_dir/sim/dds_wrapper_tb.vhd"]"\ + "[file normalize "$origin_dir/sim/tb_cap_plybk.vhd"]"\ "[file normalize "$origin_dir/sim/test_bench.vhd"]"\ ] foreach ifile $files { @@ -250,6 +262,18 @@ create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu19eg-ffvc1760-2 set proj_dir [get_property directory [current_project]] # Reconstruct message rules +set_msg_config -id {Vivado 12-1790} -string {{Evaluation} {features} {should} {NOT} {be} {used} {in} {production} {systems.}} -new_severity {WARNING} -ruleid {1} -source 2 +set_msg_config -id {Designutils 20-3303} -string {{HDPYFinalizeIO}} -new_severity {INFO} -ruleid {10} -source 2 +set_msg_config -id {Place 30-73} -string {{axi_spi}} -new_severity {WARNING} -ruleid {11} -source 2 +set_msg_config -string {{PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY}} -new_severity {WARNING} -ruleid {12} -source 2 +set_msg_config -id {BD 41-1343} -new_severity {WARNING} -ruleid {2} -source 2 +set_msg_config -id {BD 41-1306} -new_severity {WARNING} -ruleid {3} -source 2 +set_msg_config -id {BD 41-1276} -severity {CRITICAL WARNING} -new_severity {ERROR} -ruleid {4} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {41} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {42} -source 2 +set_msg_config -id {IP_Flow 19-3656} -new_severity {INFO} -ruleid {5} -source 2 +set_msg_config -id {IP_Flow 19-4623} -new_severity {INFO} -ruleid {6} -source 2 +set_msg_config -id {IP_Flow 19-459} -new_severity {INFO} -ruleid {7} -source 2 set_msg_config -id {[BD 41-1271]} -suppress -ruleid {8} -source 2 set_msg_config -id {[BD 41-1306]} -suppress -ruleid {9} -source 2 @@ -270,14 +294,14 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "sim_compile_state" -value "1" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "97" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "97" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "97" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "97" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "97" -objects $obj -set_property -name "webtalk.xcelium_export_sim" -value "15" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "97" -objects $obj -set_property -name "webtalk.xsim_launch_sim" -value "103" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "108" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "108" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "108" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "108" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "108" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "5" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "108" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "105" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_COMP_DECL XPM_FIFO XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -297,6 +321,12 @@ if { $obj != {} } { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ + [file normalize "${origin_dir}/source/eth_flowctrl_rx.vhd"] \ + [file normalize "${origin_dir}/source/eth_frame_packer.vhd"] \ + [file normalize "${origin_dir}/source/eth_flowctrl_tx.vhd"] \ + [file normalize "${origin_dir}/source/eth_frame_unpacker.vhd"] \ + [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"] \ + [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_register_slice_128/axis_register_slice_128.xci"] \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci"] \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci"] \ @@ -306,17 +336,19 @@ set files [list \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci"] \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci"] \ + [file normalize "${origin_dir}/ip_repo/ila_3/ila_3.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_register_slice_240/axis_register_slice_240.xci"] \ [file normalize "${origin_dir}/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_register_slice_512/axis_register_slice_512.xci"] \ - [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"] \ - [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"] \ + [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"] \ [file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"] \ [file normalize "${origin_dir}/source/ad_3w_spi.v"] \ [file normalize "${origin_dir}/source/ad_iobuf.v"] \ + [file normalize "${origin_dir}/source/axis_demux_128b.vhd"] \ [file normalize "${origin_dir}/source/axis_mux_128b.vhd"] \ + [file normalize "${origin_dir}/source/axis_mux_512b.vhd"] \ [file normalize "${origin_dir}/source/axis_mux_s2_128b.vhd"] \ [file normalize "${origin_dir}/ip_repo/Si5332/src/global_types.vhd"] \ [file normalize "${origin_dir}/ip_repo/Si5332/src/si5341_gen_cfg.vhd"] \ @@ -348,6 +380,44 @@ set files [list \ add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/source/eth_flowctrl_rx.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/eth_frame_packer.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/eth_flowctrl_tx.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/eth_frame_unpacker.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj +} +set_property -name "registered_with_manager" -value "1" -objects $file_obj + +set file "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj +} +set_property -name "registered_with_manager" -value "1" -objects $file_obj + set file "$origin_dir/ip_repo/axis_register_slice_128/axis_register_slice_128.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -429,6 +499,15 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } +set file "$origin_dir/ip_repo/ila_3/ila_3.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + set file "$origin_dir/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -465,23 +544,14 @@ if { ![get_property "is_locked" $file_obj] } { } set_property -name "registered_with_manager" -value "1" -objects $file_obj -set file "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" +set file "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj -} set_property -name "registered_with_manager" -value "1" -objects $file_obj - -set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj if { ![get_property "is_locked" $file_obj] } { - set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set_property -name "registered_with_manager" -value "1" -objects $file_obj set file "$origin_dir/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci" set file [file normalize $file] @@ -497,11 +567,21 @@ set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "netlist_only" -value "0" -objects $file_obj +set file "$origin_dir/source/axis_demux_128b.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + set file "$origin_dir/source/axis_mux_128b.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "file_type" -value "VHDL" -objects $file_obj +set file "$origin_dir/source/axis_mux_512b.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + set file "$origin_dir/source/axis_mux_s2_128b.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -648,48 +728,6 @@ set_property -name "top" -value "system_top" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "vhdl_generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [file normalize "${origin_dir}/ip_repo/ila_3/ila_3.xci"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip_repo/ila_3/ila_3.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - # Create 'constrs_1' fileset (if not found) if {[string equal [get_filesets -quiet constrs_1] ""]} { create_fileset -constrset constrs_1 @@ -734,19 +772,19 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] set files [list \ - [file normalize "${origin_dir}/sim/tb_cap_plybk.vhd"] \ [file normalize "${origin_dir}/sim/dds_wrapper_tb.vhd"] \ + [file normalize "${origin_dir}/sim/tb_cap_plybk.vhd"] \ [file normalize "${origin_dir}/sim/test_bench.vhd"] \ ] add_files -norecurse -fileset $obj $files # Set 'sim_1' fileset file properties for remote files -set file "$origin_dir/sim/tb_cap_plybk.vhd" +set file "$origin_dir/sim/dds_wrapper_tb.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] set_property -name "file_type" -value "VHDL" -objects $file_obj -set file "$origin_dir/sim/dds_wrapper_tb.vhd" +set file "$origin_dir/sim/tb_cap_plybk.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] set_property -name "file_type" -value "VHDL" -objects $file_obj @@ -762,7 +800,7 @@ set_property -name "file_type" -value "VHDL" -objects $file_obj # Set 'sim_1' fileset properties set obj [get_filesets sim_1] -set_property -name "top" -value "tb_cap_plybk" -objects $obj +set_property -name "top" -value "dds_wrapper_tb" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj set_property -name "xsim.simulate.log_all_signals" -value "1" -objects $obj @@ -776,6 +814,1077 @@ set obj [get_filesets utils_1] # Adding sources referenced in BDs, if not already added +if { [get_files [list eth_flowctrl_rx.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_rx.vhd +} +if { [get_files [list eth_frame_packer.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_packer.vhd +} +if { [get_files [list eth_flowctrl_tx.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_tx.vhd +} +if { [get_files [list eth_frame_unpacker.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_unpacker.vhd +} + + +# Proc to create BD raw_eth +proc cr_bd_raw_eth { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# eth_flowctrl_rx, eth_frame_packer, eth_flowctrl_tx, eth_frame_unpacker + + + + # CHANGE DESIGN NAME HERE + set design_name raw_eth + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:axis_register_slice:1.1\ + xilinx.com:ip:axis_subset_converter:1.1\ + xilinx.com:ip:axis_data_fifo:2.0\ + xilinx.com:ip:cmac_usplus:3.1\ + xilinx.com:ip:system_ila:1.1\ + xilinx.com:ip:util_vector_logic:2.0\ + xilinx.com:ip:c_counter_binary:12.0\ + xilinx.com:ip:smartconnect:1.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + user:user:axi_regs_32:1.0\ + xilinx.com:ip:xlslice:1.0\ + xilinx.com:ip:xlconcat:2.1\ + xilinx.com:ip:xpm_cdc_gen:1.0\ + xilinx.com:ip:xlconstant:1.1\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + eth_flowctrl_rx\ + eth_frame_packer\ + eth_flowctrl_tx\ + eth_frame_unpacker\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + +# Hierarchical cell: ETH_regs +proc create_hier_cell_ETH_regs { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ETH_regs() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + + # Create pins + create_bd_pin -dir O -from 47 -to 0 dest_addr + create_bd_pin -dir O -from 47 -to 0 source_addr + create_bd_pin -dir O -from 15 -to 0 EtherType + create_bd_pin -dir I cmac_clk + create_bd_pin -dir I aclk + create_bd_pin -dir I aresetn + create_bd_pin -dir O -from 0 -to 0 prog_full_manual + create_bd_pin -dir O -from 31 -to 0 prog_full_on + create_bd_pin -dir O -from 31 -to 0 prog_full_off + create_bd_pin -dir I -from 31 -to 0 tx_frame_cnt + create_bd_pin -dir I -from 31 -to 0 tx_frame_underrun_cnt + create_bd_pin -dir I -from 31 -to 0 tx_pause_cnt + create_bd_pin -dir I -from 31 -to 0 rx_frame_cnt + create_bd_pin -dir I -from 31 -to 0 rx_frame_err_cnt + create_bd_pin -dir I -from 31 -to 0 rx_pause_cnt + create_bd_pin -dir I -from 31 -to 0 rx_fifo_overflow_cnt + + # Create instance: axi_regs_32_0, and set properties + set axi_regs_32_0 [ create_bd_cell -type ip -vlnv user:user:axi_regs_32:1.0 axi_regs_32_0 ] + + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + set_property CONFIG.DIN_FROM {15} $xlslice_0 + + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {32} \ + CONFIG.IN1_WIDTH {16} \ + ] $xlconcat_0 + + + # Create instance: xlconcat_1, and set properties + set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {32} \ + CONFIG.IN1_WIDTH {16} \ + ] $xlconcat_1 + + + # Create instance: xlslice_1, and set properties + set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + set_property CONFIG.DIN_FROM {15} $xlslice_1 + + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property CONFIG.DIN_FROM {15} $xlslice_2 + + + # Create instance: xpm_cdc_gen_0, and set properties + set xpm_cdc_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {48} \ + ] $xpm_cdc_gen_0 + + + # Create instance: const_1b0, and set properties + set const_1b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1b0 ] + set_property CONFIG.CONST_VAL {0} $const_1b0 + + + # Create instance: xpm_cdc_gen_1, and set properties + set xpm_cdc_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_1 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {48} \ + ] $xpm_cdc_gen_1 + + + # Create instance: xpm_cdc_gen_2, and set properties + set xpm_cdc_gen_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_2 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {16} \ + ] $xpm_cdc_gen_2 + + + # Create instance: const_32b0, and set properties + set const_32b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_32b0 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {32} \ + ] $const_32b0 + + + # Create instance: xlslice_3, and set properties + set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ] + set_property CONFIG.DIN_FROM {0} $xlslice_3 + + + # Create instance: xpm_cdc_gen_3, and set properties + set xpm_cdc_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_3 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {1} \ + ] $xpm_cdc_gen_3 + + + # Create instance: xpm_cdc_gen_4, and set properties + set xpm_cdc_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_4 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_4 + + + # Create instance: xpm_cdc_gen_5, and set properties + set xpm_cdc_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_5 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_5 + + + # Create instance: xpm_cdc_gen_16, and set properties + set xpm_cdc_gen_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_16 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_16 + + + # Create instance: xpm_cdc_gen_17, and set properties + set xpm_cdc_gen_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_17 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_17 + + + # Create instance: xpm_cdc_gen_18, and set properties + set xpm_cdc_gen_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_18 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_18 + + + # Create instance: xpm_cdc_gen_19, and set properties + set xpm_cdc_gen_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_19 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_19 + + + # Create instance: xpm_cdc_gen_20, and set properties + set xpm_cdc_gen_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_20 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_20 + + + # Create instance: xpm_cdc_gen_21, and set properties + set xpm_cdc_gen_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_21 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_21 + + + # Create instance: xpm_cdc_gen_22, and set properties + set xpm_cdc_gen_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_22 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_22 + + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_regs_32_0/S_AXI] + + # Create port connections + connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_regs_32_0/S_AXI_ACLK] [get_bd_pins xpm_cdc_gen_16/dest_clk] [get_bd_pins xpm_cdc_gen_17/dest_clk] [get_bd_pins xpm_cdc_gen_18/dest_clk] [get_bd_pins xpm_cdc_gen_19/dest_clk] [get_bd_pins xpm_cdc_gen_20/dest_clk] [get_bd_pins xpm_cdc_gen_21/dest_clk] [get_bd_pins xpm_cdc_gen_22/dest_clk] + connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins axi_regs_32_0/S_AXI_ARESETN] + connect_bd_net -net axi_regs_32_0_reg0_out [get_bd_pins axi_regs_32_0/reg0_out] [get_bd_pins xlconcat_0/In0] [get_bd_pins axi_regs_32_0/reg0_in] + connect_bd_net -net axi_regs_32_0_reg1_out [get_bd_pins axi_regs_32_0/reg1_out] [get_bd_pins xlslice_0/Din] [get_bd_pins axi_regs_32_0/reg1_in] + connect_bd_net -net axi_regs_32_0_reg2_out [get_bd_pins axi_regs_32_0/reg2_out] [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_regs_32_0/reg2_in] + connect_bd_net -net axi_regs_32_0_reg3_out [get_bd_pins axi_regs_32_0/reg3_out] [get_bd_pins xlslice_1/Din] [get_bd_pins axi_regs_32_0/reg3_in] + connect_bd_net -net axi_regs_32_0_reg4_out [get_bd_pins axi_regs_32_0/reg4_out] [get_bd_pins xlslice_2/Din] [get_bd_pins axi_regs_32_0/reg4_in] + connect_bd_net -net axi_regs_32_0_reg5_out [get_bd_pins axi_regs_32_0/reg5_out] [get_bd_pins xlslice_3/Din] [get_bd_pins axi_regs_32_0/reg5_in] + connect_bd_net -net axi_regs_32_0_reg6_out [get_bd_pins axi_regs_32_0/reg6_out] [get_bd_pins axi_regs_32_0/reg6_in] [get_bd_pins xpm_cdc_gen_4/src_in] + connect_bd_net -net axi_regs_32_0_reg7_out [get_bd_pins axi_regs_32_0/reg7_out] [get_bd_pins axi_regs_32_0/reg7_in] [get_bd_pins xpm_cdc_gen_5/src_in] + connect_bd_net -net cmac_clk_1 [get_bd_pins cmac_clk] [get_bd_pins xpm_cdc_gen_0/dest_clk] [get_bd_pins xpm_cdc_gen_2/dest_clk] [get_bd_pins xpm_cdc_gen_1/dest_clk] [get_bd_pins xpm_cdc_gen_3/dest_clk] [get_bd_pins xpm_cdc_gen_4/dest_clk] [get_bd_pins xpm_cdc_gen_5/dest_clk] + connect_bd_net -net const_1b0_dout [get_bd_pins const_1b0/dout] [get_bd_pins xpm_cdc_gen_0/src_clk] [get_bd_pins xpm_cdc_gen_1/src_clk] [get_bd_pins xpm_cdc_gen_2/src_clk] [get_bd_pins xpm_cdc_gen_3/src_clk] [get_bd_pins xpm_cdc_gen_4/src_clk] [get_bd_pins xpm_cdc_gen_5/src_clk] [get_bd_pins xpm_cdc_gen_16/src_clk] [get_bd_pins xpm_cdc_gen_17/src_clk] [get_bd_pins xpm_cdc_gen_18/src_clk] [get_bd_pins xpm_cdc_gen_19/src_clk] [get_bd_pins xpm_cdc_gen_20/src_clk] [get_bd_pins xpm_cdc_gen_21/src_clk] [get_bd_pins xpm_cdc_gen_22/src_clk] + connect_bd_net -net const_32b0_dout [get_bd_pins const_32b0/dout] [get_bd_pins axi_regs_32_0/reg9_in] [get_bd_pins axi_regs_32_0/reg8_in] [get_bd_pins axi_regs_32_0/reg10_in] [get_bd_pins axi_regs_32_0/reg11_in] [get_bd_pins axi_regs_32_0/reg12_in] [get_bd_pins axi_regs_32_0/reg13_in] [get_bd_pins axi_regs_32_0/reg14_in] [get_bd_pins axi_regs_32_0/reg15_in] [get_bd_pins axi_regs_32_0/reg23_in] [get_bd_pins axi_regs_32_0/reg24_in] [get_bd_pins axi_regs_32_0/reg25_in] [get_bd_pins axi_regs_32_0/reg26_in] [get_bd_pins axi_regs_32_0/reg27_in] [get_bd_pins axi_regs_32_0/reg28_in] [get_bd_pins axi_regs_32_0/reg29_in] [get_bd_pins axi_regs_32_0/reg30_in] [get_bd_pins axi_regs_32_0/reg31_in] + connect_bd_net -net rx_fifo_overflow_cnt_1 [get_bd_pins rx_fifo_overflow_cnt] [get_bd_pins xpm_cdc_gen_22/src_in] + connect_bd_net -net rx_frame_cnt_1 [get_bd_pins rx_frame_cnt] [get_bd_pins xpm_cdc_gen_19/src_in] + connect_bd_net -net rx_frame_err_cnt_1 [get_bd_pins rx_frame_err_cnt] [get_bd_pins xpm_cdc_gen_20/src_in] + connect_bd_net -net rx_pause_cnt_1 [get_bd_pins rx_pause_cnt] [get_bd_pins xpm_cdc_gen_21/src_in] + connect_bd_net -net tx_frame_cnt_1 [get_bd_pins tx_frame_cnt] [get_bd_pins xpm_cdc_gen_16/src_in] + connect_bd_net -net tx_frame_underrun_cnt_1 [get_bd_pins tx_frame_underrun_cnt] [get_bd_pins xpm_cdc_gen_17/src_in] + connect_bd_net -net tx_pause_cnt_1 [get_bd_pins tx_pause_cnt] [get_bd_pins xpm_cdc_gen_18/src_in] + connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xpm_cdc_gen_0/src_in] + connect_bd_net -net xlconcat_1_dout [get_bd_pins xlconcat_1/dout] [get_bd_pins xpm_cdc_gen_1/src_in] + connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins xlconcat_1/In1] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins xpm_cdc_gen_2/src_in] + connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins xpm_cdc_gen_3/src_in] + connect_bd_net -net xpm_cdc_gen_0_dest_out [get_bd_pins xpm_cdc_gen_0/dest_out] [get_bd_pins dest_addr] + connect_bd_net -net xpm_cdc_gen_18_dest_out [get_bd_pins xpm_cdc_gen_18/dest_out] [get_bd_pins axi_regs_32_0/reg18_in] + connect_bd_net -net xpm_cdc_gen_19_dest_out [get_bd_pins xpm_cdc_gen_19/dest_out] [get_bd_pins axi_regs_32_0/reg19_in] + connect_bd_net -net xpm_cdc_gen_1_dest_out [get_bd_pins xpm_cdc_gen_1/dest_out] [get_bd_pins source_addr] + connect_bd_net -net xpm_cdc_gen_20_dest_out [get_bd_pins xpm_cdc_gen_20/dest_out] [get_bd_pins axi_regs_32_0/reg20_in] + connect_bd_net -net xpm_cdc_gen_21_dest_out [get_bd_pins xpm_cdc_gen_21/dest_out] [get_bd_pins axi_regs_32_0/reg21_in] + connect_bd_net -net xpm_cdc_gen_22_dest_out [get_bd_pins xpm_cdc_gen_22/dest_out] [get_bd_pins axi_regs_32_0/reg22_in] + connect_bd_net -net xpm_cdc_gen_2_dest_out [get_bd_pins xpm_cdc_gen_2/dest_out] [get_bd_pins EtherType] + connect_bd_net -net xpm_cdc_gen_3_dest_out [get_bd_pins xpm_cdc_gen_3/dest_out] [get_bd_pins prog_full_manual] + connect_bd_net -net xpm_cdc_gen_4_dest_out [get_bd_pins xpm_cdc_gen_4/dest_out] [get_bd_pins prog_full_on] + connect_bd_net -net xpm_cdc_gen_5_dest_out [get_bd_pins xpm_cdc_gen_5/dest_out] [get_bd_pins prog_full_off] + connect_bd_net -net xpm_cdc_gen_6_dest_out [get_bd_pins xpm_cdc_gen_16/dest_out] [get_bd_pins axi_regs_32_0/reg16_in] + connect_bd_net -net xpm_cdc_gen_7_dest_out [get_bd_pins xpm_cdc_gen_17/dest_out] [get_bd_pins axi_regs_32_0/reg17_in] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: Ethernet +proc create_hier_cell_Ethernet { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_Ethernet() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXIL + + + # Create pins + create_bd_pin -dir O -type clk axis_aclk + create_bd_pin -dir O -from 0 -to 0 axis_aresetn + create_bd_pin -dir I -type clk axil_clk + create_bd_pin -dir I clk_100_reset + create_bd_pin -dir I clk_100 + create_bd_pin -dir I -from 31 -to 0 rx_fifo_wr_data_cnt + create_bd_pin -dir I -type rst axil_resetn + create_bd_pin -dir I -from 0 -to 0 rx_fifo_overflow + + # Create instance: eth_flowctrl_rx_i, and set properties + set block_name eth_flowctrl_rx + set block_cell_name eth_flowctrl_rx_i + if { [catch {set eth_flowctrl_rx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_flowctrl_rx_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: cmac_usplus_i, and set properties + set cmac_usplus_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_i ] + set_property -dict [list \ + CONFIG.CMAC_CAUI4_MODE {1} \ + CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y1} \ + CONFIG.ENABLE_AXI_INTERFACE {1} \ + CONFIG.ENABLE_PIPELINE_REG {1} \ + CONFIG.GT_GROUP_SELECT {X0Y12~X0Y15} \ + CONFIG.GT_REF_CLK_FREQ {156.25} \ + CONFIG.RX_CHECK_ACK {0} \ + CONFIG.RX_FLOW_CONTROL {1} \ + CONFIG.TX_FLOW_CONTROL {1} \ + CONFIG.TX_SA_GPP {0x000000000000} \ + CONFIG.TX_SA_PPP {0x000000000000} \ + CONFIG.USER_INTERFACE {AXIS} \ + ] $cmac_usplus_i + + + # Create instance: eth_frame_packer_i, and set properties + set block_name eth_frame_packer + set block_cell_name eth_frame_packer_i + if { [catch {set eth_frame_packer_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_frame_packer_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: eth_flowctrl_tx_i, and set properties + set block_name eth_flowctrl_tx + set block_cell_name eth_flowctrl_tx_i + if { [catch {set eth_flowctrl_tx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_flowctrl_tx_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: eth_frame_unpacker_i, and set properties + set block_name eth_frame_unpacker + set block_cell_name eth_frame_unpacker_i + if { [catch {set eth_frame_unpacker_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_frame_unpacker_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: system_ila_i, and set properties + set system_ila_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_i ] + set_property -dict [list \ + CONFIG.C_MON_TYPE {MIX} \ + CONFIG.C_NUM_MONITOR_SLOTS {6} \ + CONFIG.C_NUM_OF_PROBES {20} \ + CONFIG.C_SLOT {5} \ + CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \ + CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \ + CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + ] $system_ila_i + + + # Create instance: ETH_regs + create_hier_cell_ETH_regs $hier_obj ETH_regs + + # Create instance: rst_inv_i, and set properties + set rst_inv_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rst_inv_i ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $rst_inv_i + + + # Create instance: counter_i, and set properties + set counter_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 counter_i ] + set_property -dict [list \ + CONFIG.CE {true} \ + CONFIG.Fb_Latency_Configuration {Automatic} \ + CONFIG.Latency_Configuration {Automatic} \ + CONFIG.Load {false} \ + CONFIG.Load_Sense {Active_High} \ + CONFIG.Output_Width {32} \ + CONFIG.Restrict_Count {false} \ + CONFIG.SCLR {true} \ + CONFIG.SSET {false} \ + CONFIG.Sync_Threshold_Output {false} \ + ] $counter_i + + + # Create instance: smartcon_i, and set properties + set smartcon_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartcon_i ] + set_property -dict [list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $smartcon_i + + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins smartcon_i/S00_AXI] [get_bd_intf_pins S_AXIL] + connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins ETH_regs/S_AXI] [get_bd_intf_pins smartcon_i/M01_AXI] + connect_bd_intf_net -intf_net cmac_axis_rx [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins eth_frame_unpacker_i/s_axis] + connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_axis_rx] [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins system_ila_i/SLOT_4_AXIS] + connect_bd_intf_net -intf_net cmac_refclk [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins cmac_usplus_i/gt_ref_clk] + connect_bd_intf_net -intf_net cmac_tx_fifo_M_AXIS [get_bd_intf_pins S_AXIS] [get_bd_intf_pins eth_frame_packer_i/s_axis] + connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_tx_fifo_M_AXIS] [get_bd_intf_pins S_AXIS] [get_bd_intf_pins system_ila_i/SLOT_0_AXIS] + connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_pins cmac_gt] [get_bd_intf_pins cmac_usplus_i/gt_serial_port] + connect_bd_intf_net -intf_net cmac_usplus_i_stat_rx [get_bd_intf_pins cmac_usplus_i/stat_rx] [get_bd_intf_pins system_ila_i/SLOT_3_STATISTICS_PORTS] + connect_bd_intf_net -intf_net cmac_usplus_i_stat_tx [get_bd_intf_pins cmac_usplus_i/stat_tx] [get_bd_intf_pins system_ila_i/SLOT_2_STATISTICS_PORTS] + connect_bd_intf_net -intf_net packer_m_axis [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins cmac_usplus_i/axis_tx] + connect_bd_intf_net -intf_net [get_bd_intf_nets packer_m_axis] [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_1_AXIS] + connect_bd_intf_net -intf_net smartcon_i_M00_AXI [get_bd_intf_pins cmac_usplus_i/s_axi] [get_bd_intf_pins smartcon_i/M00_AXI] + connect_bd_intf_net -intf_net unpacker_m_axis [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins M_AXIS] + connect_bd_intf_net -intf_net [get_bd_intf_nets unpacker_m_axis] [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_5_AXIS] + + # Create port connections + connect_bd_net -net ETH_regs_prog_full_off [get_bd_pins ETH_regs/prog_full_off] [get_bd_pins system_ila_i/probe12] [get_bd_pins eth_flowctrl_tx_i/prog_full_off] + connect_bd_net -net ETH_regs_prog_full_on [get_bd_pins ETH_regs/prog_full_on] [get_bd_pins system_ila_i/probe11] [get_bd_pins eth_flowctrl_tx_i/prog_full_on] + connect_bd_net -net axil_clk [get_bd_pins axil_clk] [get_bd_pins ETH_regs/aclk] [get_bd_pins cmac_usplus_i/s_axi_aclk] [get_bd_pins smartcon_i/aclk] + connect_bd_net -net axil_resetn [get_bd_pins axil_resetn] [get_bd_pins ETH_regs/aresetn] [get_bd_pins rst_inv_i/Op1] [get_bd_pins smartcon_i/aresetn] + connect_bd_net -net clk_100 [get_bd_pins clk_100] [get_bd_pins cmac_usplus_i/drp_clk] [get_bd_pins cmac_usplus_i/init_clk] + connect_bd_net -net clk_100_reset [get_bd_pins clk_100_reset] [get_bd_pins cmac_usplus_i/sys_reset] + connect_bd_net -net cmac_reset [get_bd_pins cmac_usplus_i/usr_tx_reset] [get_bd_pins proc_sys_reset_0/ext_reset_in] + connect_bd_net -net cmac_resetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins axis_aresetn] [get_bd_pins system_ila_i/resetn] [get_bd_pins eth_flowctrl_rx_i/resetn] [get_bd_pins eth_frame_packer_i/resetn] [get_bd_pins eth_flowctrl_tx_i/resetn] [get_bd_pins eth_frame_unpacker_i/resetn] + connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins rx_fifo_wr_data_cnt] [get_bd_pins system_ila_i/probe10] [get_bd_pins eth_flowctrl_tx_i/data_cnt] + connect_bd_net -net cmac_usplus_i_gt_powergoodout [get_bd_pins cmac_usplus_i/gt_powergoodout] [get_bd_pins system_ila_i/probe0] + connect_bd_net -net cmac_usplus_i_gt_txusrclk2 [get_bd_pins cmac_usplus_i/gt_txusrclk2] [get_bd_pins axis_aclk] [get_bd_pins cmac_usplus_i/rx_clk] [get_bd_pins system_ila_i/clk] [get_bd_pins ETH_regs/cmac_clk] [get_bd_pins counter_i/CLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins eth_flowctrl_rx_i/clk] [get_bd_pins eth_frame_packer_i/clk] [get_bd_pins eth_flowctrl_tx_i/clk] [get_bd_pins eth_frame_unpacker_i/clk] + connect_bd_net -net cmac_usplus_i_stat_rx_pause [get_bd_pins cmac_usplus_i/stat_rx_pause] [get_bd_pins system_ila_i/probe16] [get_bd_pins eth_flowctrl_rx_i/rx_pause] + connect_bd_net -net cmac_usplus_i_stat_rx_pause_quanta8 [get_bd_pins cmac_usplus_i/stat_rx_pause_quanta8] [get_bd_pins system_ila_i/probe17] [get_bd_pins eth_flowctrl_rx_i/rx_pause_quanta8] + connect_bd_net -net counter_i_Q [get_bd_pins counter_i/Q] [get_bd_pins ETH_regs/rx_fifo_overflow_cnt] + connect_bd_net -net ctl_tx_pause_req [get_bd_pins eth_flowctrl_tx_i/ctl_tx_pause_req] [get_bd_pins cmac_usplus_i/ctl_tx_pause_req] [get_bd_pins system_ila_i/probe9] + connect_bd_net -net ctl_tx_resend_pause [get_bd_pins eth_flowctrl_tx_i/ctl_tx_resend_pause] [get_bd_pins cmac_usplus_i/ctl_tx_resend_pause] [get_bd_pins system_ila_i/probe8] + connect_bd_net -net eth_flowctrl_rx_0_pause [get_bd_pins eth_flowctrl_rx_i/pause] [get_bd_pins system_ila_i/probe15] + connect_bd_net -net eth_flowctrl_rx_0_rx_pause_cnt [get_bd_pins eth_flowctrl_rx_i/rx_pause_cnt] [get_bd_pins ETH_regs/rx_pause_cnt] [get_bd_pins system_ila_i/probe14] + connect_bd_net -net eth_flowctrl_tx_i_tx_pause_cnt [get_bd_pins eth_flowctrl_tx_i/tx_pause_cnt] [get_bd_pins ETH_regs/tx_pause_cnt] [get_bd_pins system_ila_i/probe19] + connect_bd_net -net eth_frame_packer_i_tx_cnt [get_bd_pins eth_frame_packer_i/tx_cnt] [get_bd_pins ETH_regs/tx_frame_cnt] [get_bd_pins system_ila_i/probe13] + connect_bd_net -net eth_frame_unpacker_i_rx_frame_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_cnt] [get_bd_pins ETH_regs/rx_frame_cnt] [get_bd_pins system_ila_i/probe18] + connect_bd_net -net eth_regs_EtherType [get_bd_pins ETH_regs/EtherType] [get_bd_pins system_ila_i/probe6] [get_bd_pins eth_frame_packer_i/cfg_eth_type] + connect_bd_net -net eth_regs_dest_addr [get_bd_pins ETH_regs/dest_addr] [get_bd_pins system_ila_i/probe4] [get_bd_pins eth_frame_packer_i/cfg_dst_mac] + connect_bd_net -net eth_regs_source_addr [get_bd_pins ETH_regs/source_addr] [get_bd_pins system_ila_i/probe5] [get_bd_pins eth_frame_packer_i/cfg_src_mac] + connect_bd_net -net packer_underrun_cnt [get_bd_pins eth_frame_packer_i/underrun_cnt] [get_bd_pins system_ila_i/probe1] [get_bd_pins ETH_regs/tx_frame_underrun_cnt] + connect_bd_net -net probe2_1 [get_bd_pins rx_fifo_overflow] [get_bd_pins system_ila_i/probe2] [get_bd_pins counter_i/CE] + connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins counter_i/SCLR] + connect_bd_net -net prog_full_manual [get_bd_pins ETH_regs/prog_full_manual] [get_bd_pins system_ila_i/probe7] [get_bd_pins eth_flowctrl_tx_i/prog_full_manual] + connect_bd_net -net rst_inv_i_Res [get_bd_pins rst_inv_i/Res] [get_bd_pins cmac_usplus_i/s_axi_sreset] + connect_bd_net -net unpacker_rx_frame_err_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_err_cnt] [get_bd_pins system_ila_i/probe3] [get_bd_pins ETH_regs/rx_frame_err_cnt] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: srl2 +proc create_hier_cell_srl2 { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_srl2() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + + # Create pins + create_bd_pin -dir I -type clk axis_clk + create_bd_pin -dir I -type rst axis_resetn + create_bd_pin -dir I -type clk axil_clk + create_bd_pin -dir I -type rst axil_resetn + create_bd_pin -dir I clk_100 + create_bd_pin -dir I clk_100_reset + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst aresetn_0 + + # Create instance: axis_reg_0_i, and set properties + set axis_reg_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_0_i ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $axis_reg_0_i + + + # Create instance: axis_ss_conv_0_i, and set properties + set axis_ss_conv_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_0_i ] + set_property -dict [list \ + CONFIG.DEFAULT_TLAST {16} \ + CONFIG.M_HAS_TKEEP {0} \ + CONFIG.M_HAS_TLAST {1} \ + CONFIG.M_HAS_TREADY {1} \ + CONFIG.M_HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.M_TDEST_WIDTH {0} \ + CONFIG.M_TID_WIDTH {0} \ + CONFIG.M_TUSER_WIDTH {0} \ + CONFIG.S_HAS_TKEEP {0} \ + CONFIG.S_HAS_TLAST {0} \ + CONFIG.S_HAS_TREADY {1} \ + CONFIG.S_HAS_TSTRB {0} \ + CONFIG.S_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDEST_WIDTH {0} \ + CONFIG.S_TID_WIDTH {0} \ + CONFIG.S_TUSER_WIDTH {0} \ + ] $axis_ss_conv_0_i + + + # Create instance: cmac_rx_fifo_i, and set properties + set cmac_rx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_rx_fifo_i ] + set_property -dict [list \ + CONFIG.FIFO_DEPTH {1024} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.HAS_WR_DATA_COUNT {1} \ + CONFIG.IS_ACLK_ASYNC {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $cmac_rx_fifo_i + + + # Create instance: axis_ss_conv_1_i, and set properties + set axis_ss_conv_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_1_i ] + set_property -dict [list \ + CONFIG.M_HAS_TKEEP {0} \ + CONFIG.M_HAS_TLAST {0} \ + CONFIG.M_HAS_TREADY {1} \ + CONFIG.M_HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.M_TDEST_WIDTH {0} \ + CONFIG.M_TID_WIDTH {0} \ + CONFIG.M_TUSER_WIDTH {0} \ + CONFIG.S_HAS_TKEEP {0} \ + CONFIG.S_HAS_TLAST {1} \ + CONFIG.S_HAS_TREADY {0} \ + CONFIG.S_HAS_TSTRB {0} \ + CONFIG.S_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDEST_WIDTH {0} \ + CONFIG.S_TID_WIDTH {0} \ + CONFIG.S_TUSER_WIDTH {1} \ + ] $axis_ss_conv_1_i + + + # Create instance: axis_reg_1_i, and set properties + set axis_reg_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_1_i ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $axis_reg_1_i + + + # Create instance: cmac_tx_fifo_i, and set properties + set cmac_tx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_tx_fifo_i ] + set_property -dict [list \ + CONFIG.FIFO_DEPTH {32} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.IS_ACLK_ASYNC {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $cmac_tx_fifo_i + + + # Create instance: Ethernet + create_hier_cell_Ethernet $hier_obj Ethernet + + # Create interface connections + connect_bd_intf_net -intf_net Ethernet_M_AXIS [get_bd_intf_pins Ethernet/M_AXIS] [get_bd_intf_pins axis_ss_conv_1_i/S_AXIS] + connect_bd_intf_net -intf_net Ethernet_cmac_gt [get_bd_intf_pins cmac_gt] [get_bd_intf_pins Ethernet/cmac_gt] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins cmac_rx_fifo_i/M_AXIS] [get_bd_intf_pins axis_reg_1_i/S_AXIS] + connect_bd_intf_net -intf_net axis_reg_1_i_M_AXIS [get_bd_intf_pins m_axis] [get_bd_intf_pins axis_reg_1_i/M_AXIS] + connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_reg_0_i/M_AXIS] [get_bd_intf_pins axis_ss_conv_0_i/S_AXIS] + connect_bd_intf_net -intf_net axis_ss_conv_0_i_M_AXIS [get_bd_intf_pins axis_ss_conv_0_i/M_AXIS] [get_bd_intf_pins cmac_tx_fifo_i/S_AXIS] + connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS1 [get_bd_intf_pins axis_ss_conv_1_i/M_AXIS] [get_bd_intf_pins cmac_rx_fifo_i/S_AXIS] + connect_bd_intf_net -intf_net cmac_refclk_1 [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins Ethernet/cmac_refclk] + connect_bd_intf_net -intf_net cmac_tx_fifo_i_M_AXIS [get_bd_intf_pins cmac_tx_fifo_i/M_AXIS] [get_bd_intf_pins Ethernet/S_AXIS] + connect_bd_intf_net -intf_net s_axil_1 [get_bd_intf_pins s_axil] [get_bd_intf_pins Ethernet/S_AXIL] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins axis_reg_0_i/S_AXIS] + + # Create port connections + connect_bd_net -net Ethernet_axis_aclk [get_bd_pins Ethernet/axis_aclk] [get_bd_pins axis_ss_conv_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/s_axis_aclk] [get_bd_pins cmac_tx_fifo_i/m_axis_aclk] + connect_bd_net -net Ethernet_axis_aresetn [get_bd_pins Ethernet/axis_aresetn] [get_bd_pins cmac_rx_fifo_i/s_axis_aresetn] [get_bd_pins axis_ss_conv_1_i/aresetn] + connect_bd_net -net Net [get_bd_pins m_axis_aclk] [get_bd_pins axis_reg_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/m_axis_aclk] + connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins axis_reg_1_i/aresetn] + connect_bd_net -net clk_100_1 [get_bd_pins clk_100] [get_bd_pins Ethernet/clk_100] + connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset] [get_bd_pins Ethernet/clk_100_reset] + connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins cmac_rx_fifo_i/axis_wr_data_count] [get_bd_pins Ethernet/rx_fifo_wr_data_cnt] + connect_bd_net -net cmac_rx_overflow [get_bd_pins axis_ss_conv_1_i/transfer_dropped] [get_bd_pins Ethernet/rx_fifo_overflow] + connect_bd_net -net s_axi_sreset_1 [get_bd_pins axil_resetn] [get_bd_pins Ethernet/axil_resetn] + connect_bd_net -net s_axilite_dsp_clk [get_bd_pins axil_clk] [get_bd_pins Ethernet/axil_clk] + connect_bd_net -net s_axis_dsp_clk [get_bd_pins axis_clk] [get_bd_pins axis_reg_0_i/aclk] [get_bd_pins axis_ss_conv_0_i/aclk] [get_bd_pins cmac_tx_fifo_i/s_axis_aclk] + connect_bd_net -net s_axis_dsp_resetn [get_bd_pins axis_resetn] [get_bd_pins axis_reg_0_i/aresetn] [get_bd_pins axis_ss_conv_0_i/aresetn] [get_bd_pins cmac_tx_fifo_i/s_axis_aresetn] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: hier_0 +proc create_hier_cell_hier_0 { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_hier_0() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0 + + + # Create pins + create_bd_pin -dir I -type clk axis_clk_0 + create_bd_pin -dir I -type rst axis_resetn_0 + create_bd_pin -dir I -type clk axil_clk_0 + create_bd_pin -dir I -type rst axil_resetn_0 + create_bd_pin -dir I clk_100_0 + create_bd_pin -dir I clk_100_reset_0 + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst aresetn_0 + + # Create instance: srl2 + create_hier_cell_srl2 $hier_obj srl2 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins srl2/cmac_gt] [get_bd_intf_pins cmac_gt_0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins srl2/m_axis] [get_bd_intf_pins m_axis_0] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins srl2/s_axil] [get_bd_intf_pins s_axil_0] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins srl2/s_axis] [get_bd_intf_pins s_axis_0] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins srl2/cmac_refclk] [get_bd_intf_pins cmac_refclk_0] + + # Create port connections + connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins srl2/aresetn_0] + connect_bd_net -net axil_clk_1 [get_bd_pins axil_clk_0] [get_bd_pins srl2/axil_clk] + connect_bd_net -net axil_resetn_1 [get_bd_pins axil_resetn_0] [get_bd_pins srl2/axil_resetn] + connect_bd_net -net axis_clk_1 [get_bd_pins axis_clk_0] [get_bd_pins srl2/axis_clk] + connect_bd_net -net axis_resetn_1 [get_bd_pins axis_resetn_0] [get_bd_pins srl2/axis_resetn] + connect_bd_net -net clk_100_1 [get_bd_pins clk_100_0] [get_bd_pins srl2/clk_100] + connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset_0] [get_bd_pins srl2/clk_100_reset] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins srl2/m_axis_aclk] + + # Restore current instance + current_bd_instance $oldCurInst +} + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set cmac_gt_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0 ] + + set m_axis [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {375000000} \ + ] $m_axis + + set s_axil_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axil_0 + + set s_axis [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {375000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $s_axis + + set cmac_refclk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {156250000} \ + ] $cmac_refclk_0 + + + # Create ports + set s_axis_clk [ create_bd_port -dir I -type clk -freq_hz 375000000 s_axis_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {s_axis} \ + CONFIG.ASSOCIATED_RESET {s_axis_aresetn} \ + ] $s_axis_clk + set s_axis_aresetn [ create_bd_port -dir I -type rst s_axis_aresetn ] + set axil_clk_0 [ create_bd_port -dir I -type clk axil_clk_0 ] + set axil_resetn_0 [ create_bd_port -dir I -type rst axil_resetn_0 ] + set clk_100_0 [ create_bd_port -dir I clk_100_0 ] + set clk_100_reset_0 [ create_bd_port -dir I clk_100_reset_0 ] + set m_axis_aclk [ create_bd_port -dir I -type clk -freq_hz 375000000 m_axis_aclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axis} \ + CONFIG.ASSOCIATED_RESET {m_axis_aresetn} \ + CONFIG.CLK_DOMAIN {raw_eth_axis_clk_0} \ + ] $m_axis_aclk + set m_axis_aresetn [ create_bd_port -dir I -type rst m_axis_aresetn ] + + # Create instance: hier_0 + create_hier_cell_hier_0 [current_bd_instance .] hier_0 + + # Create interface connections + connect_bd_intf_net -intf_net cmac_refclk_0_1 [get_bd_intf_ports cmac_refclk_0] [get_bd_intf_pins hier_0/cmac_refclk_0] + connect_bd_intf_net -intf_net hier_0_cmac_gt_0 [get_bd_intf_ports cmac_gt_0] [get_bd_intf_pins hier_0/cmac_gt_0] + connect_bd_intf_net -intf_net hier_0_m_axis_0 [get_bd_intf_ports m_axis] [get_bd_intf_pins hier_0/m_axis_0] + connect_bd_intf_net -intf_net s_axil_0_1 [get_bd_intf_ports s_axil_0] [get_bd_intf_pins hier_0/s_axil_0] + connect_bd_intf_net -intf_net s_axis_0_1 [get_bd_intf_ports s_axis] [get_bd_intf_pins hier_0/s_axis_0] + + # Create port connections + connect_bd_net -net aresetn_0_1 [get_bd_ports m_axis_aresetn] [get_bd_pins hier_0/aresetn_0] + connect_bd_net -net axil_clk_0_1 [get_bd_ports axil_clk_0] [get_bd_pins hier_0/axil_clk_0] + connect_bd_net -net axil_resetn_0_1 [get_bd_ports axil_resetn_0] [get_bd_pins hier_0/axil_resetn_0] + connect_bd_net -net axis_clk_0_1 [get_bd_ports s_axis_clk] [get_bd_pins hier_0/axis_clk_0] + connect_bd_net -net axis_resetn_0_1 [get_bd_ports s_axis_aresetn] [get_bd_pins hier_0/axis_resetn_0] + connect_bd_net -net clk_100_0_1 [get_bd_ports clk_100_0] [get_bd_pins hier_0/clk_100_0] + connect_bd_net -net clk_100_reset_0_1 [get_bd_ports clk_100_reset_0] [get_bd_pins hier_0/clk_100_reset_0] + connect_bd_net -net m_axis_aclk_1 [get_bd_ports m_axis_aclk] [get_bd_pins hier_0/m_axis_aclk] + + # Create address segments + assign_bd_address -offset 0x84000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/ETH_regs/axi_regs_32_0/S_AXI/reg0] -force + assign_bd_address -offset 0x84010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/cmac_usplus_i/s_axi/Reg] -force + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-456,-97", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port cmac_gt_0 -pg 1 -lvl 2 -x 320 -y 150 -defaultsOSRD +preplace port m_axis -pg 1 -lvl 2 -x 320 -y 170 -defaultsOSRD +preplace port s_axil_0 -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD +preplace port s_axis -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD +preplace port cmac_refclk_0 -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD +preplace port port-id_s_axis_clk -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD +preplace port port-id_s_axis_aresetn -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD +preplace port port-id_axil_clk_0 -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD +preplace port port-id_axil_resetn_0 -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD +preplace port port-id_clk_100_0 -pg 1 -lvl 0 -x 0 -y 200 -defaultsOSRD +preplace port port-id_clk_100_reset_0 -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD +preplace port port-id_m_axis_aclk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD +preplace port port-id_m_axis_aresetn -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD +preplace inst hier_0 -pg 1 -lvl 1 -x 160 -y 160 -defaultsOSRD +preplace netloc aresetn_0_1 1 0 1 NJ 260 +preplace netloc axil_clk_0_1 1 0 1 NJ 160 +preplace netloc axil_resetn_0_1 1 0 1 NJ 180 +preplace netloc axis_clk_0_1 1 0 1 NJ 120 +preplace netloc axis_resetn_0_1 1 0 1 NJ 140 +preplace netloc clk_100_0_1 1 0 1 NJ 200 +preplace netloc clk_100_reset_0_1 1 0 1 NJ 220 +preplace netloc m_axis_aclk_1 1 0 1 NJ 240 +preplace netloc cmac_refclk_0_1 1 0 1 NJ 100 +preplace netloc hier_0_cmac_gt_0 1 1 1 NJ 150 +preplace netloc hier_0_m_axis_0 1 1 1 NJ 170 +preplace netloc s_axil_0_1 1 0 1 NJ 60 +preplace netloc s_axis_0_1 1 0 1 NJ 80 +levelinfo -pg 1 0 160 320 +pagesize -pg 1 -db -bbox -sgen -170 0 450 310 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_raw_eth() + +cr_bd_raw_eth "" +set_property REGISTERED_WITH_MANAGER "1" [get_files raw_eth.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files raw_eth.bd ] + # Proc to create BD iq_240b_to_512b @@ -2242,6 +3351,13 @@ proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { CONFIG.PROTOCOL {AXI4LITE} \ ] $M12_AXI_0 + set M13_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M13_AXI_0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $M13_AXI_0 + # Create ports set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ] @@ -2312,7 +3428,7 @@ proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { set clk_250_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst clk_250_aresetn_out ] set sys_cpu_clk_out [ create_bd_port -dir O -type clk sys_cpu_clk_out ] set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {M11_AXI_0:M12_AXI_0} \ + CONFIG.ASSOCIATED_BUSIF {M11_AXI_0:M12_AXI_0:M13_AXI_0} \ ] $sys_cpu_clk_out set sys_cpu_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst sys_cpu_aresetn_out ] set pl_clk3_0 [ create_bd_port -dir O -type clk pl_clk3_0 ] @@ -3406,7 +4522,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 # Create instance: axi_cpu_interconnect, and set properties set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ] set_property -dict [list \ - CONFIG.NUM_MI {13} \ + CONFIG.NUM_MI {14} \ CONFIG.NUM_SI {1} \ ] $axi_cpu_interconnect @@ -3660,6 +4776,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_M11_AXI [get_bd_intf_ports M11_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] connect_bd_intf_net -intf_net axi_cpu_interconnect_M12_AXI [get_bd_intf_ports M12_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M13_AXI [get_bd_intf_ports M13_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD] connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD] connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD] @@ -3822,6 +4939,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 # Create address segments assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M11_AXI_0/Reg] -force assign_bd_address -offset 0x83000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M12_AXI_0/Reg] -force + assign_bd_address -offset 0x84000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M13_AXI_0/Reg] -force assign_bd_address -offset 0x9C420000 -range 0x00001000 -with_name SEG_data_axi_mxfe_rx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force assign_bd_address -offset 0x84A90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_rx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force assign_bd_address -offset 0x84A60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_rx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force @@ -3842,6 +4960,297 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH] exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH] + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.04233", + "Default View_TopLeft":"4252,745", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port util_mxfe_upack_s_axis -pg 1 -lvl 0 -x -10 -y 780 -defaultsOSRD +preplace port mxfe_tx_data_offload_m_axis -pg 1 -lvl 11 -x 4990 -y 2470 -defaultsOSRD +preplace port M11_AXI_0 -pg 1 -lvl 11 -x 4990 -y 2230 -defaultsOSRD +preplace port M12_AXI_0 -pg 1 -lvl 11 -x 4990 -y 2210 -defaultsOSRD +preplace port M13_AXI_0 -pg 1 -lvl 11 -x 4990 -y 1890 -defaultsOSRD +preplace port port-id_spi0_sclk -pg 1 -lvl 11 -x 4990 -y 2700 -defaultsOSRD +preplace port port-id_spi0_mosi -pg 1 -lvl 11 -x 4990 -y 2720 -defaultsOSRD +preplace port port-id_spi0_miso -pg 1 -lvl 0 -x -10 -y 3280 -defaultsOSRD +preplace port port-id_spi1_sclk -pg 1 -lvl 11 -x 4990 -y 3120 -defaultsOSRD +preplace port port-id_spi1_mosi -pg 1 -lvl 11 -x 4990 -y 2900 -defaultsOSRD +preplace port port-id_spi1_miso -pg 1 -lvl 0 -x -10 -y 3300 -defaultsOSRD +preplace port port-id_rx_device_clk -pg 1 -lvl 0 -x -10 -y 2720 -defaultsOSRD +preplace port port-id_tx_device_clk -pg 1 -lvl 0 -x -10 -y 800 -defaultsOSRD +preplace port port-id_ref_clk_q0 -pg 1 -lvl 0 -x -10 -y 1510 -defaultsOSRD +preplace port port-id_ref_clk_q1 -pg 1 -lvl 0 -x -10 -y 20 -defaultsOSRD +preplace port port-id_rx_sysref_0 -pg 1 -lvl 0 -x -10 -y 1490 -defaultsOSRD +preplace port port-id_rx_data_0_p -pg 1 -lvl 0 -x -10 -y 1530 -defaultsOSRD +preplace port port-id_rx_data_0_n -pg 1 -lvl 0 -x -10 -y 1550 -defaultsOSRD +preplace port port-id_rx_data_1_p -pg 1 -lvl 0 -x -10 -y 1570 -defaultsOSRD +preplace port port-id_rx_data_1_n -pg 1 -lvl 0 -x -10 -y 1590 -defaultsOSRD +preplace port port-id_rx_data_2_p -pg 1 -lvl 0 -x -10 -y 2100 -defaultsOSRD +preplace port port-id_rx_data_2_n -pg 1 -lvl 0 -x -10 -y 2080 -defaultsOSRD +preplace port port-id_rx_data_3_p -pg 1 -lvl 0 -x -10 -y 2120 -defaultsOSRD +preplace port port-id_rx_data_3_n -pg 1 -lvl 0 -x -10 -y 2160 -defaultsOSRD +preplace port port-id_tx_sysref_0 -pg 1 -lvl 0 -x -10 -y 2140 -defaultsOSRD +preplace port port-id_tx_data_0_p -pg 1 -lvl 11 -x 4990 -y 1360 -defaultsOSRD +preplace port port-id_tx_data_0_n -pg 1 -lvl 11 -x 4990 -y 1340 -defaultsOSRD +preplace port port-id_tx_data_1_p -pg 1 -lvl 11 -x 4990 -y 1660 -defaultsOSRD +preplace port port-id_tx_data_1_n -pg 1 -lvl 11 -x 4990 -y 1680 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util_mxfe_xcvr_tx_3_n 1 9 2 NJ 1800 NJ +preplace netloc util_mxfe_xcvr_tx_3_p 1 9 2 NJ 1780 NJ +preplace netloc util_mxfe_xcvr_tx_out_clk_0 1 7 3 3480 1390 3920 930 4360 +preplace netloc axi_cpu_interconnect_M00_AXI 1 6 1 2610 1630n +preplace netloc axi_cpu_interconnect_M01_AXI 1 2 5 660 1060 NJ 1060 NJ 1060 NJ 1060 2580 +preplace netloc axi_cpu_interconnect_M02_AXI 1 6 1 2650 220n +preplace netloc axi_cpu_interconnect_M03_AXI 1 6 4 2850J 1310 NJ 1310 3790J 1090 4410 +preplace netloc axi_cpu_interconnect_M04_AXI 1 2 5 650 1510 NJ 1510 NJ 1510 NJ 1510 2570 +preplace netloc axi_cpu_interconnect_M05_AXI 1 1 6 260 1520 NJ 1520 NJ 1520 NJ 1520 NJ 1520 2590 +preplace netloc axi_cpu_interconnect_M06_AXI 1 6 2 2860J 1630 3300 +preplace netloc axi_cpu_interconnect_M07_AXI 1 6 1 2710 740n +preplace netloc axi_cpu_interconnect_M08_AXI 1 6 2 NJ 1790 3460 +preplace netloc axi_cpu_interconnect_M09_AXI 1 2 5 660 1530 NJ 1530 NJ 1530 NJ 1530 2600 +preplace netloc axi_cpu_interconnect_M10_AXI 1 6 3 2870 1680 NJ 1680 3880J +preplace netloc axi_cpu_interconnect_M11_AXI 1 6 5 2780J 1210 3400J 940 NJ 940 NJ 940 4970J +preplace netloc axi_cpu_interconnect_M12_AXI 1 6 5 NJ 1870 3410J 1960 3840J 2210 NJ 2210 NJ +preplace netloc axi_cpu_interconnect_M13_AXI 1 6 5 NJ 1890 3360J 1970 3820J 2170 4430J 1890 NJ +preplace netloc axi_hp0_interconnect_M00_AXI 1 4 1 1420 2560n +preplace netloc axi_hp1_interconnect_M00_AXI 1 4 1 1390 2740n +preplace netloc axi_hp2_interconnect_M00_AXI 1 4 1 1440 2810n +preplace netloc axi_mxfe_rx_dma_m_dest_axi 1 3 1 1020 2680n +preplace netloc axi_mxfe_rx_xcvr_m_axi 1 3 1 1070 1230n +preplace netloc axi_mxfe_rx_xcvr_up_ch_0 1 3 6 980J 1080 NJ 1080 NJ 1080 2840J 1110 NJ 1110 3980 +preplace netloc axi_mxfe_rx_xcvr_up_ch_1 1 3 6 NJ 1310 NJ 1310 NJ 1310 2730J 1300 NJ 1300 3820 +preplace netloc axi_mxfe_rx_xcvr_up_ch_2 1 3 6 1030J 1090 NJ 1090 NJ 1090 2830J 1120 NJ 1120 3970 +preplace netloc axi_mxfe_rx_xcvr_up_ch_3 1 3 6 1040J 1100 NJ 1100 NJ 1100 2820J 1130 NJ 1130 3960 +preplace netloc axi_mxfe_rx_xcvr_up_es_0 1 3 6 NJ 1250 NJ 1250 2180J 1270 NJ 1270 3450J 1290 3800 +preplace netloc axi_mxfe_rx_xcvr_up_es_1 1 3 6 NJ 1290 NJ 1290 2150J 1320 NJ 1320 NJ 1320 3830 +preplace netloc axi_mxfe_rx_xcvr_up_es_2 1 3 6 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 N +preplace netloc axi_mxfe_rx_xcvr_up_es_3 1 3 6 NJ 1370 NJ 1370 NJ 1370 2730J 1360 NJ 1360 3950 +preplace netloc axi_mxfe_tx_dma_m_src_axi 1 3 1 1000 2440n +preplace netloc axi_mxfe_tx_jesd_tx_phy0 1 8 1 3860 1230n +preplace netloc axi_mxfe_tx_jesd_tx_phy1 1 8 1 3900 1310n +preplace netloc axi_mxfe_tx_jesd_tx_phy2 1 8 1 3930 1390n +preplace netloc axi_mxfe_tx_jesd_tx_phy3 1 8 1 3950 1470n +preplace netloc axi_mxfe_tx_xcvr_up_ch_0 1 8 1 3840 1210n +preplace netloc axi_mxfe_tx_xcvr_up_ch_1 1 8 1 3850 1290n +preplace netloc axi_mxfe_tx_xcvr_up_ch_2 1 8 1 3870 1370n +preplace netloc axi_mxfe_tx_xcvr_up_ch_3 1 8 1 3880 1450n +preplace netloc axi_mxfe_tx_xcvr_up_cm_0 1 8 1 3810 1150n +preplace netloc mxfe_rx_data_offload_m_axis 1 2 1 600 2600n +preplace netloc mxfe_tx_data_offload_m_axis 1 9 2 NJ 2470 NJ +preplace netloc s_axis_1 1 3 6 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 3940 +preplace netloc sys_ps8_M_AXI_HPM0_LPD 1 5 1 2130 1740n +preplace netloc tx_mxfe_tpl_core_link 1 7 1 3410 700n +preplace netloc util_mxfe_upack_s_axis 1 0 6 NJ 780 NJ 780 NJ 780 NJ 780 NJ 780 NJ +preplace netloc util_mxfe_xcvr_rx_0 1 9 1 N 1440 +preplace netloc util_mxfe_xcvr_rx_1 1 9 1 N 1460 +preplace netloc util_mxfe_xcvr_rx_2 1 9 1 N 1480 +preplace netloc util_mxfe_xcvr_rx_3 1 9 1 N 1500 +levelinfo -pg 1 -10 100 440 820 1250 1770 2420 3070 3610 4180 4710 4990 +pagesize -pg 1 -db -bbox -sgen -230 0 5270 3740 +" +} # Restore current instance current_bd_instance $oldCurInst @@ -3856,6 +5265,15 @@ cr_bd_system "" set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ] set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ] +#call make_wrapper to create wrapper files +if { [get_property IS_LOCKED [ get_files -norecurse [list raw_eth.bd]] ] == 1 } { + import_files -fileset sources_1 [file normalize "${origin_dir}/alinx_z19_ad9081/alinx_z19_ad9081.gen/sources_1/bd/raw_eth/hdl/raw_eth_wrapper.v" ] +} else { + set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse [list raw_eth.bd]] -top] + add_files -norecurse -fileset sources_1 $wrapper_path +} + + set idrFlowPropertiesConstraints "" catch { set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints] @@ -4106,7 +5524,6 @@ set_property -name "options.warn_on_violation" -value "1" -objects $obj } set obj [get_runs impl_1] -set_property -name "needs_refresh" -value "1" -objects $obj set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj @@ -4593,6 +6010,7 @@ set_property -name "options.warn_on_violation" -value "1" -objects $obj } set obj [get_runs impl_3] +set_property -name "needs_refresh" -value "1" -objects $obj set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj set_property -name "strategy" -value "Performance_Auto_1" -objects $obj set_property -name "steps.opt_design.args.directive" -value "Explore" -objects $obj @@ -5844,7 +7262,7 @@ set_property -name "steps.write_bitstream.args.readback_file" -value "0" -object set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj # set the current impl run -current_run -implementation [get_runs impl_1] +current_run -implementation [get_runs impl_3] catch { if { $idrFlowPropertiesConstraints != {} } { set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints diff --git a/ip_repo/Si5332/src/si5332_wrapper.vhd b/ip_repo/Si5332/src/si5332_wrapper.vhd index 8ed7d03..860a8ba 100644 --- a/ip_repo/Si5332/src/si5332_wrapper.vhd +++ b/ip_repo/Si5332/src/si5332_wrapper.vhd @@ -44,21 +44,6 @@ architecture imp of si5332_wrapper is signal man_clk_gen_en : std_logic := '0'; signal man_clk_gen_cfg_reset : std_logic := '0'; - - signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal qsfp2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal qsfp2_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp2_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal qsfp3_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal qsfp3_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp3_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - - begin @@ -105,63 +90,4 @@ begin reset_in => clk_100_areset_in ); - --- i_vio_3 : entity work.vio_3 --- port map ( --- clk => clk_100_in, --- probe_in0(0) => i2c_mux_access_ok, -- 1 --- probe_in1(0) => si5341_access_ok, -- 1 --- probe_in2(0) => si5341_config_done, -- 1 --- probe_in3(0) => si5341_config_error, -- 1 --- probe_in4 => clk_100_freq_r, -- 32 --- probe_in5 => clk_100_cnt_r, -- 32 --- probe_in6 => qsfp2_freq_r, -- 32 --- probe_in7 => qsfp2_cnt_r, -- 32 --- probe_in8 => qsfp3_freq_r, -- 32 --- probe_in9 => qsfp3_cnt_r, -- 32 --- --- probe_out0(0) => man_clk_gen_en, -- 1 --- probe_out1(0) => man_clk_gen_cfg_reset -- 1 --- ); - - process(clk_100_in) - begin - if (rising_edge(clk_100_in)) then - clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms; - if (clk_100_tick_1ms_r(0 to 1) = "01") then - clk_100_freq_r <= clk_100_cnt_r; - clk_100_cnt_r <= (others => '0'); - else - clk_100_cnt_r <= clk_100_cnt_r + 1; - end if; - end if; - end process; - - process(qsfp2_clk_in) - begin - if (rising_edge(qsfp2_clk_in)) then - qsfp2_tick_1ms_r <= qsfp2_tick_1ms_r(1 to 2) & tick_1ms; - if (qsfp2_tick_1ms_r(0 to 1) = "01") then - qsfp2_freq_r <= qsfp2_cnt_r; - qsfp2_cnt_r <= (others => '0'); - else - qsfp2_cnt_r <= qsfp2_cnt_r + 1; - end if; - end if; - end process; - - process(qsfp3_clk_in) - begin - if (rising_edge(qsfp3_clk_in)) then - qsfp3_tick_1ms_r <= qsfp3_tick_1ms_r(1 to 2) & tick_1ms; - if (qsfp3_tick_1ms_r(0 to 1) = "01") then - qsfp3_freq_r <= qsfp3_cnt_r; - qsfp3_cnt_r <= (others => '0'); - else - qsfp3_cnt_r <= qsfp3_cnt_r + 1; - end if; - end if; - end process; - - end architecture imp; diff --git a/ip_repo/axi_regs_32/axi_regs_32.vhd b/ip_repo/axi_regs_32/axi_regs_32.vhd new file mode 100644 index 0000000..babb1f5 --- /dev/null +++ b/ip_repo/axi_regs_32/axi_regs_32.vhd @@ -0,0 +1,839 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_regs_32 is + generic ( + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 7 + ); + port ( + reg0_out : out std_logic_vector(31 downto 0); + reg1_out : out std_logic_vector(31 downto 0); + reg2_out : out std_logic_vector(31 downto 0); + reg3_out : out std_logic_vector(31 downto 0); + reg4_out : out std_logic_vector(31 downto 0); + reg5_out : out std_logic_vector(31 downto 0); + reg6_out : out std_logic_vector(31 downto 0); + reg7_out : out std_logic_vector(31 downto 0); + reg8_out : out std_logic_vector(31 downto 0); + reg9_out : out std_logic_vector(31 downto 0); + reg10_out : out std_logic_vector(31 downto 0); + reg11_out : out std_logic_vector(31 downto 0); + reg12_out : out std_logic_vector(31 downto 0); + reg13_out : out std_logic_vector(31 downto 0); + reg14_out : out std_logic_vector(31 downto 0); + reg15_out : out std_logic_vector(31 downto 0); + reg16_out : out std_logic_vector(31 downto 0); + reg17_out : out std_logic_vector(31 downto 0); + reg18_out : out std_logic_vector(31 downto 0); + reg19_out : out std_logic_vector(31 downto 0); + reg20_out : out std_logic_vector(31 downto 0); + reg21_out : out std_logic_vector(31 downto 0); + reg22_out : out std_logic_vector(31 downto 0); + reg23_out : out std_logic_vector(31 downto 0); + reg24_out : out std_logic_vector(31 downto 0); + reg25_out : out std_logic_vector(31 downto 0); + reg26_out : out std_logic_vector(31 downto 0); + reg27_out : out std_logic_vector(31 downto 0); + reg28_out : out std_logic_vector(31 downto 0); + reg29_out : out std_logic_vector(31 downto 0); + reg30_out : out std_logic_vector(31 downto 0); + reg31_out : out std_logic_vector(31 downto 0); + + reg0_in : in std_logic_vector(31 downto 0); + reg1_in : in std_logic_vector(31 downto 0); + reg2_in : in std_logic_vector(31 downto 0); + reg3_in : in std_logic_vector(31 downto 0); + reg4_in : in std_logic_vector(31 downto 0); + reg5_in : in std_logic_vector(31 downto 0); + reg6_in : in std_logic_vector(31 downto 0); + reg7_in : in std_logic_vector(31 downto 0); + reg8_in : in std_logic_vector(31 downto 0); + reg9_in : in std_logic_vector(31 downto 0); + reg10_in : in std_logic_vector(31 downto 0); + reg11_in : in std_logic_vector(31 downto 0); + reg12_in : in std_logic_vector(31 downto 0); + reg13_in : in std_logic_vector(31 downto 0); + reg14_in : in std_logic_vector(31 downto 0); + reg15_in : in std_logic_vector(31 downto 0); + reg16_in : in std_logic_vector(31 downto 0); + reg17_in : in std_logic_vector(31 downto 0); + reg18_in : in std_logic_vector(31 downto 0); + reg19_in : in std_logic_vector(31 downto 0); + reg20_in : in std_logic_vector(31 downto 0); + reg21_in : in std_logic_vector(31 downto 0); + reg22_in : in std_logic_vector(31 downto 0); + reg23_in : in std_logic_vector(31 downto 0); + reg24_in : in std_logic_vector(31 downto 0); + reg25_in : in std_logic_vector(31 downto 0); + reg26_in : in std_logic_vector(31 downto 0); + reg27_in : in std_logic_vector(31 downto 0); + reg28_in : in std_logic_vector(31 downto 0); + reg29_in : in std_logic_vector(31 downto 0); + reg30_in : in std_logic_vector(31 downto 0); + reg31_in : in std_logic_vector(31 downto 0); + + -- Global Clock Signal + S_AXI_ACLK : in std_logic; + -- Global Reset Signal. This Signal is Active LOW + S_AXI_ARESETN : in std_logic; + -- Write address (issued by master, acceped by Slave) + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Write channel Protection type. This signal indicates the + -- privilege and security level of the transaction, and whether + -- the transaction is a data access or an instruction access. + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + -- Write address valid. This signal indicates that the master signaling + -- valid write address and control information. + S_AXI_AWVALID : in std_logic; + -- Write address ready. This signal indicates that the slave is ready + -- to accept an address and associated control signals. + S_AXI_AWREADY : out std_logic; + -- Write data (issued by master, acceped by Slave) + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Write strobes. This signal indicates which byte lanes hold + -- valid data. There is one write strobe bit for each eight + -- bits of the write data bus. + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + -- Write valid. This signal indicates that valid write + -- data and strobes are available. + S_AXI_WVALID : in std_logic; + -- Write ready. This signal indicates that the slave + -- can accept the write data. + S_AXI_WREADY : out std_logic; + -- Write response. This signal indicates the status + -- of the write transaction. + S_AXI_BRESP : out std_logic_vector(1 downto 0); + -- Write response valid. This signal indicates that the channel + -- is signaling a valid write response. + S_AXI_BVALID : out std_logic; + -- Response ready. This signal indicates that the master + -- can accept a write response. + S_AXI_BREADY : in std_logic; + -- Read address (issued by master, acceped by Slave) + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Protection type. This signal indicates the privilege + -- and security level of the transaction, and whether the + -- transaction is a data access or an instruction access. + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + -- Read address valid. This signal indicates that the channel + -- is signaling valid read address and control information. + S_AXI_ARVALID : in std_logic; + -- Read address ready. This signal indicates that the slave is + -- ready to accept an address and associated control signals. + S_AXI_ARREADY : out std_logic; + -- Read data (issued by slave) + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Read response. This signal indicates the status of the + -- read transfer. + S_AXI_RRESP : out std_logic_vector(1 downto 0); + -- Read valid. This signal indicates that the channel is + -- signaling the required read data. + S_AXI_RVALID : out std_logic; + -- Read ready. This signal indicates that the master can + -- accept the read data and response information. + S_AXI_RREADY : in std_logic + ); +end axi_regs_32; + +architecture arch_imp of axi_regs_32 is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 4; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 32 + signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + signal aw_en : std_logic; + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + aw_en <= '1'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + aw_en <= '0'; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then + aw_en <= '1'; + axi_awready <= '0'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg0 <= (others => '0'); + slv_reg1 <= (others => '0'); + slv_reg2 <= (others => '0'); + slv_reg3 <= (others => '0'); + slv_reg4 <= (others => '0'); + slv_reg5 <= (others => '0'); + slv_reg6 <= (others => '0'); + slv_reg7 <= (others => '0'); + slv_reg8 <= (others => '0'); + slv_reg9 <= (others => '0'); + slv_reg10 <= (others => '0'); + slv_reg11 <= (others => '0'); + slv_reg12 <= (others => '0'); + slv_reg13 <= (others => '0'); + slv_reg14 <= (others => '0'); + slv_reg15 <= (others => '0'); + slv_reg16 <= (others => '0'); + slv_reg17 <= (others => '0'); + slv_reg18 <= (others => '0'); + slv_reg19 <= (others => '0'); + slv_reg20 <= (others => '0'); + slv_reg21 <= (others => '0'); + slv_reg22 <= (others => '0'); + slv_reg23 <= (others => '0'); + slv_reg24 <= (others => '0'); + slv_reg25 <= (others => '0'); + slv_reg26 <= (others => '0'); + slv_reg27 <= (others => '0'); + slv_reg28 <= (others => '0'); + slv_reg29 <= (others => '0'); + slv_reg30 <= (others => '0'); + slv_reg31 <= (others => '0'); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"00000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 0 + slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"00001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 1 + slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"00010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 2 + slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"00011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 3 + slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"00100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 4 + slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"00101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 5 + slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"00110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 6 + slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"00111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 7 + slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 8 + slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 9 + slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 10 + slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 11 + slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 12 + slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 13 + slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 14 + slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"01111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 15 + slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 16 + slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 17 + slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 18 + slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 19 + slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 20 + slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 21 + slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 22 + slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 23 + slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 24 + slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 25 + slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 26 + slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 27 + slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 28 + slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 29 + slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 30 + slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 31 + slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg0 <= slv_reg0; + slv_reg1 <= slv_reg1; + slv_reg2 <= slv_reg2; + slv_reg3 <= slv_reg3; + slv_reg4 <= slv_reg4; + slv_reg5 <= slv_reg5; + slv_reg6 <= slv_reg6; + slv_reg7 <= slv_reg7; + slv_reg8 <= slv_reg8; + slv_reg9 <= slv_reg9; + slv_reg10 <= slv_reg10; + slv_reg11 <= slv_reg11; + slv_reg12 <= slv_reg12; + slv_reg13 <= slv_reg13; + slv_reg14 <= slv_reg14; + slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (reg0_in, reg1_in, reg2_in, reg3_in, reg4_in, reg5_in, reg6_in, reg7_in, reg8_in, reg9_in, reg10_in, reg11_in, reg12_in, reg13_in, reg14_in, reg15_in, reg16_in, reg17_in, reg18_in, reg19_in, reg20_in, reg21_in, reg22_in, reg23_in, reg24_in, reg25_in, reg26_in, reg27_in, reg28_in, reg29_in, reg30_in, reg31_in, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"00000" => + reg_data_out <= reg0_in; + when b"00001" => + reg_data_out <= reg1_in; + when b"00010" => + reg_data_out <= reg2_in; + when b"00011" => + reg_data_out <= reg3_in; + when b"00100" => + reg_data_out <= reg4_in; + when b"00101" => + reg_data_out <= reg5_in; + when b"00110" => + reg_data_out <= reg6_in; + when b"00111" => + reg_data_out <= reg7_in; + when b"01000" => + reg_data_out <= reg8_in; + when b"01001" => + reg_data_out <= reg9_in; + when b"01010" => + reg_data_out <= reg10_in; + when b"01011" => + reg_data_out <= reg11_in; + when b"01100" => + reg_data_out <= reg12_in; + when b"01101" => + reg_data_out <= reg13_in; + when b"01110" => + reg_data_out <= reg14_in; + when b"01111" => + reg_data_out <= reg15_in; + when b"10000" => + reg_data_out <= reg16_in; + when b"10001" => + reg_data_out <= reg17_in; + when b"10010" => + reg_data_out <= reg18_in; + when b"10011" => + reg_data_out <= reg19_in; + when b"10100" => + reg_data_out <= reg20_in; + when b"10101" => + reg_data_out <= reg21_in; + when b"10110" => + reg_data_out <= reg22_in; + when b"10111" => + reg_data_out <= reg23_in; + when b"11000" => + reg_data_out <= reg24_in; + when b"11001" => + reg_data_out <= reg25_in; + when b"11010" => + reg_data_out <= reg26_in; + when b"11011" => + reg_data_out <= reg27_in; + when b"11100" => + reg_data_out <= reg28_in; + when b"11101" => + reg_data_out <= reg29_in; + when b"11110" => + reg_data_out <= reg30_in; + when b"11111" => + reg_data_out <= reg31_in; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + reg0_out <= slv_reg0; + reg1_out <= slv_reg1; + reg2_out <= slv_reg2; + reg3_out <= slv_reg3; + reg4_out <= slv_reg4; + reg5_out <= slv_reg5; + reg6_out <= slv_reg6; + reg7_out <= slv_reg7; + reg8_out <= slv_reg8; + reg9_out <= slv_reg9; + reg10_out <= slv_reg10; + reg11_out <= slv_reg11; + reg12_out <= slv_reg12; + reg13_out <= slv_reg13; + reg14_out <= slv_reg14; + reg15_out <= slv_reg15; + reg16_out <= slv_reg16; + reg17_out <= slv_reg17; + reg18_out <= slv_reg18; + reg19_out <= slv_reg19; + reg20_out <= slv_reg20; + reg21_out <= slv_reg21; + reg22_out <= slv_reg22; + reg23_out <= slv_reg23; + reg24_out <= slv_reg24; + reg25_out <= slv_reg25; + reg26_out <= slv_reg26; + reg27_out <= slv_reg27; + reg28_out <= slv_reg28; + reg29_out <= slv_reg29; + reg30_out <= slv_reg30; + reg31_out <= slv_reg31; + +end arch_imp; diff --git a/ip_repo/axi_regs_32/axi_regs_32_ooc.xdc b/ip_repo/axi_regs_32/axi_regs_32_ooc.xdc new file mode 100644 index 0000000..e15d8ab --- /dev/null +++ b/ip_repo/axi_regs_32/axi_regs_32_ooc.xdc @@ -0,0 +1,10 @@ + + + + +create_clock -period 10.000 -name S_AXI_ACLK [get_ports S_AXI_ACLK]; + + + + + \ No newline at end of file diff --git a/ip_repo/axi_regs_32/component.xml b/ip_repo/axi_regs_32/component.xml new file mode 100644 index 0000000..84e3d74 --- /dev/null +++ b/ip_repo/axi_regs_32/component.xml @@ -0,0 +1,1843 @@ + + + user + user + axi_regs_32 + 1.0 + + + S_AXI + + + + + + + + + AWADDR + + + S_AXI_AWADDR + + + + + AWPROT + + + S_AXI_AWPROT + + + + + AWVALID + + + S_AXI_AWVALID + + + + + AWREADY + + + S_AXI_AWREADY + + + + + WDATA + + + S_AXI_WDATA + + + + + WSTRB + + + S_AXI_WSTRB + + + + + WVALID + + + S_AXI_WVALID + + + + + WREADY + + + S_AXI_WREADY + + + + + BRESP + + + S_AXI_BRESP + + + + + BVALID + + + S_AXI_BVALID + + + + + BREADY + + + S_AXI_BREADY + + + + + ARADDR + + + S_AXI_ARADDR + + + + + ARPROT + + + S_AXI_ARPROT + + + + + ARVALID + + + S_AXI_ARVALID + + + + + ARREADY + + + S_AXI_ARREADY + + + + + RDATA + + + S_AXI_RDATA + + + + + RRESP + + + S_AXI_RRESP + + + + + RVALID + + + S_AXI_RVALID + + + + + RREADY + + + S_AXI_RREADY + + + + + + S_AXI_ARESETN + + + + + + + RST + + + S_AXI_ARESETN + + + + + + POLARITY + ACTIVE_LOW + + + + + S_AXI_ACLK + + + + + + + CLK + + + S_AXI_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + S_AXI_ARESETN + + + FREQ_TOLERANCE_HZ + -1 + + + + + + + S_AXI + S_AXI + + reg0 + reg0 + 0x0 + 4096 + 32 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axi_regs_32 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9264ff2f + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axi_regs_32 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + d16affe2 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 6ac409a3 + + + + + + + reg0_out + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reg1_out + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reg2_out + + out + + 31 + 0 + + + + std_logic_vector + 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+ in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_AWREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_WDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_WSTRB + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + S_AXI_WVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_WREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_BRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_BVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_BREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARADDR + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARPROT + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARVALID + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + S_AXI_ARREADY + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RRESP + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RVALID + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + S_AXI_RREADY + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 7 + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_regs_32_ooc.xdc + xdc + USED_IN_out_of_context + + + axi_regs_32.vhd + vhdlSource + CHECKSUM_d16affe2 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_regs_32.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_regs_32_v1_0.tcl + tclSource + CHECKSUM_6ac409a3 + XGUI_VERSION_2 + + + + axi_regs_32 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + + false + + + + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 7 + + + + false + + + + + + Component_Name + axi_regs_32_v1_0 + + + + + + versal + zynq + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /UserIP + + axi_regs_32 + package_project + 3 + + tridsys.com:user:axi_regs_32:1.0 + + 2023-07-06T15:45:59Z + + + + + + 2022.2 + + + + + + + + + + + + + + diff --git a/ip_repo/axi_regs_32/xgui/axi_regs_32_v1_0.tcl b/ip_repo/axi_regs_32/xgui/axi_regs_32_v1_0.tcl new file mode 100644 index 0000000..6902354 --- /dev/null +++ b/ip_repo/axi_regs_32/xgui/axi_regs_32_v1_0.tcl @@ -0,0 +1,38 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + +proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to validate C_S_AXI_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH} +} + diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp deleted file mode 100755 index 2e8c58c..0000000 Binary files a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp and /dev/null differ diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml deleted file mode 100644 index 083cc97..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml +++ /dev/null @@ -1,1606 +0,0 @@ - - - xilinx.com - customized_ip - axis_register_slice_32 - 1.0 - - - RSTIF - RSTIF - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - CLKIF - CLKIF - - - - - - - CLK - - - aclk - - - - - - FREQ_HZ - aclk frequency - aclk frequency - 10000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - CLKIF2X - CLKIF2X - - - - - - - CLK - - - aclk2x - - - - - - FREQ_HZ - aclk2x frequency - aclk2x frequency - 10000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLKENIF - CLKENIF - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - S_AXIS - S_AXIS - - - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - TDATA - - - s_axis_tdata - - - - - TSTRB - - - s_axis_tstrb - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TID - - - s_axis_tid - - - - - TDEST - - - s_axis_tdest - - - - - TUSER - - - s_axis_tuser - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXIS - M_AXIS - - - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - TDATA - - - m_axis_tdata - - - - - TSTRB - - - m_axis_tstrb - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TID - - - m_axis_tid - - - - - TDEST - - - m_axis_tdest - - - - - TUSER - - - m_axis_tuser - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - axis_register_slice_v1_1_29_axis_register_slice - - xilinx_implementation_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axis_register_slice_v1_1_29_axis_register_slice - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axis_register_slice_32 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - - - aclk - - in - - - wire - xilinx_verilogsynthesis - - - - - - aclk2x - - in - - - wire - xilinx_verilogsynthesis - - - - 0x0 - - - - - - false - - - - - - aresetn - - in - - - wire - xilinx_verilogsynthesis - - - - 0x1 - - - - - aclken - - in - - - wire - xilinx_verilogsynthesis - - - - 0x1 - - - - - - false - - - - - - s_axis_tvalid - - in - - - wire - xilinx_verilogsynthesis - - - - 0x0 - - - - - s_axis_tready - - out - - - wire - xilinx_verilogsynthesis - - - - - - - true - - - - - - s_axis_tdata - - in - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - - - - 0x00000000 - - - - - - true - - - - - - s_axis_tstrb - - in - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - - - - 0xF - - - - - - false - - - - - - s_axis_tkeep - - in - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - - - - 0xF - - - - - - false - - - - - - s_axis_tlast - - in - - - wire - xilinx_verilogsynthesis - - - - 0x1 - - - - - - false - - - - - - s_axis_tid - - in - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - - - - 0x0 - - - - - - false - - - - - - s_axis_tdest - - in - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - - - - 0x0 - - - - - - false - - - - - - s_axis_tuser - - in - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - - - - 0x0 - - - - - - false - - - - - - m_axis_tvalid - - out - - - wire - xilinx_verilogsynthesis - - - - - - m_axis_tready - - in - - - wire - xilinx_verilogsynthesis - - - - 0x1 - - - - - - true - - - - - - m_axis_tdata - - out - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - - - - - - - true - - - - - - m_axis_tstrb - - out - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - - - - - - - false - - - - - - m_axis_tkeep - - out - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - - - - - - - false - - - - - - m_axis_tlast - - out - - - wire - xilinx_verilogsynthesis - - - - - - - false - - - - - - m_axis_tid - - out - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - - - - - - - false - - - - - - m_axis_tdest - - out - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - - - - - - - false - - - - - - m_axis_tuser - - out - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - - - - - - - false - - - - - - - - C_FAMILY - zynquplus - - - C_AXIS_TDATA_WIDTH - 32 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 1 - - - C_AXIS_SIGNAL_SET - 0b00000000000000000000000000000011 - - - C_REG_CONFIG - 8 - - - C_NUM_SLR_CROSSINGS - 0 - - - C_PIPELINES_MASTER - 0 - - - C_PIPELINES_SLAVE - 0 - - - C_PIPELINES_MIDDLE - 0 - - - - - - choice_pairs_37189c7b - 0 - 1 - - - choice_pairs_962b65a8 - 1 - 0 - 8 - 7 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - - - - - xilinx_externalfiles_view_fileset - - axis_register_slice_32_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axis_register_slice_32.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axis_register_slice_32_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axis_register_slice_32_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axis_register_slice_32_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - - xilinx_implementation_view_fileset - - axis_register_slice_32_clocks.xdc - xdc - USED_IN_implementation - USED_IN_synthesis - - processing_order - late - - - - - xilinx_synthesisconstraints_view_fileset - - axis_register_slice_32_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_1.vh - verilogSource - true - axis_infrastructure_v1_1_1 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - axis_infrastructure_v1_1_1 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axis_register_slice_v1_1_vl_rfs.v - verilogSource - axis_register_slice_v1_1_29 - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axis_register_slice_32.v - verilogSource - xil_defaultlib - - - - The AXI4-Stream Register Slice IP provides the infrastructure to insert a pipeline stage between a AXI4-Stream master and slave. - - - TDATA_NUM_BYTES - TDATA Width (bytes) - 4 - - - - true - - - - - - TID_WIDTH - TID Width (bits) - 0 - - - - true - - - - - - TDEST_WIDTH - TDEST Width (bits) - 0 - - - - true - - - - - - TUSER_WIDTH - TUSER Width (bits) - 0 - - - - true - - - - - - REG_CONFIG - Register Pipeline Type - 8 - - - - true - - - - - - HAS_TREADY - Enable TREADY - 1 - - - - true - - - - - - HAS_TSTRB - Enable TSTRB - 0 - - - - true - - - - - - HAS_TKEEP - Enable TKEEP - 0 - - - - true - - - - - - HAS_TLAST - Enable TLAST - 0 - - - - true - - - - - - HAS_ACLKEN - Enable ACLKEN - 0 - - - - true - - - - - - NUM_SLR_CROSSINGS - Number of SLR Crossings - 0 - - - - false - - - - - - PIPELINES_MASTER - Pipeline Stages within Master-side SLR - 0 - - - - false - - - - - - PIPELINES_MIDDLE - Pipeline Stages within Middle SLR - 0 - - - - false - - - - - - PIPELINES_SLAVE - Pipeline Stages within Slave-side SLR - 0 - - - - false - - - - - - Component_Name - axis_register_slice_32 - - - - - AXI4-Stream Register Slice - - XPM_FIFO - XPM_CDC - - 29 - - - - - - - - - 2023.2 - - - - - - - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc deleted file mode 100644 index d5fdeee..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc +++ /dev/null @@ -1,6 +0,0 @@ -############################################################################################################### -# Core-Level Timing Constraints for axi_register_slice Component "axis_register_slice_32" -############################################################################################################### -# -# This component is not configured in a multi-SLR crossing or auto-pipelining mode. -# No timing core-level constraints are needed. diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc deleted file mode 100644 index 9f673bc..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc +++ /dev/null @@ -1,57 +0,0 @@ -# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of AMD and is protected under U.S. and international copyright -# and other intellectual property laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# AMD, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) AMD shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or AMD had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# AMD products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of AMD products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# DO NOT MODIFY THIS FILE. -# ######################################################### -# -# This XDC is used only in OOC mode for synthesis, implementation -# -# ######################################################### - - -create_clock -period 100 -name aclk [get_ports aclk] - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v deleted file mode 100644 index d2ccd4d..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v +++ /dev/null @@ -1,1100 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -// Date : Thu Apr 23 10:08:04 2026 -// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS -// Command : write_verilog -force -mode funcsim -rename_top axis_register_slice_32 -prefix -// axis_register_slice_32_ axis_register_slice_32_sim_netlist.v -// Design : axis_register_slice_32 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xczu19eg-ffvc1760-2-i -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *) -(* NotValidForBitStream *) -module axis_register_slice_32 - (aclk, - aresetn, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata); - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input aclk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aresetn; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input s_axis_tvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output s_axis_tready; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input [31:0]s_axis_tdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output m_axis_tvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input m_axis_tready; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output [31:0]m_axis_tdata; - - wire aclk; - wire aresetn; - wire [31:0]m_axis_tdata; - wire m_axis_tready; - wire m_axis_tvalid; - wire [31:0]s_axis_tdata; - wire s_axis_tready; - wire s_axis_tvalid; - wire NLW_inst_m_axis_tlast_UNCONNECTED; - wire [0:0]NLW_inst_m_axis_tdest_UNCONNECTED; - wire [0:0]NLW_inst_m_axis_tid_UNCONNECTED; - wire [3:0]NLW_inst_m_axis_tkeep_UNCONNECTED; - wire [3:0]NLW_inst_m_axis_tstrb_UNCONNECTED; - wire [0:0]NLW_inst_m_axis_tuser_UNCONNECTED; - - (* C_AXIS_SIGNAL_SET = "3" *) - (* C_AXIS_TDATA_WIDTH = "32" *) - (* C_AXIS_TDEST_WIDTH = "1" *) - (* C_AXIS_TID_WIDTH = "1" *) - (* C_AXIS_TUSER_WIDTH = "1" *) - (* C_FAMILY = "zynquplus" *) - (* C_NUM_SLR_CROSSINGS = "0" *) - (* C_PIPELINES_MASTER = "0" *) - (* C_PIPELINES_MIDDLE = "0" *) - (* C_PIPELINES_SLAVE = "0" *) - (* C_REG_CONFIG = "8" *) - (* DowngradeIPIdentifiedWarnings = "yes" *) - (* G_INDX_SS_TDATA = "1" *) - (* G_INDX_SS_TDEST = "6" *) - (* G_INDX_SS_TID = "5" *) - (* G_INDX_SS_TKEEP = "3" *) - (* G_INDX_SS_TLAST = "4" *) - (* G_INDX_SS_TREADY = "0" *) - (* G_INDX_SS_TSTRB = "2" *) - (* G_INDX_SS_TUSER = "7" *) - (* G_MASK_SS_TDATA = "2" *) - (* G_MASK_SS_TDEST = "64" *) - (* G_MASK_SS_TID = "32" *) - (* G_MASK_SS_TKEEP = "8" *) - (* G_MASK_SS_TLAST = "16" *) - (* G_MASK_SS_TREADY = "1" *) - (* G_MASK_SS_TSTRB = "4" *) - (* G_MASK_SS_TUSER = "128" *) - (* G_TASK_SEVERITY_ERR = "2" *) - (* G_TASK_SEVERITY_INFO = "0" *) - (* G_TASK_SEVERITY_WARNING = "1" *) - (* P_TPAYLOAD_WIDTH = "32" *) - axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice inst - (.aclk(aclk), - .aclk2x(1'b0), - .aclken(1'b1), - .aresetn(aresetn), - .m_axis_tdata(m_axis_tdata), - .m_axis_tdest(NLW_inst_m_axis_tdest_UNCONNECTED[0]), - .m_axis_tid(NLW_inst_m_axis_tid_UNCONNECTED[0]), - .m_axis_tkeep(NLW_inst_m_axis_tkeep_UNCONNECTED[3:0]), - .m_axis_tlast(NLW_inst_m_axis_tlast_UNCONNECTED), - .m_axis_tready(m_axis_tready), - .m_axis_tstrb(NLW_inst_m_axis_tstrb_UNCONNECTED[3:0]), - .m_axis_tuser(NLW_inst_m_axis_tuser_UNCONNECTED[0]), - .m_axis_tvalid(m_axis_tvalid), - .s_axis_tdata(s_axis_tdata), - .s_axis_tdest(1'b0), - .s_axis_tid(1'b0), - .s_axis_tkeep({1'b1,1'b1,1'b1,1'b1}), - .s_axis_tlast(1'b1), - .s_axis_tready(s_axis_tready), - .s_axis_tstrb({1'b1,1'b1,1'b1,1'b1}), - .s_axis_tuser(1'b0), - .s_axis_tvalid(s_axis_tvalid)); -endmodule - -(* C_AXIS_SIGNAL_SET = "3" *) (* C_AXIS_TDATA_WIDTH = "32" *) (* C_AXIS_TDEST_WIDTH = "1" *) -(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "1" *) (* C_FAMILY = "zynquplus" *) -(* C_NUM_SLR_CROSSINGS = "0" *) (* C_PIPELINES_MASTER = "0" *) (* C_PIPELINES_MIDDLE = "0" *) -(* C_PIPELINES_SLAVE = "0" *) (* C_REG_CONFIG = "8" *) (* DowngradeIPIdentifiedWarnings = "yes" *) -(* G_INDX_SS_TDATA = "1" *) (* G_INDX_SS_TDEST = "6" *) (* G_INDX_SS_TID = "5" *) -(* G_INDX_SS_TKEEP = "3" *) (* G_INDX_SS_TLAST = "4" *) (* G_INDX_SS_TREADY = "0" *) -(* G_INDX_SS_TSTRB = "2" *) (* G_INDX_SS_TUSER = "7" *) (* G_MASK_SS_TDATA = "2" *) -(* G_MASK_SS_TDEST = "64" *) (* G_MASK_SS_TID = "32" *) (* G_MASK_SS_TKEEP = "8" *) -(* G_MASK_SS_TLAST = "16" *) (* G_MASK_SS_TREADY = "1" *) (* G_MASK_SS_TSTRB = "4" *) -(* G_MASK_SS_TUSER = "128" *) (* G_TASK_SEVERITY_ERR = "2" *) (* G_TASK_SEVERITY_INFO = "0" *) -(* G_TASK_SEVERITY_WARNING = "1" *) (* P_TPAYLOAD_WIDTH = "32" *) -module axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice - (aclk, - aclk2x, - aresetn, - aclken, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - s_axis_tstrb, - s_axis_tkeep, - s_axis_tlast, - s_axis_tid, - s_axis_tdest, - s_axis_tuser, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata, - m_axis_tstrb, - m_axis_tkeep, - m_axis_tlast, - m_axis_tid, - m_axis_tdest, - m_axis_tuser); - input aclk; - input aclk2x; - input aresetn; - input aclken; - input s_axis_tvalid; - output s_axis_tready; - input [31:0]s_axis_tdata; - input [3:0]s_axis_tstrb; - input [3:0]s_axis_tkeep; - input s_axis_tlast; - input [0:0]s_axis_tid; - input [0:0]s_axis_tdest; - input [0:0]s_axis_tuser; - output m_axis_tvalid; - input m_axis_tready; - output [31:0]m_axis_tdata; - output [3:0]m_axis_tstrb; - output [3:0]m_axis_tkeep; - output m_axis_tlast; - output [0:0]m_axis_tid; - output [0:0]m_axis_tdest; - output [0:0]m_axis_tuser; - - wire \ ; - wire aclk; - wire areset_r; - wire areset_r_i_1_n_0; - wire aresetn; - wire [31:0]m_axis_tdata; - wire m_axis_tready; - wire m_axis_tvalid; - wire [31:0]s_axis_tdata; - wire s_axis_tready; - wire s_axis_tvalid; - - assign m_axis_tdest[0] = \ ; - assign m_axis_tid[0] = \ ; - assign m_axis_tkeep[3] = \ ; - assign m_axis_tkeep[2] = \ ; - assign m_axis_tkeep[1] = \ ; - assign m_axis_tkeep[0] = \ ; - assign m_axis_tlast = \ ; - assign m_axis_tstrb[3] = \ ; - assign m_axis_tstrb[2] = \ ; - assign m_axis_tstrb[1] = \ ; - assign m_axis_tstrb[0] = \ ; - assign m_axis_tuser[0] = \ ; - GND GND - (.G(\ )); - LUT1 #( - .INIT(2'h1)) - areset_r_i_1 - (.I0(aresetn), - .O(areset_r_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - areset_r_reg - (.C(aclk), - .CE(1'b1), - .D(areset_r_i_1_n_0), - .Q(areset_r), - .R(1'b0)); - axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice axisc_register_slice_0 - (.Q(m_axis_tvalid), - .aclk(aclk), - .areset_r(areset_r), - .m_axis_tdata(m_axis_tdata), - .m_axis_tready(m_axis_tready), - .s_axis_tdata(s_axis_tdata), - .s_axis_tready(s_axis_tready), - .s_axis_tvalid(s_axis_tvalid)); -endmodule - -module axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice - (s_axis_tready, - Q, - m_axis_tdata, - aclk, - m_axis_tready, - s_axis_tvalid, - s_axis_tdata, - areset_r); - output s_axis_tready; - output [0:0]Q; - output [31:0]m_axis_tdata; - input aclk; - input m_axis_tready; - input s_axis_tvalid; - input [31:0]s_axis_tdata; - input areset_r; - - wire [0:0]Q; - wire aclk; - wire areset_r; - wire \aresetn_d_reg_n_0_[0] ; - wire \aresetn_d_reg_n_0_[1] ; - wire [31:0]m_axis_tdata; - wire m_axis_tready; - wire [31:0]p_0_in; - wire [0:0]p_1_out; - wire [31:0]s_axis_tdata; - wire s_axis_tready; - wire s_axis_tvalid; - wire s_ready_i0; - wire s_ready_i_i_1_n_0; - wire s_ready_i_i_2_n_0; - wire [1:0]state; - wire \state[0]_i_1_n_0 ; - wire \state[0]_i_2_n_0 ; - wire \state_reg_n_0_[1] ; - wire storage_data1; - wire [31:0]storage_data2; - wire storage_data2_0; - - LUT4 #( - .INIT(16'hE420)) - \__2/i_ - (.I0(\state_reg_n_0_[1] ), - .I1(Q), - .I2(s_axis_tvalid), - .I3(m_axis_tready), - .O(storage_data1)); - LUT1 #( - .INIT(2'h1)) - \aresetn_d[0]_i_1 - (.I0(areset_r), - .O(p_1_out)); - (* equivalent_register_removal = "no" *) - FDRE #( - .INIT(1'b0)) - \aresetn_d_reg[0] - (.C(aclk), - .CE(1'b1), - .D(p_1_out), - .Q(\aresetn_d_reg_n_0_[0] ), - .R(1'b0)); - (* equivalent_register_removal = "no" *) - FDRE #( - .INIT(1'b0)) - \aresetn_d_reg[1] - (.C(aclk), - .CE(1'b1), - .D(\aresetn_d_reg_n_0_[0] ), - .Q(\aresetn_d_reg_n_0_[1] ), - .R(1'b0)); - LUT6 #( - .INIT(64'h00000000E2E2EEE2)) - s_ready_i_i_1 - (.I0(s_axis_tready), - .I1(s_ready_i_i_2_n_0), - .I2(s_ready_i0), - .I3(m_axis_tready), - .I4(\state_reg_n_0_[1] ), - .I5(areset_r), - .O(s_ready_i_i_1_n_0)); - LUT6 #( - .INIT(64'h2808FFFF00000000)) - s_ready_i_i_2 - (.I0(Q), - .I1(m_axis_tready), - .I2(\state_reg_n_0_[1] ), - .I3(s_axis_tvalid), - .I4(\aresetn_d_reg_n_0_[1] ), - .I5(\aresetn_d_reg_n_0_[0] ), - .O(s_ready_i_i_2_n_0)); - LUT2 #( - .INIT(4'h2)) - s_ready_i_i_3 - (.I0(\aresetn_d_reg_n_0_[0] ), - .I1(\aresetn_d_reg_n_0_[1] ), - .O(s_ready_i0)); - FDRE #( - .INIT(1'b0)) - s_ready_i_reg - (.C(aclk), - .CE(1'b1), - .D(s_ready_i_i_1_n_0), - .Q(s_axis_tready), - .R(1'b0)); - LUT3 #( - .INIT(8'hBA)) - \state[0]_i_1 - (.I0(areset_r), - .I1(\aresetn_d_reg_n_0_[1] ), - .I2(\aresetn_d_reg_n_0_[0] ), - .O(\state[0]_i_1_n_0 )); - LUT5 #( - .INIT(32'h2A808A8A)) - \state[0]_i_2 - (.I0(\aresetn_d_reg_n_0_[0] ), - .I1(m_axis_tready), - .I2(Q), - .I3(s_axis_tvalid), - .I4(\state_reg_n_0_[1] ), - .O(\state[0]_i_2_n_0 )); - LUT4 #( - .INIT(16'h7808)) - \state[0]_i_3 - (.I0(m_axis_tready), - .I1(Q), - .I2(\state_reg_n_0_[1] ), - .I3(s_axis_tvalid), - .O(state[0])); - LUT4 #( - .INIT(16'hFD2D)) - \state[1]_i_1 - (.I0(\state_reg_n_0_[1] ), - .I1(s_axis_tvalid), - .I2(Q), - .I3(m_axis_tready), - .O(state[1])); - (* FSM_ENCODING = "none" *) - FDRE #( - .INIT(1'b0)) - \state_reg[0] - (.C(aclk), - .CE(\state[0]_i_2_n_0 ), - .D(state[0]), - .Q(Q), - .R(\state[0]_i_1_n_0 )); - (* FSM_ENCODING = "none" *) - FDSE #( - .INIT(1'b1)) - \state_reg[1] - (.C(aclk), - .CE(\state[0]_i_2_n_0 ), - .D(state[1]), - .Q(\state_reg_n_0_[1] ), - .S(\state[0]_i_1_n_0 )); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[0]_i_1 - (.I0(storage_data2[0]), - .I1(s_axis_tdata[0]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[0])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[10]_i_1 - (.I0(storage_data2[10]), - .I1(s_axis_tdata[10]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[10])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[11]_i_1 - (.I0(storage_data2[11]), - .I1(s_axis_tdata[11]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[11])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[12]_i_1 - (.I0(storage_data2[12]), - .I1(s_axis_tdata[12]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[12])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[13]_i_1 - (.I0(storage_data2[13]), - .I1(s_axis_tdata[13]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[13])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[14]_i_1 - (.I0(storage_data2[14]), - .I1(s_axis_tdata[14]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[14])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[15]_i_1 - (.I0(storage_data2[15]), - .I1(s_axis_tdata[15]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[15])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[16]_i_1 - (.I0(storage_data2[16]), - .I1(s_axis_tdata[16]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[16])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[17]_i_1 - (.I0(storage_data2[17]), - .I1(s_axis_tdata[17]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[17])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[18]_i_1 - (.I0(storage_data2[18]), - .I1(s_axis_tdata[18]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[18])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[19]_i_1 - (.I0(storage_data2[19]), - .I1(s_axis_tdata[19]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[19])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[1]_i_1 - (.I0(storage_data2[1]), - .I1(s_axis_tdata[1]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[1])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[20]_i_1 - (.I0(storage_data2[20]), - .I1(s_axis_tdata[20]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[20])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[21]_i_1 - (.I0(storage_data2[21]), - .I1(s_axis_tdata[21]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[21])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[22]_i_1 - (.I0(storage_data2[22]), - .I1(s_axis_tdata[22]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[22])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[23]_i_1 - (.I0(storage_data2[23]), - .I1(s_axis_tdata[23]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[23])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[24]_i_1 - (.I0(storage_data2[24]), - .I1(s_axis_tdata[24]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[24])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[25]_i_1 - (.I0(storage_data2[25]), - .I1(s_axis_tdata[25]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[25])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[26]_i_1 - (.I0(storage_data2[26]), - .I1(s_axis_tdata[26]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[26])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[27]_i_1 - (.I0(storage_data2[27]), - .I1(s_axis_tdata[27]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[27])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[28]_i_1 - (.I0(storage_data2[28]), - .I1(s_axis_tdata[28]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[28])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[29]_i_1 - (.I0(storage_data2[29]), - .I1(s_axis_tdata[29]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[29])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[2]_i_1 - (.I0(storage_data2[2]), - .I1(s_axis_tdata[2]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[2])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[30]_i_1 - (.I0(storage_data2[30]), - .I1(s_axis_tdata[30]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[30])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[31]_i_1 - (.I0(storage_data2[31]), - .I1(s_axis_tdata[31]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[31])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[3]_i_1 - (.I0(storage_data2[3]), - .I1(s_axis_tdata[3]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[3])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[4]_i_1 - (.I0(storage_data2[4]), - .I1(s_axis_tdata[4]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[4])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[5]_i_1 - (.I0(storage_data2[5]), - .I1(s_axis_tdata[5]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[5])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[6]_i_1 - (.I0(storage_data2[6]), - .I1(s_axis_tdata[6]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[6])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[7]_i_1 - (.I0(storage_data2[7]), - .I1(s_axis_tdata[7]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[7])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[8]_i_1 - (.I0(storage_data2[8]), - .I1(s_axis_tdata[8]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[8])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[9]_i_1 - (.I0(storage_data2[9]), - .I1(s_axis_tdata[9]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[9])); - FDRE \storage_data1_reg[0] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[0]), - .Q(m_axis_tdata[0]), - .R(1'b0)); - FDRE \storage_data1_reg[10] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[10]), - .Q(m_axis_tdata[10]), - .R(1'b0)); - FDRE \storage_data1_reg[11] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[11]), - .Q(m_axis_tdata[11]), - .R(1'b0)); - FDRE \storage_data1_reg[12] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[12]), - .Q(m_axis_tdata[12]), - .R(1'b0)); - FDRE \storage_data1_reg[13] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[13]), - .Q(m_axis_tdata[13]), - .R(1'b0)); - FDRE \storage_data1_reg[14] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[14]), - .Q(m_axis_tdata[14]), - .R(1'b0)); - FDRE \storage_data1_reg[15] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[15]), - .Q(m_axis_tdata[15]), - .R(1'b0)); - FDRE \storage_data1_reg[16] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[16]), - .Q(m_axis_tdata[16]), - .R(1'b0)); - FDRE \storage_data1_reg[17] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[17]), - .Q(m_axis_tdata[17]), - .R(1'b0)); - FDRE \storage_data1_reg[18] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[18]), - .Q(m_axis_tdata[18]), - .R(1'b0)); - FDRE \storage_data1_reg[19] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[19]), - .Q(m_axis_tdata[19]), - .R(1'b0)); - FDRE \storage_data1_reg[1] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[1]), - .Q(m_axis_tdata[1]), - .R(1'b0)); - FDRE \storage_data1_reg[20] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[20]), - .Q(m_axis_tdata[20]), - .R(1'b0)); - FDRE \storage_data1_reg[21] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[21]), - .Q(m_axis_tdata[21]), - .R(1'b0)); - FDRE \storage_data1_reg[22] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[22]), - .Q(m_axis_tdata[22]), - .R(1'b0)); - FDRE \storage_data1_reg[23] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[23]), - .Q(m_axis_tdata[23]), - .R(1'b0)); - FDRE \storage_data1_reg[24] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[24]), - .Q(m_axis_tdata[24]), - .R(1'b0)); - FDRE \storage_data1_reg[25] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[25]), - .Q(m_axis_tdata[25]), - .R(1'b0)); - FDRE \storage_data1_reg[26] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[26]), - .Q(m_axis_tdata[26]), - .R(1'b0)); - FDRE \storage_data1_reg[27] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[27]), - .Q(m_axis_tdata[27]), - .R(1'b0)); - FDRE \storage_data1_reg[28] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[28]), - .Q(m_axis_tdata[28]), - .R(1'b0)); - FDRE \storage_data1_reg[29] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[29]), - .Q(m_axis_tdata[29]), - .R(1'b0)); - FDRE \storage_data1_reg[2] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[2]), - .Q(m_axis_tdata[2]), - .R(1'b0)); - FDRE \storage_data1_reg[30] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[30]), - .Q(m_axis_tdata[30]), - .R(1'b0)); - FDRE \storage_data1_reg[31] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[31]), - .Q(m_axis_tdata[31]), - .R(1'b0)); - FDRE \storage_data1_reg[3] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[3]), - .Q(m_axis_tdata[3]), - .R(1'b0)); - FDRE \storage_data1_reg[4] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[4]), - .Q(m_axis_tdata[4]), - .R(1'b0)); - FDRE \storage_data1_reg[5] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[5]), - .Q(m_axis_tdata[5]), - .R(1'b0)); - FDRE \storage_data1_reg[6] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[6]), - .Q(m_axis_tdata[6]), - .R(1'b0)); - FDRE \storage_data1_reg[7] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[7]), - .Q(m_axis_tdata[7]), - .R(1'b0)); - FDRE \storage_data1_reg[8] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[8]), - .Q(m_axis_tdata[8]), - .R(1'b0)); - FDRE \storage_data1_reg[9] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[9]), - .Q(m_axis_tdata[9]), - .R(1'b0)); - LUT2 #( - .INIT(4'h8)) - \storage_data2[31]_i_1 - (.I0(s_axis_tvalid), - .I1(s_axis_tready), - .O(storage_data2_0)); - FDRE \storage_data2_reg[0] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[0]), - .Q(storage_data2[0]), - .R(1'b0)); - FDRE \storage_data2_reg[10] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[10]), - .Q(storage_data2[10]), - .R(1'b0)); - FDRE \storage_data2_reg[11] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[11]), - .Q(storage_data2[11]), - .R(1'b0)); - FDRE \storage_data2_reg[12] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[12]), - .Q(storage_data2[12]), - .R(1'b0)); - FDRE \storage_data2_reg[13] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[13]), - .Q(storage_data2[13]), - .R(1'b0)); - FDRE \storage_data2_reg[14] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[14]), - .Q(storage_data2[14]), - .R(1'b0)); - FDRE \storage_data2_reg[15] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[15]), - .Q(storage_data2[15]), - .R(1'b0)); - FDRE \storage_data2_reg[16] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[16]), - .Q(storage_data2[16]), - .R(1'b0)); - FDRE \storage_data2_reg[17] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[17]), - .Q(storage_data2[17]), - .R(1'b0)); - FDRE \storage_data2_reg[18] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[18]), - .Q(storage_data2[18]), - .R(1'b0)); - FDRE \storage_data2_reg[19] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[19]), - .Q(storage_data2[19]), - .R(1'b0)); - FDRE \storage_data2_reg[1] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[1]), - .Q(storage_data2[1]), - .R(1'b0)); - FDRE \storage_data2_reg[20] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[20]), - .Q(storage_data2[20]), - .R(1'b0)); - FDRE \storage_data2_reg[21] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[21]), - .Q(storage_data2[21]), - .R(1'b0)); - FDRE \storage_data2_reg[22] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[22]), - .Q(storage_data2[22]), - .R(1'b0)); - FDRE \storage_data2_reg[23] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[23]), - .Q(storage_data2[23]), - .R(1'b0)); - FDRE \storage_data2_reg[24] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[24]), - .Q(storage_data2[24]), - .R(1'b0)); - FDRE \storage_data2_reg[25] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[25]), - .Q(storage_data2[25]), - .R(1'b0)); - FDRE \storage_data2_reg[26] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[26]), - .Q(storage_data2[26]), - .R(1'b0)); - FDRE \storage_data2_reg[27] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[27]), - .Q(storage_data2[27]), - .R(1'b0)); - FDRE \storage_data2_reg[28] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[28]), - .Q(storage_data2[28]), - .R(1'b0)); - FDRE \storage_data2_reg[29] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[29]), - .Q(storage_data2[29]), - .R(1'b0)); - FDRE \storage_data2_reg[2] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[2]), - .Q(storage_data2[2]), - .R(1'b0)); - FDRE \storage_data2_reg[30] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[30]), - .Q(storage_data2[30]), - .R(1'b0)); - FDRE \storage_data2_reg[31] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[31]), - .Q(storage_data2[31]), - .R(1'b0)); - FDRE \storage_data2_reg[3] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[3]), - .Q(storage_data2[3]), - .R(1'b0)); - FDRE \storage_data2_reg[4] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[4]), - .Q(storage_data2[4]), - .R(1'b0)); - FDRE \storage_data2_reg[5] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[5]), - .Q(storage_data2[5]), - .R(1'b0)); - FDRE \storage_data2_reg[6] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[6]), - .Q(storage_data2[6]), - .R(1'b0)); - FDRE \storage_data2_reg[7] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[7]), - .Q(storage_data2[7]), - .R(1'b0)); - FDRE \storage_data2_reg[8] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[8]), - .Q(storage_data2[8]), - .R(1'b0)); - FDRE \storage_data2_reg[9] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[9]), - .Q(storage_data2[9]), - .R(1'b0)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - parameter GRES_WIDTH = 10000; - parameter GRES_START = 10000; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - wire GRESTORE; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - reg GRESTORE_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - assign (strong1, weak0) GRESTORE = GRESTORE_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - - initial begin - GRESTORE_int = 1'b0; - #(GRES_START); - GRESTORE_int = 1'b1; - #(GRES_WIDTH); - GRESTORE_int = 1'b0; - end - -endmodule -`endif diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl deleted file mode 100644 index 63fbf37..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl +++ /dev/null @@ -1,1366 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 --- Date : Thu Apr 23 10:08:04 2026 --- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS --- Command : write_vhdl -force -mode funcsim -rename_top axis_register_slice_32 -prefix --- axis_register_slice_32_ axis_register_slice_32_sim_netlist.vhdl --- Design : axis_register_slice_32 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xczu19eg-ffvc1760-2-i --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice is - port ( - s_axis_tready : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - aclk : in STD_LOGIC; - m_axis_tready : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - areset_r : in STD_LOGIC - ); -end axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice; - -architecture STRUCTURE of axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice is - signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; - signal \aresetn_d_reg_n_0_[1]\ : STD_LOGIC; - signal p_0_in : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal p_1_out : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^s_axis_tready\ : STD_LOGIC; - signal s_ready_i0 : STD_LOGIC; - signal s_ready_i_i_1_n_0 : STD_LOGIC; - signal s_ready_i_i_2_n_0 : STD_LOGIC; - signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \state[0]_i_1_n_0\ : STD_LOGIC; - signal \state[0]_i_2_n_0\ : STD_LOGIC; - signal \state_reg_n_0_[1]\ : STD_LOGIC; - signal storage_data1 : STD_LOGIC; - signal storage_data2 : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal storage_data2_0 : STD_LOGIC; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of \aresetn_d_reg[0]\ : label is "no"; - attribute equivalent_register_removal of \aresetn_d_reg[1]\ : label is "no"; - attribute FSM_ENCODING : string; - attribute FSM_ENCODING of \state_reg[0]\ : label is "none"; - attribute FSM_ENCODING of \state_reg[1]\ : label is "none"; -begin - Q(0) <= \^q\(0); - s_axis_tready <= \^s_axis_tready\; -\__2/i_\: unisim.vcomponents.LUT4 - generic map( - INIT => X"E420" - ) - port map ( - I0 => \state_reg_n_0_[1]\, - I1 => \^q\(0), - I2 => s_axis_tvalid, - I3 => m_axis_tready, - O => storage_data1 - ); -\aresetn_d[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => areset_r, - O => p_1_out(0) - ); -\aresetn_d_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => p_1_out(0), - Q => \aresetn_d_reg_n_0_[0]\, - R => '0' - ); -\aresetn_d_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => \aresetn_d_reg_n_0_[0]\, - Q => \aresetn_d_reg_n_0_[1]\, - R => '0' - ); -s_ready_i_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000E2E2EEE2" - ) - port map ( - I0 => \^s_axis_tready\, - I1 => s_ready_i_i_2_n_0, - I2 => s_ready_i0, - I3 => m_axis_tready, - I4 => \state_reg_n_0_[1]\, - I5 => areset_r, - O => s_ready_i_i_1_n_0 - ); -s_ready_i_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"2808FFFF00000000" - ) - port map ( - I0 => \^q\(0), - I1 => m_axis_tready, - I2 => \state_reg_n_0_[1]\, - I3 => s_axis_tvalid, - I4 => \aresetn_d_reg_n_0_[1]\, - I5 => \aresetn_d_reg_n_0_[0]\, - O => s_ready_i_i_2_n_0 - ); -s_ready_i_i_3: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => \aresetn_d_reg_n_0_[0]\, - I1 => \aresetn_d_reg_n_0_[1]\, - O => s_ready_i0 - ); -s_ready_i_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => s_ready_i_i_1_n_0, - Q => \^s_axis_tready\, - R => '0' - ); -\state[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"BA" - ) - port map ( - I0 => areset_r, - I1 => \aresetn_d_reg_n_0_[1]\, - I2 => \aresetn_d_reg_n_0_[0]\, - O => \state[0]_i_1_n_0\ - ); -\state[0]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"2A808A8A" - ) - port map ( - I0 => \aresetn_d_reg_n_0_[0]\, - I1 => m_axis_tready, - I2 => \^q\(0), - I3 => s_axis_tvalid, - I4 => \state_reg_n_0_[1]\, - O => \state[0]_i_2_n_0\ - ); -\state[0]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7808" - ) - port map ( - I0 => m_axis_tready, - I1 => \^q\(0), - I2 => \state_reg_n_0_[1]\, - I3 => s_axis_tvalid, - O => state(0) - ); -\state[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FD2D" - ) - port map ( - I0 => \state_reg_n_0_[1]\, - I1 => s_axis_tvalid, - I2 => \^q\(0), - I3 => m_axis_tready, - O => state(1) - ); -\state_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => \state[0]_i_2_n_0\, - D => state(0), - Q => \^q\(0), - R => \state[0]_i_1_n_0\ - ); -\state_reg[1]\: unisim.vcomponents.FDSE - generic map( - INIT => '1' - ) - port map ( - C => aclk, - CE => \state[0]_i_2_n_0\, - D => state(1), - Q => \state_reg_n_0_[1]\, - S => \state[0]_i_1_n_0\ - ); -\storage_data1[0]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(0), - I1 => s_axis_tdata(0), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(0) - ); -\storage_data1[10]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(10), - I1 => s_axis_tdata(10), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(10) - ); -\storage_data1[11]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(11), - I1 => s_axis_tdata(11), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(11) - ); -\storage_data1[12]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(12), - I1 => s_axis_tdata(12), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(12) - ); -\storage_data1[13]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(13), - I1 => s_axis_tdata(13), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(13) - ); -\storage_data1[14]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(14), - I1 => s_axis_tdata(14), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(14) - ); -\storage_data1[15]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(15), - I1 => s_axis_tdata(15), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(15) - ); -\storage_data1[16]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(16), - I1 => s_axis_tdata(16), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(16) - ); -\storage_data1[17]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(17), - I1 => s_axis_tdata(17), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(17) - ); -\storage_data1[18]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(18), - I1 => s_axis_tdata(18), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(18) - ); -\storage_data1[19]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(19), - I1 => s_axis_tdata(19), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(19) - ); -\storage_data1[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(1), - I1 => s_axis_tdata(1), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(1) - ); -\storage_data1[20]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(20), - I1 => s_axis_tdata(20), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(20) - ); -\storage_data1[21]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(21), - I1 => s_axis_tdata(21), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(21) - ); -\storage_data1[22]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(22), - I1 => s_axis_tdata(22), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(22) - ); -\storage_data1[23]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(23), - I1 => s_axis_tdata(23), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(23) - ); -\storage_data1[24]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(24), - I1 => s_axis_tdata(24), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(24) - ); -\storage_data1[25]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(25), - I1 => s_axis_tdata(25), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(25) - ); -\storage_data1[26]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(26), - I1 => s_axis_tdata(26), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(26) - ); -\storage_data1[27]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(27), - I1 => s_axis_tdata(27), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(27) - ); -\storage_data1[28]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(28), - I1 => s_axis_tdata(28), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(28) - ); -\storage_data1[29]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(29), - I1 => s_axis_tdata(29), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(29) - ); -\storage_data1[2]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(2), - I1 => s_axis_tdata(2), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(2) - ); -\storage_data1[30]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(30), - I1 => s_axis_tdata(30), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(30) - ); -\storage_data1[31]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(31), - I1 => s_axis_tdata(31), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(31) - ); -\storage_data1[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(3), - I1 => s_axis_tdata(3), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(3) - ); -\storage_data1[4]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(4), - I1 => s_axis_tdata(4), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(4) - ); -\storage_data1[5]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(5), - I1 => s_axis_tdata(5), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(5) - ); -\storage_data1[6]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(6), - I1 => s_axis_tdata(6), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(6) - ); -\storage_data1[7]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(7), - I1 => s_axis_tdata(7), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(7) - ); -\storage_data1[8]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(8), - I1 => s_axis_tdata(8), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(8) - ); -\storage_data1[9]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(9), - I1 => s_axis_tdata(9), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(9) - ); -\storage_data1_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(0), - Q => m_axis_tdata(0), - R => '0' - ); -\storage_data1_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(10), - Q => m_axis_tdata(10), - R => '0' - ); -\storage_data1_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(11), - Q => m_axis_tdata(11), - R => '0' - ); -\storage_data1_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(12), - Q => m_axis_tdata(12), - R => '0' - ); -\storage_data1_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(13), - Q => m_axis_tdata(13), - R => '0' - ); -\storage_data1_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(14), - Q => m_axis_tdata(14), - R => '0' - ); -\storage_data1_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(15), - Q => m_axis_tdata(15), - R => '0' - ); -\storage_data1_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(16), - Q => m_axis_tdata(16), - R => '0' - ); -\storage_data1_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(17), - Q => m_axis_tdata(17), - R => '0' - ); -\storage_data1_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(18), - Q => m_axis_tdata(18), - R => '0' - ); -\storage_data1_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(19), - Q => m_axis_tdata(19), - R => '0' - ); -\storage_data1_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(1), - Q => m_axis_tdata(1), - R => '0' - ); -\storage_data1_reg[20]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(20), - Q => m_axis_tdata(20), - R => '0' - ); -\storage_data1_reg[21]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(21), - Q => m_axis_tdata(21), - R => '0' - ); -\storage_data1_reg[22]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(22), - Q => m_axis_tdata(22), - R => '0' - ); -\storage_data1_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(23), - Q => m_axis_tdata(23), - R => '0' - ); -\storage_data1_reg[24]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(24), - Q => m_axis_tdata(24), - R => '0' - ); -\storage_data1_reg[25]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(25), - Q => m_axis_tdata(25), - R => '0' - ); -\storage_data1_reg[26]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(26), - Q => m_axis_tdata(26), - R => '0' - ); -\storage_data1_reg[27]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(27), - Q => m_axis_tdata(27), - R => '0' - ); -\storage_data1_reg[28]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(28), - Q => m_axis_tdata(28), - R => '0' - ); -\storage_data1_reg[29]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(29), - Q => m_axis_tdata(29), - R => '0' - ); -\storage_data1_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(2), - Q => m_axis_tdata(2), - R => '0' - ); -\storage_data1_reg[30]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(30), - Q => m_axis_tdata(30), - R => '0' - ); -\storage_data1_reg[31]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(31), - Q => m_axis_tdata(31), - R => '0' - ); -\storage_data1_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(3), - Q => m_axis_tdata(3), - R => '0' - ); -\storage_data1_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(4), - Q => m_axis_tdata(4), - R => '0' - ); -\storage_data1_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(5), - Q => m_axis_tdata(5), - R => '0' - ); -\storage_data1_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(6), - Q => m_axis_tdata(6), - R => '0' - ); -\storage_data1_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(7), - Q => m_axis_tdata(7), - R => '0' - ); -\storage_data1_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(8), - Q => m_axis_tdata(8), - R => '0' - ); -\storage_data1_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(9), - Q => m_axis_tdata(9), - R => '0' - ); -\storage_data2[31]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => s_axis_tvalid, - I1 => \^s_axis_tready\, - O => storage_data2_0 - ); -\storage_data2_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(0), - Q => storage_data2(0), - R => '0' - ); -\storage_data2_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(10), - Q => storage_data2(10), - R => '0' - ); -\storage_data2_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(11), - Q => storage_data2(11), - R => '0' - ); -\storage_data2_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(12), - Q => storage_data2(12), - R => '0' - ); -\storage_data2_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(13), - Q => storage_data2(13), - R => '0' - ); -\storage_data2_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(14), - Q => storage_data2(14), - R => '0' - ); -\storage_data2_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(15), - Q => storage_data2(15), - R => '0' - ); -\storage_data2_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(16), - Q => storage_data2(16), - R => '0' - ); -\storage_data2_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(17), - Q => storage_data2(17), - R => '0' - ); -\storage_data2_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(18), - Q => storage_data2(18), - R => '0' - ); -\storage_data2_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(19), - Q => storage_data2(19), - R => '0' - ); -\storage_data2_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(1), - Q => storage_data2(1), - R => '0' - ); -\storage_data2_reg[20]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(20), - Q => storage_data2(20), - R => '0' - ); -\storage_data2_reg[21]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(21), - Q => storage_data2(21), - R => '0' - ); -\storage_data2_reg[22]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(22), - Q => storage_data2(22), - R => '0' - ); -\storage_data2_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(23), - Q => storage_data2(23), - R => '0' - ); -\storage_data2_reg[24]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(24), - Q => storage_data2(24), - R => '0' - ); -\storage_data2_reg[25]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(25), - Q => storage_data2(25), - R => '0' - ); -\storage_data2_reg[26]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(26), - Q => storage_data2(26), - R => '0' - ); -\storage_data2_reg[27]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(27), - Q => storage_data2(27), - R => '0' - ); -\storage_data2_reg[28]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(28), - Q => storage_data2(28), - R => '0' - ); -\storage_data2_reg[29]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(29), - Q => storage_data2(29), - R => '0' - ); -\storage_data2_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(2), - Q => storage_data2(2), - R => '0' - ); -\storage_data2_reg[30]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(30), - Q => storage_data2(30), - R => '0' - ); -\storage_data2_reg[31]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(31), - Q => storage_data2(31), - R => '0' - ); -\storage_data2_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(3), - Q => storage_data2(3), - R => '0' - ); -\storage_data2_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(4), - Q => storage_data2(4), - R => '0' - ); -\storage_data2_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(5), - Q => storage_data2(5), - R => '0' - ); -\storage_data2_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(6), - Q => storage_data2(6), - R => '0' - ); -\storage_data2_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(7), - Q => storage_data2(7), - R => '0' - ); -\storage_data2_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(8), - Q => storage_data2(8), - R => '0' - ); -\storage_data2_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(9), - Q => storage_data2(9), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice is - port ( - aclk : in STD_LOGIC; - aclk2x : in STD_LOGIC; - aresetn : in STD_LOGIC; - aclken : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axis_tlast : in STD_LOGIC; - s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axis_tlast : out STD_LOGIC; - m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute C_AXIS_SIGNAL_SET : integer; - attribute C_AXIS_SIGNAL_SET of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 3; - attribute C_AXIS_TDATA_WIDTH : integer; - attribute C_AXIS_TDATA_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 32; - attribute C_AXIS_TDEST_WIDTH : integer; - attribute C_AXIS_TDEST_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute C_AXIS_TID_WIDTH : integer; - attribute C_AXIS_TID_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute C_AXIS_TUSER_WIDTH : integer; - attribute C_AXIS_TUSER_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute C_FAMILY : string; - attribute C_FAMILY of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is "zynquplus"; - attribute C_NUM_SLR_CROSSINGS : integer; - attribute C_NUM_SLR_CROSSINGS of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_PIPELINES_MASTER : integer; - attribute C_PIPELINES_MASTER of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_PIPELINES_MIDDLE : integer; - attribute C_PIPELINES_MIDDLE of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_PIPELINES_SLAVE : integer; - attribute C_PIPELINES_SLAVE of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_REG_CONFIG : integer; - attribute C_REG_CONFIG of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 8; - attribute DowngradeIPIdentifiedWarnings : string; - attribute DowngradeIPIdentifiedWarnings of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is "yes"; - attribute G_INDX_SS_TDATA : integer; - attribute G_INDX_SS_TDATA of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute G_INDX_SS_TDEST : integer; - attribute G_INDX_SS_TDEST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 6; - attribute G_INDX_SS_TID : integer; - attribute G_INDX_SS_TID of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 5; - attribute G_INDX_SS_TKEEP : integer; - attribute G_INDX_SS_TKEEP of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 3; - attribute G_INDX_SS_TLAST : integer; - attribute G_INDX_SS_TLAST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 4; - attribute G_INDX_SS_TREADY : integer; - attribute G_INDX_SS_TREADY of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute G_INDX_SS_TSTRB : integer; - attribute G_INDX_SS_TSTRB of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 2; - attribute G_INDX_SS_TUSER : integer; - attribute G_INDX_SS_TUSER of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 7; - attribute G_MASK_SS_TDATA : integer; - attribute G_MASK_SS_TDATA of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 2; - attribute G_MASK_SS_TDEST : integer; - attribute G_MASK_SS_TDEST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 64; - attribute G_MASK_SS_TID : integer; - attribute G_MASK_SS_TID of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 32; - attribute G_MASK_SS_TKEEP : integer; - attribute G_MASK_SS_TKEEP of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 8; - attribute G_MASK_SS_TLAST : integer; - attribute G_MASK_SS_TLAST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 16; - attribute G_MASK_SS_TREADY : integer; - attribute G_MASK_SS_TREADY of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute G_MASK_SS_TSTRB : integer; - attribute G_MASK_SS_TSTRB of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 4; - attribute G_MASK_SS_TUSER : integer; - attribute G_MASK_SS_TUSER of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 128; - attribute G_TASK_SEVERITY_ERR : integer; - attribute G_TASK_SEVERITY_ERR of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 2; - attribute G_TASK_SEVERITY_INFO : integer; - attribute G_TASK_SEVERITY_INFO of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute G_TASK_SEVERITY_WARNING : integer; - attribute G_TASK_SEVERITY_WARNING of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute P_TPAYLOAD_WIDTH : integer; - attribute P_TPAYLOAD_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 32; -end axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice; - -architecture STRUCTURE of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice is - signal \\ : STD_LOGIC; - signal areset_r : STD_LOGIC; - signal areset_r_i_1_n_0 : STD_LOGIC; -begin - m_axis_tdest(0) <= \\; - m_axis_tid(0) <= \\; - m_axis_tkeep(3) <= \\; - m_axis_tkeep(2) <= \\; - m_axis_tkeep(1) <= \\; - m_axis_tkeep(0) <= \\; - m_axis_tlast <= \\; - m_axis_tstrb(3) <= \\; - m_axis_tstrb(2) <= \\; - m_axis_tstrb(1) <= \\; - m_axis_tstrb(0) <= \\; - m_axis_tuser(0) <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -areset_r_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => aresetn, - O => areset_r_i_1_n_0 - ); -areset_r_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => areset_r_i_1_n_0, - Q => areset_r, - R => '0' - ); -axisc_register_slice_0: entity work.axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice - port map ( - Q(0) => m_axis_tvalid, - aclk => aclk, - areset_r => areset_r, - m_axis_tdata(31 downto 0) => m_axis_tdata(31 downto 0), - m_axis_tready => m_axis_tready, - s_axis_tdata(31 downto 0) => s_axis_tdata(31 downto 0), - s_axis_tready => s_axis_tready, - s_axis_tvalid => s_axis_tvalid - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_register_slice_32 is - port ( - aclk : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of axis_register_slice_32 : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of axis_register_slice_32 : entity is "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}"; - attribute DowngradeIPIdentifiedWarnings : string; - attribute DowngradeIPIdentifiedWarnings of axis_register_slice_32 : entity is "yes"; - attribute X_CORE_INFO : string; - attribute X_CORE_INFO of axis_register_slice_32 : entity is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2"; -end axis_register_slice_32; - -architecture STRUCTURE of axis_register_slice_32 is - signal NLW_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_AXIS_SIGNAL_SET : integer; - attribute C_AXIS_SIGNAL_SET of inst : label is 3; - attribute C_AXIS_TDATA_WIDTH : integer; - attribute C_AXIS_TDATA_WIDTH of inst : label is 32; - attribute C_AXIS_TDEST_WIDTH : integer; - attribute C_AXIS_TDEST_WIDTH of inst : label is 1; - attribute C_AXIS_TID_WIDTH : integer; - attribute C_AXIS_TID_WIDTH of inst : label is 1; - attribute C_AXIS_TUSER_WIDTH : integer; - attribute C_AXIS_TUSER_WIDTH of inst : label is 1; - attribute C_FAMILY : string; - attribute C_FAMILY of inst : label is "zynquplus"; - attribute C_NUM_SLR_CROSSINGS : integer; - attribute C_NUM_SLR_CROSSINGS of inst : label is 0; - attribute C_PIPELINES_MASTER : integer; - attribute C_PIPELINES_MASTER of inst : label is 0; - attribute C_PIPELINES_MIDDLE : integer; - attribute C_PIPELINES_MIDDLE of inst : label is 0; - attribute C_PIPELINES_SLAVE : integer; - attribute C_PIPELINES_SLAVE of inst : label is 0; - attribute C_REG_CONFIG : integer; - attribute C_REG_CONFIG of inst : label is 8; - attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; - attribute G_INDX_SS_TDATA : integer; - attribute G_INDX_SS_TDATA of inst : label is 1; - attribute G_INDX_SS_TDEST : integer; - attribute G_INDX_SS_TDEST of inst : label is 6; - attribute G_INDX_SS_TID : integer; - attribute G_INDX_SS_TID of inst : label is 5; - attribute G_INDX_SS_TKEEP : integer; - attribute G_INDX_SS_TKEEP of inst : label is 3; - attribute G_INDX_SS_TLAST : integer; - attribute G_INDX_SS_TLAST of inst : label is 4; - attribute G_INDX_SS_TREADY : integer; - attribute G_INDX_SS_TREADY of inst : label is 0; - attribute G_INDX_SS_TSTRB : integer; - attribute G_INDX_SS_TSTRB of inst : label is 2; - attribute G_INDX_SS_TUSER : integer; - attribute G_INDX_SS_TUSER of inst : label is 7; - attribute G_MASK_SS_TDATA : integer; - attribute G_MASK_SS_TDATA of inst : label is 2; - attribute G_MASK_SS_TDEST : integer; - attribute G_MASK_SS_TDEST of inst : label is 64; - attribute G_MASK_SS_TID : integer; - attribute G_MASK_SS_TID of inst : label is 32; - attribute G_MASK_SS_TKEEP : integer; - attribute G_MASK_SS_TKEEP of inst : label is 8; - attribute G_MASK_SS_TLAST : integer; - attribute G_MASK_SS_TLAST of inst : label is 16; - attribute G_MASK_SS_TREADY : integer; - attribute G_MASK_SS_TREADY of inst : label is 1; - attribute G_MASK_SS_TSTRB : integer; - attribute G_MASK_SS_TSTRB of inst : label is 4; - attribute G_MASK_SS_TUSER : integer; - attribute G_MASK_SS_TUSER of inst : label is 128; - attribute G_TASK_SEVERITY_ERR : integer; - attribute G_TASK_SEVERITY_ERR of inst : label is 2; - attribute G_TASK_SEVERITY_INFO : integer; - attribute G_TASK_SEVERITY_INFO of inst : label is 0; - attribute G_TASK_SEVERITY_WARNING : integer; - attribute G_TASK_SEVERITY_WARNING of inst : label is 1; - attribute P_TPAYLOAD_WIDTH : integer; - attribute P_TPAYLOAD_WIDTH of inst : label is 32; - attribute X_INTERFACE_INFO : string; - attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK"; - attribute X_INTERFACE_PARAMETER : string; - attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST"; - attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; - attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; - attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; - attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; - attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; - attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; - attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; -begin -inst: entity work.axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice - port map ( - aclk => aclk, - aclk2x => '0', - aclken => '1', - aresetn => aresetn, - m_axis_tdata(31 downto 0) => m_axis_tdata(31 downto 0), - m_axis_tdest(0) => NLW_inst_m_axis_tdest_UNCONNECTED(0), - m_axis_tid(0) => NLW_inst_m_axis_tid_UNCONNECTED(0), - m_axis_tkeep(3 downto 0) => NLW_inst_m_axis_tkeep_UNCONNECTED(3 downto 0), - m_axis_tlast => NLW_inst_m_axis_tlast_UNCONNECTED, - m_axis_tready => m_axis_tready, - m_axis_tstrb(3 downto 0) => NLW_inst_m_axis_tstrb_UNCONNECTED(3 downto 0), - m_axis_tuser(0) => NLW_inst_m_axis_tuser_UNCONNECTED(0), - m_axis_tvalid => m_axis_tvalid, - s_axis_tdata(31 downto 0) => s_axis_tdata(31 downto 0), - s_axis_tdest(0) => '0', - s_axis_tid(0) => '0', - s_axis_tkeep(3 downto 0) => B"1111", - s_axis_tlast => '1', - s_axis_tready => s_axis_tready, - s_axis_tstrb(3 downto 0) => B"1111", - s_axis_tuser(0) => '0', - s_axis_tvalid => s_axis_tvalid - ); -end STRUCTURE; diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v deleted file mode 100644 index a8ddc84..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -// Date : Thu Apr 23 10:08:03 2026 -// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS -// Command : write_verilog -force -mode synth_stub -rename_top axis_register_slice_32 -prefix -// axis_register_slice_32_ axis_register_slice_32_stub.v -// Design : axis_register_slice_32 -// Purpose : Stub declaration of top-level module interface -// Device : xczu19eg-ffvc1760-2-i -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *) -module axis_register_slice_32(aclk, aresetn, s_axis_tvalid, s_axis_tready, - s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata) -/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]" */ -/* synthesis syn_force_seq_prim="aclk" */; - input aclk /* synthesis syn_isclock = 1 */; - input aresetn; - input s_axis_tvalid; - output s_axis_tready; - input [31:0]s_axis_tdata; - output m_axis_tvalid; - input m_axis_tready; - output [31:0]m_axis_tdata; -endmodule diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl deleted file mode 100644 index cf52608..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl +++ /dev/null @@ -1,38 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 --- Date : Thu Apr 23 10:08:04 2026 --- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS --- Command : write_vhdl -force -mode synth_stub -rename_top axis_register_slice_32 -prefix --- axis_register_slice_32_ axis_register_slice_32_stub.vhdl --- Design : axis_register_slice_32 --- Purpose : Stub declaration of top-level module interface --- Device : xczu19eg-ffvc1760-2-i --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity axis_register_slice_32 is - Port ( - aclk : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - -end axis_register_slice_32; - -architecture stub of axis_register_slice_32 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2"; -begin -end; diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh deleted file mode 100755 index 9be387b..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh +++ /dev/null @@ -1,336 +0,0 @@ -// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// Global Parameters: -// -// Functions: -// f_clogb2 -// f_gcd -// f_lcm -// f_get_tdata_indx -// f_get_tstrb_indx -// f_get_tkeep_indx -// f_get_tlast_indx -// f_get_tid_indx -// f_get_tdest_indx -// f_get_tuser_indx -// f_payload_width -// Tasks: -// t_display_tdata_error -//-------------------------------------------------------------------------- -/////////////////////////////////////////////////////////////////////////////// -// BEGIN Global Parameters -/////////////////////////////////////////////////////////////////////////////// -// Define Signal Set indices -localparam G_INDX_SS_TREADY = 0; -localparam G_INDX_SS_TDATA = 1; -localparam G_INDX_SS_TSTRB = 2; -localparam G_INDX_SS_TKEEP = 3; -localparam G_INDX_SS_TLAST = 4; -localparam G_INDX_SS_TID = 5; -localparam G_INDX_SS_TDEST = 6; -localparam G_INDX_SS_TUSER = 7; -localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY; -localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA; -localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB; -localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP; -localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST; -localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ; -localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST; -localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER; - -// Task DRC error levels -localparam G_TASK_SEVERITY_ERR = 2; -localparam G_TASK_SEVERITY_WARNING = 1; -localparam G_TASK_SEVERITY_INFO = 0; - -/////////////////////////////////////////////////////////////////////////////// -// BEGIN Functions -/////////////////////////////////////////////////////////////////////////////// -// ceiling logb2 - function integer f_clogb2 (input integer size); - integer s; - begin - s = size; - s = s - 1; - for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) - s = s >> 1; - end - endfunction // clogb2 - - // Calculates the Greatest Common Divisor between two integers using the - // euclidean algorithm. - function automatic integer f_gcd ( - input integer a, - input integer b - ); - begin : main - if (a == 0) begin - f_gcd = b; - end else if (b == 0) begin - f_gcd = a; - end else if (a > b) begin - f_gcd = f_gcd(a % b, b); - end else begin - f_gcd = f_gcd(a, b % a); - end - end - endfunction - - // Calculates the Lowest Common Denominator between two integers - function integer f_lcm ( - input integer a, - input integer b - ); - begin : main - f_lcm = ( a / f_gcd(a, b)) * b; - end - endfunction - - // Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tdata_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - f_get_tdata_indx = 0; - end - endfunction - - // Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tstrb_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST); - // If TDATA exists, then add its width to its base to get the tstrb index - f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx; - end - endfunction - - // Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tkeep_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST); - f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx; - end - endfunction - - // Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tlast_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST); - f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx; - end - endfunction - - // Returns back the index to the tid portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tid_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST); - f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx; - end - endfunction - - // Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tdest_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST); - f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx; - end - endfunction - - // Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tuser_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST); - f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx; - end - endfunction - - // Payload is the sum of all the AXIS signals present except for - // TREADY/TVALID - function integer f_payload_width ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST); - f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx; - // Ensure that the return value is never less than 1 - f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width; - end - endfunction - - task t_check_tdata_width( - input integer data_width, - input [8*80-1:0] var_name, - input [8*80-1:0] inst_name, - input integer severity_lvl, - output integer ret_val - ); - // Severity levels: - // 0 = INFO - // 1 = WARNING - // 2 = ERROR - begin : t_check_tdata_width - if (data_width%8 != 0) begin - // 000 1 2 3 4 5 6 7 8 - // 012 0 0 0 0 0 0 0 0 - if (severity_lvl >= 2) begin - $display("ERROR: %m::%s", inst_name); - end else if (severity_lvl == 1) begin - $display("WARNING: %m::%s", inst_name); - end else begin - $display("INFO: %m::%s", inst_name); - end - $display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width); - $display(" AXI4-Stream data width is only defined for byte multiples. See the "); - $display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more"); - $display(" information."); - ret_val = 1; - end else begin - ret_val = 0; - end - end - endtask - - task t_check_tuser_width( - input integer tuser_width, - input [8*80-1:0] tuser_name, - input integer tdata_width, - input [8*80-1:0] tdata_name, - input [8*80-1:0] inst_name, - input integer severity_lvl, - output integer ret_val - ); - // Severity levels: - // 0 = INFO - // 1 = WARNING - // 2 = ERROR - begin : t_check_tuser_width - integer tdata_bytes; - tdata_bytes = tdata_width/8; - if ((tuser_width%tdata_bytes) != 0) begin - // 000 1 2 3 4 5 6 7 8 - // 012 0 0 0 0 0 0 0 0 - if (severity_lvl >= 2) begin - $display("ERROR: %m::%s", inst_name); - end else if (severity_lvl == 1) begin - $display("WARNING: %m::%s", inst_name); - end else begin - $display("INFO: %m::%s", inst_name); - end - $display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width); - $display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width); - $display(" TUSER width in this module is only defined when the TUSER is the"); - $display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0"); - $display(" Section 2.1, 2.3.3 and 2.8 for more information. "); - ret_val = 1; - end else begin - ret_val = 0; - end - end - endtask - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v deleted file mode 100755 index 33ddf3c..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v +++ /dev/null @@ -1,1318 +0,0 @@ -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -//----------------------------------------------------------------------------- -// -// Description: -// Optimized Mux using MUXF7/8. -// Any mux ratio. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// mux_enc -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V -`define AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V -`timescale 1ps/1ps - - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_mux_enc # - ( - parameter C_FAMILY = "rtl", - // FPGA Family. Current version: virtex6 or spartan6. - parameter integer C_RATIO = 4, - // Mux select ratio. Can be any binary value (>= 1) - parameter integer C_SEL_WIDTH = 2, - // Log2-ceiling of C_RATIO (>= 1) - parameter integer C_DATA_WIDTH = 1 - // Data width for comparator (>= 1) - ) - ( - input wire [C_SEL_WIDTH-1:0] S, - input wire [C_RATIO*C_DATA_WIDTH-1:0] A, - output wire [C_DATA_WIDTH-1:0] O, - input wire OE - ); - - wire [C_DATA_WIDTH-1:0] o_i; - genvar bit_cnt; - - function [C_DATA_WIDTH-1:0] f_mux - ( - input [C_SEL_WIDTH-1:0] s, - input [C_RATIO*C_DATA_WIDTH-1:0] a - ); - integer i; - reg [C_RATIO*C_DATA_WIDTH-1:0] carry; - begin - carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0]; - for (i=1;i 17, use RTL - assign o_i = f_mux(S, A); - endcase - end // gen_fpga - endgenerate -endmodule - -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_infrastructure_v1_1_1_util_aclken_converter -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V -`define AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_aclken_converter # ( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_PAYLOAD_WIDTH = 32, - parameter integer C_S_ACLKEN_CAN_TOGGLE = 1, - parameter integer C_M_ACLKEN_CAN_TOGGLE = 1 - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // Slave side - input wire ACLK, - input wire ARESETN, - - input wire S_ACLKEN, - input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD, - input wire S_VALID, - output wire S_READY, - - // Master side - input wire M_ACLKEN, - output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD, - output wire M_VALID, - input wire M_READY -); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - -// State machine states -localparam SM_NOT_READY = 3'b000; -localparam SM_EMPTY = 3'b001; -localparam SM_R0_NOT_READY = 3'b010; -localparam SM_R0 = 3'b011; -localparam SM_R1 = 3'b100; -localparam SM_FULL = 3'b110; - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -wire s_aclken_i; -wire m_aclken_i; -reg areset; - -reg [2:0] state = SM_NOT_READY; - -// r0 is the output register -reg [C_PAYLOAD_WIDTH-1:0] r0; -wire load_r0; -wire load_r0_from_r1; - -// r1 is the overflow register -reg [C_PAYLOAD_WIDTH-1:0] r1; -wire load_r1; -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - -assign s_aclken_i = C_S_ACLKEN_CAN_TOGGLE ? S_ACLKEN : 1'b1; -assign m_aclken_i = C_M_ACLKEN_CAN_TOGGLE ? M_ACLKEN : 1'b1; - -always @(posedge ACLK) begin - areset <= ~ARESETN; -end - -// Valid/Ready outputs encoded into state machine. -assign S_READY = (state == SM_NOT_READY ) ? 1'b0 : state[0] ; -assign M_VALID = (state == SM_NOT_READY ) ? 1'b0 : state[1]; - -// State machine: Controls outputs and hold register state info -always @(posedge ACLK) begin - if (areset) begin - state <= SM_NOT_READY; - end - else begin - case (state) - // De-assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied - SM_NOT_READY: begin - if (s_aclken_i) begin - state <= SM_EMPTY; - end - else begin - state <= state; - end - end - - // Assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied - SM_EMPTY: begin - if (s_aclken_i & S_VALID & m_aclken_i) begin - state <= SM_R0; - end - else if (s_aclken_i & S_VALID & ~m_aclken_i) begin - state <= SM_R1; - end - else begin - state <= state; - end - end - - // Assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied - SM_R0: begin - if ((m_aclken_i & M_READY) & ~(s_aclken_i & S_VALID)) begin - state <= SM_EMPTY; - end - else if (~(m_aclken_i & M_READY) & (s_aclken_i & S_VALID)) begin - state <= SM_FULL; - end - else begin - state <= state; - end - end - - // De-assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied - SM_R0_NOT_READY: begin - if (s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_EMPTY; - end - else if (~s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_NOT_READY; - end - else if (s_aclken_i) begin - state <= SM_R0; - end - else begin - state <= state; - end - end - - // De-assert s_ready, De-assert m_valid, R0 unoccupied, R1 occupied - SM_R1: begin - if (~s_aclken_i & m_aclken_i) begin - state <= SM_R0_NOT_READY; - end - else if (s_aclken_i & m_aclken_i) begin - state <= SM_R0; - end - else begin - state <= state; - end - end - - // De-assert s_ready, De-assert m_valid, R0 occupied, R1 occupied - SM_FULL: begin - if (~s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_R0_NOT_READY; - end - else if (s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_R0; - end - else begin - state <= state; - end - end - - default: begin - state <= SM_NOT_READY; - end - endcase - end -end - -assign M_PAYLOAD = r0; - -always @(posedge ACLK) begin - if (m_aclken_i) begin - r0 <= ~load_r0 ? r0 : - load_r0_from_r1 ? r1 : - S_PAYLOAD ; - end -end - -assign load_r0 = (state == SM_EMPTY) - | (state == SM_R1) - | ((state == SM_R0) & M_READY) - | ((state == SM_FULL) & M_READY); - -assign load_r0_from_r1 = (state == SM_R1) | (state == SM_FULL); - -always @(posedge ACLK) begin - r1 <= ~load_r1 ? r1 : S_PAYLOAD; -end - -assign load_r1 = (state == SM_EMPTY) | (state == SM_R0); - - -endmodule // axis_infrastructure_v1_1_1_util_aclken_converter - -`default_nettype wire -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Verilog-standard: Verilog 2001 -//////////////////////////////////////////////////////////// -// -// Structure: -// axis_infrastructure_v1_1_1_util_aclken_converter_wrapper -// axis_infrastructure_v1_1_1_util_axis2_vector -// axis_infrastructure_v1_1_1_util_aclken_converter -// axis_infrastructure_v1_1_1_util_vector2axis -// -//////////////////////////////////////////////////////////// -`ifndef axis_infrastructure_v1_1_1_UTIL_ACLKEN_CONVERTER_WRAPPER_V -`define axis_infrastructure_v1_1_1_UTIL_ACLKEN_CONVERTER_WRAPPER_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_aclken_converter_wrapper # ( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_TDATA_WIDTH = 32, - parameter integer C_TID_WIDTH = 1, - parameter integer C_TDEST_WIDTH = 1, - parameter integer C_TUSER_WIDTH = 1, - parameter [31:0] C_SIGNAL_SET = 32'hFF, - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - parameter integer C_S_ACLKEN_CAN_TOGGLE = 1, - parameter integer C_M_ACLKEN_CAN_TOGGLE = 1 - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // Slave side - input wire ACLK, - input wire ARESETN, - input wire S_ACLKEN, - input wire S_VALID, - output wire S_READY, - input wire [C_TDATA_WIDTH-1:0] S_TDATA, - input wire [C_TDATA_WIDTH/8-1:0] S_TSTRB, - input wire [C_TDATA_WIDTH/8-1:0] S_TKEEP, - input wire S_TLAST, - input wire [C_TID_WIDTH-1:0] S_TID, - input wire [C_TDEST_WIDTH-1:0] S_TDEST, - input wire [C_TUSER_WIDTH-1:0] S_TUSER, - - input wire M_ACLKEN, - output wire M_VALID, - input wire M_READY, - output wire [C_TDATA_WIDTH-1:0] M_TDATA, - output wire [C_TDATA_WIDTH/8-1:0] M_TSTRB, - output wire [C_TDATA_WIDTH/8-1:0] M_TKEEP, - output wire M_TLAST, - output wire [C_TID_WIDTH-1:0] M_TID, - output wire [C_TDEST_WIDTH-1:0] M_TDEST, - output wire [C_TUSER_WIDTH-1:0] M_TUSER -); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - -localparam integer P_TPAYLOAD_WIDTH = f_payload_width(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -wire [P_TPAYLOAD_WIDTH-1:0] s_tpayload; -wire [P_TPAYLOAD_WIDTH-1:0] m_tpayload; - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - -axis_infrastructure_v1_1_1_util_axis2vector #( - .C_TDATA_WIDTH ( C_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_SIGNAL_SET ) -) -util_axis2vector_0 ( - .TDATA ( S_TDATA ) , - .TSTRB ( S_TSTRB ) , - .TKEEP ( S_TKEEP ) , - .TLAST ( S_TLAST ) , - .TID ( S_TID ) , - .TDEST ( S_TDEST ) , - .TUSER ( S_TUSER ) , - .TPAYLOAD ( s_tpayload ) -); - -generate -if (C_S_ACLKEN_CAN_TOGGLE | C_M_ACLKEN_CAN_TOGGLE) begin : gen_aclken_converter - axis_infrastructure_v1_1_1_util_aclken_converter #( - .C_PAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_S_ACLKEN_CAN_TOGGLE ( C_S_ACLKEN_CAN_TOGGLE ) , - .C_M_ACLKEN_CAN_TOGGLE ( C_M_ACLKEN_CAN_TOGGLE ) - ) - s_util_aclken_converter_0 ( - .ACLK ( ACLK ) , - .ARESETN ( ARESETN ) , - .S_ACLKEN ( S_ACLKEN ) , - .S_PAYLOAD ( s_tpayload ) , - .S_VALID ( S_VALID ) , - .S_READY ( S_READY ) , - .M_ACLKEN ( M_ACLKEN ) , - .M_PAYLOAD ( m_tpayload ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); -end -else begin : gen_aclken_passthru - assign m_tpayload = s_tpayload; - assign M_VALID = S_VALID; - assign S_READY = M_READY; -end -endgenerate - -axis_infrastructure_v1_1_1_util_vector2axis #( - .C_TDATA_WIDTH ( C_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_SIGNAL_SET ) -) -util_vector2axis_0 ( - .TPAYLOAD ( m_tpayload ) , - .TDATA ( M_TDATA ) , - .TSTRB ( M_TSTRB ) , - .TKEEP ( M_TKEEP ) , - .TLAST ( M_TLAST ) , - .TID ( M_TID ) , - .TDEST ( M_TDEST ) , - .TUSER ( M_TUSER ) -); - -endmodule // axis_infrastructure_v1_1_1_util_aclken_converter_wrapper - -`default_nettype wire -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// axis to vector -// A generic module to merge all axis 'data' signals into one signal called payload. -// This is strictly wires, so no clk, reset, aclken, valid/ready are required. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_infrastructure_v1_1_1_util_axis2vector -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V -`define AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_axis2vector # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_TDATA_WIDTH = 32, - parameter integer C_TID_WIDTH = 1, - parameter integer C_TDEST_WIDTH = 1, - parameter integer C_TUSER_WIDTH = 1, - parameter integer C_TPAYLOAD_WIDTH = 44, - parameter [31:0] C_SIGNAL_SET = 32'hFF - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // inputs - input wire [C_TDATA_WIDTH-1:0] TDATA, - input wire [C_TDATA_WIDTH/8-1:0] TSTRB, - input wire [C_TDATA_WIDTH/8-1:0] TKEEP, - input wire TLAST, - input wire [C_TID_WIDTH-1:0] TID, - input wire [C_TDEST_WIDTH-1:0] TDEST, - input wire [C_TUSER_WIDTH-1:0] TUSER, - - // outputs - output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD - ); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// -localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// -generate - if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata - assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] = TDATA; - end else begin : no_gen_tdata - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb - assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB; - end else begin : no_gen_tstrb - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep - assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP; - end else begin : no_gen_tkeep - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast - assign TPAYLOAD[P_TLAST_INDX+:1] = TLAST; - end else begin : no_gen_tlast - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid - assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] = TID; - end else begin : no_gen_tid - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest - assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] = TDEST; - end else begin : no_gen_tdest - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser - assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] = TUSER; - end else begin : no_gen_tuser - // Do nothing - end -endgenerate -endmodule - -`default_nettype wire -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// axis to vector -// A generic module to unmerge all axis 'data' signals from payload. -// This is strictly wires, so no clk, reset, aclken, valid/ready are required. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_infrastructure_v1_1_1_util_vector2axis -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V -`define AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_vector2axis # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_TDATA_WIDTH = 32, - parameter integer C_TID_WIDTH = 1, - parameter integer C_TDEST_WIDTH = 1, - parameter integer C_TUSER_WIDTH = 1, - parameter integer C_TPAYLOAD_WIDTH = 44, - parameter [31:0] C_SIGNAL_SET = 32'hFF - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // outputs - input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD, - - // inputs - output wire [C_TDATA_WIDTH-1:0] TDATA, - output wire [C_TDATA_WIDTH/8-1:0] TSTRB, - output wire [C_TDATA_WIDTH/8-1:0] TKEEP, - output wire TLAST, - output wire [C_TID_WIDTH-1:0] TID, - output wire [C_TDEST_WIDTH-1:0] TDEST, - output wire [C_TUSER_WIDTH-1:0] TUSER - ); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// -localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// -generate - if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata - assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ; - end - else begin : no_gen_tdata - assign TDATA = {C_TDATA_WIDTH{1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb - assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8]; - end - else begin : no_gen_tstrb - assign TSTRB = {(C_TDATA_WIDTH/8){1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep - assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8]; - end - else begin : no_gen_tkeep - assign TKEEP = {(C_TDATA_WIDTH/8){1'b1}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast - assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ; - end - else begin : no_gen_tlast - assign TLAST = 1'b0; - end - if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid - assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ; - end - else begin : no_gen_tid - assign TID = {C_TID_WIDTH{1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest - assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ; - end - else begin : no_gen_tdest - assign TDEST = {C_TDEST_WIDTH{1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser - assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ; - end - else begin : no_gen_tuser - assign TUSER = {C_TUSER_WIDTH{1'b0}}; - end -endgenerate -endmodule - -`default_nettype wire -`endif - - -// (c) Copyright 2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -//***************************************************************************** -// Description -// This module instantiates the clock synchronization logic. It passes the -// incoming signal through two flops to ensure metastability. -// -//***************************************************************************** -`timescale 1ps / 1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_clock_synchronizer # ( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_NUM_STAGES = 4 -) -( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - input wire clk, - input wire synch_in , - output wire synch_out -); - -//////////////////////////////////////////////////////////////////////////////// -// Local Parameters -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -xpm_cdc_single #( - .DEST_SYNC_FF ( C_NUM_STAGES ) , - .SRC_INPUT_REG ( 0 ) , - .SIM_ASSERT_CHK ( 0 ) -) -inst_xpm_cdc_single ( - .src_clk ( 1'b0 ) , - .src_in ( synch_in ) , - .dest_out ( synch_out ) , - .dest_clk ( clk ) -); - -endmodule - -`default_nettype wire - - -// (c) Copyright 2014, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -/////////////////////////////////////////////////////////////////////////////// -// -// File name: axis_infrastructure_v1_1_1_cdc_handshake -// -/////////////////////////////////////////////////////////////////////////////// -`timescale 1ps/1ps -`default_nettype none - -module axis_infrastructure_v1_1_1_cdc_handshake # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_WIDTH = 32, - parameter integer C_NUM_SYNCHRONIZER_STAGES = 2 -) -( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - input wire from_clk, - input wire req, - output wire ack, - input wire [C_WIDTH-1:0] data_in, - - input wire to_clk, - output wire data_valid, - output wire [C_WIDTH-1:0] data_out -); - -///////////////////////////////////////////////////////////////////////////// -// Functions -///////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -/////////////////////////////////////////////////////////////////////////////// -xpm_cdc_handshake #( - .WIDTH ( C_WIDTH ) , - .DEST_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) , - .SRC_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) , - .DEST_EXT_HSK ( 0 ) , - .SIM_ASSERT_CHK ( 0 ) -) -inst_xpm_cdc_handshake ( - .src_in ( data_in ) , - .src_send ( req ) , - .src_rcv ( ack ) , - .src_clk ( from_clk ) , - .dest_out ( data_out ) , - .dest_req ( data_valid ) , - .dest_ack ( 1'b0 ) , - .dest_clk ( to_clk ) -); - -endmodule // axis_infrastructure_v1_1_1_cdc_handshake - -`default_nettype wire - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_register_slice_v1_1_vl_rfs.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_register_slice_v1_1_vl_rfs.v deleted file mode 100755 index ebea64a..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_register_slice_v1_1_vl_rfs.v +++ /dev/null @@ -1,2998 +0,0 @@ -// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps -`default_nettype none - -module axis_register_slice_v1_1_29_tdm_sample ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - input wire slow_clk, - input wire fast_clk, - output wire sample_cycle -); - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -reg slow_clk_div2 = 1'b0; -reg posedge_finder_first; -reg posedge_finder_second; -wire first_edge; -wire second_edge; -reg sample_cycle_d; -(* shreg_extract = "no" *) reg sample_cycle_r; - - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - always @(posedge slow_clk) begin - slow_clk_div2 <= ~slow_clk_div2; - end - - // Find matching rising edges by clocking slow_clk_div2 onto faster clock - always @(posedge fast_clk) begin - posedge_finder_first <= slow_clk_div2; - end - always @(posedge fast_clk) begin - posedge_finder_second <= ~slow_clk_div2; - end - - assign first_edge = slow_clk_div2 & ~posedge_finder_first; - assign second_edge = ~slow_clk_div2 & ~posedge_finder_second; - - always @(*) begin - sample_cycle_d = first_edge | second_edge; - end - - always @(posedge fast_clk) begin - sample_cycle_r <= sample_cycle_d; - end - - assign sample_cycle = sample_cycle_r; - -endmodule // tdm_sample - -`default_nettype wire - - -// (c) Copyright 2019, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - -module axis_register_slice_v1_1_29_test_master # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Master side - (* dont_touch="true" *) output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - (* dont_touch="true" *) output wire M_VALID, - input wire M_READY - ); - - //********************************************** - reg [C_DATA_WIDTH-1:0] payld_i = {C_DATA_WIDTH{1'b0}}; - reg tvalid_i = 1'b0; - - assign M_VALID = tvalid_i; - assign M_PAYLOAD_DATA = payld_i; - - always @(posedge ACLK) begin - if (ARESET) begin - tvalid_i <= 1'b0; - payld_i <= {C_DATA_WIDTH{1'b0}}; - end else if (ACLKEN) begin - if (M_READY && tvalid_i) begin - tvalid_i <= 1'b0; - payld_i <= {payld_i[C_DATA_WIDTH-2 : 0], ~payld_i[C_DATA_WIDTH-1]}; - end else begin - tvalid_i <= 1'b1; - end - end - end - -endmodule - -`default_nettype wire - - -// (c) Copyright 2019, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - -module axis_register_slice_v1_1_29_test_slave # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - (* dont_touch="true" *) output wire S_READY - - ); - - reg valid_d = 1'b0; - reg [C_DATA_WIDTH-1:0] payld_i = {C_DATA_WIDTH{1'b0}}; - reg ready_i = 1'b0; - - assign S_READY = ready_i; - - always @(posedge ACLK) begin - if(ARESET) begin - ready_i <= 1'b0; - payld_i <= {C_DATA_WIDTH{1'b0}}; - end else if (ACLKEN) begin - valid_d <= S_VALID; - if (S_VALID & ready_i) begin - payld_i <= S_PAYLOAD_DATA; - ready_i <= 1'b0; - end else begin - payld_i <= payld_i>>1; - ready_i <= payld_i[0] ? valid_d : S_VALID; - end - end - end - -endmodule - - - -// (c) Copyright 2010-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Register Slice -// Generic single-channel AXI pipeline register on forward and/or reverse signal path -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axic_register_slice_slr -// -//-------------------------------------------------------------------------- - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_multi_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_DATA_WIDTH = 32, - parameter integer C_NUM_SLR_CROSSINGS = 0, - parameter integer C_PIPELINES_MASTER = 0, - parameter integer C_PIPELINES_SLAVE = 0, - parameter integer C_PIPELINES_MIDDLE = 0 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - localparam integer P_MULTI_SLR = 15; - localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2; - localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2; - localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0); - - generate - - if (C_NUM_SLR_CROSSINGS==0) begin : single_slr - - axis_register_slice_v1_1_29_single_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MASTER) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr - - wire [C_DATA_WIDTH-1:0] src_payload; - wire src_handshake; - wire src_reset; - wire src_ready; - - axis_register_slice_v1_1_29_source_region_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES ( C_PIPELINES_MASTER) , - .C_REG_CONFIG ( P_MULTI_SLR ) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .laguna_m_reset_out ( src_reset ) , - .laguna_m_payload ( src_payload ) , - .laguna_m_handshake ( src_handshake ) , - .laguna_m_ready ( src_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( P_MULTI_SLR ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_SLAVE), - .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY) - ) - slr_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .laguna_s_reset_in ( src_reset ) , - .laguna_s_payload ( src_payload ) , - .laguna_s_handshake ( src_handshake ) , - .laguna_s_ready ( src_ready ) , - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr - - wire [C_DATA_WIDTH-1:0] src_payload; - wire src_handshake; - wire src_ready; - wire src_reset; - wire [C_DATA_WIDTH-1:0] dest_payload; - wire dest_handshake; - wire dest_ready; - wire dest_reset; - - axis_register_slice_v1_1_29_source_region_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_MASTER) , - .C_REG_CONFIG ( P_MULTI_SLR ) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .laguna_m_reset_out ( src_reset ) , - .laguna_m_payload ( src_payload ) , - .laguna_m_handshake ( src_handshake ) , - .laguna_m_ready ( src_ready ) - ); - - axis_register_slice_v1_1_29_middle_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MIDDLE), - .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY) - ) - slr_middle ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .laguna_s_reset_in ( src_reset ) , - .laguna_s_payload ( src_payload ) , - .laguna_s_handshake ( src_handshake ) , - .laguna_s_ready ( src_ready ) , - .laguna_m_reset_out ( dest_reset ) , - .laguna_m_payload ( dest_payload ) , - .laguna_m_handshake ( dest_handshake ) , - .laguna_m_ready ( dest_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( P_MULTI_SLR ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_SLAVE), - .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY) - ) - slr_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .laguna_s_reset_in ( dest_reset ) , - .laguna_s_payload ( dest_payload ) , - .laguna_s_handshake ( dest_handshake ) , - .laguna_s_ready ( dest_ready ) , - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr - - wire [C_DATA_WIDTH-1:0] src_payload; - wire src_handshake; - wire src_ready; - wire src_reset; - wire [C_DATA_WIDTH-1:0] mid_payload; - wire mid_handshake; - wire mid_ready; - wire mid_reset; - wire [C_DATA_WIDTH-1:0] dest_payload; - wire dest_handshake; - wire dest_ready; - wire dest_reset; - - axis_register_slice_v1_1_29_source_region_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_MASTER) , - .C_REG_CONFIG ( P_MULTI_SLR ) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .laguna_m_reset_out ( src_reset ) , - .laguna_m_payload ( src_payload ) , - .laguna_m_handshake ( src_handshake ) , - .laguna_m_ready ( src_ready ) - ); - - axis_register_slice_v1_1_29_middle_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MIDDLE), - .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY) - ) - slr_middle_master ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .laguna_s_reset_in ( src_reset ) , - .laguna_s_payload ( src_payload ) , - .laguna_s_handshake ( src_handshake ) , - .laguna_s_ready ( src_ready ) , - .laguna_m_reset_out ( mid_reset ) , - .laguna_m_payload ( mid_payload ) , - .laguna_m_handshake ( mid_handshake ) , - .laguna_m_ready ( mid_ready ) - ); - - axis_register_slice_v1_1_29_middle_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MIDDLE), - .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY) - ) - slr_middle_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .laguna_s_reset_in ( mid_reset ) , - .laguna_s_payload ( mid_payload ) , - .laguna_s_handshake ( mid_handshake ) , - .laguna_s_ready ( mid_ready ) , - .laguna_m_reset_out ( dest_reset ) , - .laguna_m_payload ( dest_payload ) , - .laguna_m_handshake ( dest_handshake ) , - .laguna_m_ready ( dest_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( P_MULTI_SLR ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_SLAVE), - .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY) - ) - slr_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .laguna_s_reset_in ( dest_reset ) , - .laguna_s_payload ( dest_payload ) , - .laguna_s_handshake ( dest_handshake ) , - .laguna_s_ready ( dest_ready ) , - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end - -endgenerate -endmodule // multi_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_middle_region_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_DATA_WIDTH = 32, - parameter integer C_PIPELINES = 0, - parameter integer C_SOURCE_LATENCY = 1 - // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr . - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire laguna_s_reset_in, - input wire [C_DATA_WIDTH-1:0] laguna_s_payload, - input wire laguna_s_handshake, - output wire laguna_s_ready, - - // Master side - output wire laguna_m_reset_out, - output wire [C_DATA_WIDTH-1:0] laguna_m_payload, - output wire laguna_m_handshake, - input wire laguna_m_ready - ); - - localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1; - localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES; - - generate - - (* keep="true" *) reg s_reset_dd = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0; - - assign laguna_m_reset_out = laguna_m_reset_out_i; - - always @(posedge ACLK) begin - laguna_s_reset_in_d <= laguna_s_reset_in; - s_reset_dd <= laguna_s_reset_in_d; - laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd; - end - - wire ACLEAR; - assign ACLEAR = ARESET; - - if (1) begin : common - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d; - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i; - wire laguna_s_handshake_q; - wire m_handshake_d; - wire laguna_m_handshake_q; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+2)-1:0] handshake_i; - genvar p; - - assign laguna_m_payload = laguna_m_payload_i; - assign m_handshake_d = handshake_i[C_PIPELINES]; - assign laguna_m_handshake = laguna_m_handshake_q; - assign laguna_s_ready = laguna_s_ready_i; - - always @(posedge ACLK) begin - laguna_m_ready_d <= laguna_m_ready; - laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; - ready_d <= {ready_d, laguna_m_ready_d}; - end - - for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - wire payload_valid_d; - wire payload_valid_q; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data; - assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q; - assign payload_valid_d = handshake_i[((p>0)?(p-1):0)]; - - always @(posedge ACLK) begin - if (p==0) begin - laguna_s_payload_d <= laguna_s_payload; - end else if (p==C_PIPELINES+1) begin - laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - FDCE #( - .INIT(1'b0) - ) payload_valid_asyncclear_inst ( - .Q (payload_valid_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (payload_valid_d) - ); - end // loop p - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_m_handshake_asyncclear_inst ( - .Q (laguna_m_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (m_handshake_d) - ); - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_s_handshake_asyncclear_inst ( - .Q (laguna_s_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (laguna_s_handshake) - ); - - end // gen_slr - endgenerate -endmodule // middle_region_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_source_region_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_REG_CONFIG = 12, - parameter integer C_PIPELINES = 0, - parameter integer C_DATA_WIDTH = 32, - parameter integer C_SLR_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLK2X, - input wire ARESET, - input wire ACLKEN, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire laguna_m_reset_out, - output wire [C_SLR_WIDTH-1:0] laguna_m_payload, - output wire laguna_m_handshake, - input wire laguna_m_ready - ); - - generate - - if (C_REG_CONFIG == 13) begin : gen_slr_tdm - localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH; - - (* keep="true" *) reg areset_d = 1'b0; - always @(posedge ACLK) begin - areset_d <= ARESET; - end - - assign laguna_m_reset_out = 1'b0; - - (* shreg_extract = "no" *) reg [P_EVEN_WIDTH-1:0] payload_d1; - (* shreg_extract = "no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d2; - (* USER_SLL_REG="true", shreg_extract = "no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d3; - (* USER_SLL_REG="true", shreg_extract = "no" *) reg laguna_handshake_d1 = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg s_ready_d2 = 1'b0; - wire sample_cycle; - integer i; - - assign laguna_m_payload = laguna_payload_tdm_d3; - assign laguna_m_handshake = laguna_handshake_d1; - assign S_READY = s_ready_d2; - - always @(posedge ACLK) begin - payload_d1 <= S_PAYLOAD_DATA; // ACLK cycle 1 - end - - always @(posedge ACLK2X) begin - for (i=0;i0) ? C_PIPELINES : 1; - - (* keep="true" *) reg areset_r = 1'b0; - (* keep="true" *) reg areset_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0; - reg [15:0] areset_dly = 16'b0; - - assign laguna_m_reset_out = laguna_m_reset_out_i; - - always @(posedge ACLK) begin - areset_r <= ARESET; - areset_dly <= {16{areset_r}} | (areset_dly<<1); - areset_d <= C_REG_CONFIG == 12 ? ARESET : areset_dly[15]; - laguna_m_reset_out_i <= areset_d; // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used. - end - - wire ACLEAR; - assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET; - - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i; - wire m_handshake_d; - wire laguna_m_handshake_q; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0; - (* keep="true" *) reg s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+1)-1:0] handshake_i; - genvar p; - - assign laguna_m_payload = laguna_m_payload_i; - assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[P_PIPE_WIDTH-1]; - assign laguna_m_handshake = laguna_m_handshake_q; - assign S_READY = s_ready_i; - - always @(posedge ACLK) begin - laguna_m_ready_d <= laguna_m_ready; - ready_d <= {ready_d, laguna_m_ready_d}; - if (areset_d) begin - s_ready_i <= 1'b0; - end else begin - s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; - end - end - - for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - wire payload_valid_d; - wire payload_valid_q; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data; - assign handshake_i[p] = payload_valid_q; - assign payload_valid_d = (p==0) ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[((p>0)?(p-1):0)]; - - always @(posedge ACLK) begin - if (p==C_PIPELINES) begin - laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end else if (p==0) begin - payload_data <= S_PAYLOAD_DATA; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - FDCE #( - .INIT(1'b0) - ) payload_valid_asyncclear_inst ( - .Q (payload_valid_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (payload_valid_d) - ); - end // loop p - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_m_handshake_asyncclear_inst ( - .Q (laguna_m_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (m_handshake_d) - ); - - end // gen_slr -endgenerate -endmodule // source_region_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_dest_region_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_REG_CONFIG = 12, - parameter integer C_DATA_WIDTH = 32, - parameter integer C_SLR_WIDTH = 32, - parameter integer C_PIPELINES = 0, - parameter integer C_SOURCE_LATENCY = 1 - ) - ( - // System Signals - input wire ACLK, - input wire ACLK2X, - input wire ARESET, - input wire ACLKEN, - - // Slave side - input wire laguna_s_reset_in, - input wire [C_SLR_WIDTH-1:0] laguna_s_payload, - input wire laguna_s_handshake, - output wire laguna_s_ready, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - generate - - if (C_REG_CONFIG == 13) begin : gen_slr_tdm - (* keep="true" *) reg areset_d = 1'b0; - always @(posedge ACLK) begin - areset_d <= ARESET; - end - - localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH; - - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d3; - (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d4; - (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d5; - (* USER_SLL_REG="true", shreg_extract="no" *) reg laguna_handshake_d2 = 1'b0; - (* shreg_extract="no" *) reg handshake_d3 = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg s_ready_d1 = 1'b0; - reg [P_EVEN_WIDTH-1:0] payload_demux; - wire m_valid_i; - wire push; - wire pop; - integer i; - - assign laguna_s_ready = s_ready_d1; - assign M_VALID = m_valid_i; - assign pop = M_READY & ACLKEN & m_valid_i; - assign push = handshake_d3; - - always @(posedge ACLK) begin - if (areset_d) begin - laguna_handshake_d2 <= 1'b0; - handshake_d3 <= 1'b0; - end else begin - handshake_d3 <= laguna_handshake_d2; - laguna_handshake_d2 <= laguna_s_handshake; - end - end - - always @(posedge ACLK2X) begin - payload_tdm_d5 <= payload_tdm_d4; - payload_tdm_d4 <= laguna_payload_tdm_d3; - laguna_payload_tdm_d3 <= laguna_s_payload; - end - - always @ * begin - for (i=0;i0 ? C_PIPELINES : 1; - localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES; - - (* keep="true" *) reg areset_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0; - - always @(posedge ACLK) begin - laguna_s_reset_in_d <= laguna_s_reset_in; - areset_d <= C_REG_CONFIG == 12 ? ARESET : laguna_s_reset_in_d; - end - - wire ACLEAR; - assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET; - - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d; - wire laguna_s_handshake_q; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+1)-1:0] handshake_i; - wire m_valid_i; - wire push; - wire pop; - genvar p; - - assign laguna_s_ready = laguna_s_ready_i; - assign pop = M_READY & ACLKEN & m_valid_i; - assign push = handshake_i[C_PIPELINES]; - assign M_VALID = m_valid_i; - - always @(posedge ACLK) begin - laguna_s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; - ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)}; - end - - for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - wire payload_valid_d; - wire payload_valid_q; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data; - assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q; - assign payload_valid_d = handshake_i[((p>0)?(p-1):0)]; - - always @(posedge ACLK) begin - if (p==0) begin - laguna_s_payload_d <= laguna_s_payload; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - FDCE #( - .INIT(1'b0) - ) payload_valid_asyncclear_inst ( - .Q (payload_valid_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (payload_valid_d) - ); - end // loop p - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_s_handshake_asyncclear_inst ( - .Q (laguna_s_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (laguna_s_handshake) - ); - - axis_register_slice_v1_1_29_axic_reg_srl_fifo # - ( - .C_FIFO_WIDTH (C_DATA_WIDTH), - .C_FIFO_SIZE ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4) - ) - srl_fifo_0 - ( - .aclk (ACLK), - .areset (areset_d), - .aclear (ACLEAR), - .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]), - .s_valid (push), - .m_mesg (M_PAYLOAD_DATA), - .m_valid (m_valid_i), - .m_ready (pop) - ); - - end // gen_slr -endgenerate -endmodule // dest_region_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_single_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_DATA_WIDTH = 32, - parameter integer C_PIPELINES = 0 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - generate - - localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1; - - reg areset_d = 1'b0; - reg [3:0] areset_dly = 4'b0; - always @(posedge ACLK) begin - areset_dly <= {4{ARESET}} | (areset_dly<<1); - areset_d <= areset_dly[3]; - end - - if (1) begin : common - reg s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+1)-1:0] handshake_i; - wire m_valid_i; - wire push; - wire pop; - genvar p; - - assign pop = M_READY & ACLKEN & m_valid_i; - assign push = handshake_i[C_PIPELINES]; - assign M_VALID = m_valid_i; - assign S_READY = s_ready_i; - - always @(posedge ACLK) begin - ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)}; - if (areset_d) begin - s_ready_i <= 1'b0; - end else begin - s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; - end - end - - assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA; - assign handshake_i[0] = S_VALID & ACLKEN & s_ready_i; - - for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - (* keep="true" *) reg payload_valid = 1'b0; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data; - assign handshake_i[p] = payload_valid; - - always @(posedge ACLK) begin - if (p==1) begin - payload_data <= S_PAYLOAD_DATA; - payload_valid <= S_VALID & ACLKEN & s_ready_i & ~areset_d; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - payload_valid <= handshake_i[((p>0)?(p-1):0)]; - end - end - end - - if (C_PIPELINES==0) begin : ff_fifo - - (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out; - (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1; - (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2; - reg [1:0] fifo_cnt = 2'h0; - reg m_valid_r = 1'b0; - - assign M_PAYLOAD_DATA = fifo_out; - assign m_valid_i = m_valid_r; - - always @(posedge ACLK) begin - if (areset_d) begin - fifo_cnt <= 2'h0; - m_valid_r <= 1'b0; - end else begin - if (push & ~pop) begin - fifo_cnt <= fifo_cnt + 2'h1; - m_valid_r <= 1'b1; - end else if (~push & pop) begin - fifo_cnt <= fifo_cnt - 2'h1; - m_valid_r <= fifo_cnt[1]; // fifo_cnt >= 2 - end - end - end - - always @(posedge ACLK) begin - case (fifo_cnt) - 2'h0: begin // EMPTY - fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - - 2'h1: begin - fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - if (pop) begin - fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - 2'h2: begin - fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - if (pop) begin - fifo_out <= fifo_out_n1; - fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - default: begin // fifo_cnt == 3 - if (pop) begin - fifo_out <= fifo_out_n1; - fifo_out_n1 <= fifo_out_n2; - fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - endcase - end - - end else begin : srl_fifo - - axis_register_slice_v1_1_29_axic_reg_srl_fifo # - ( - .C_FIFO_WIDTH (C_DATA_WIDTH), - .C_FIFO_SIZE ((C_PIPELINES>12) ? 5 : 4) - ) - srl_fifo_0 - ( - .aclk (ACLK), - .areset (areset_d), - .aclear (1'b0), - .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]), - .s_valid (push), - .m_mesg (M_PAYLOAD_DATA), - .m_valid (m_valid_i), - .m_ready (pop) - ); - - end // gen_fifo - end // gen_slr - endgenerate -endmodule // single_slr - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_axic_reg_srl_fifo # - // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full - ( - parameter integer C_FIFO_WIDTH = 1, // Width of s_mesg/m_mesg. - parameter integer C_FIFO_SIZE = 5 // Depth of FIFO is 2**C_FIFO_SIZE. - ) - ( - input wire aclk, // Clock - input wire areset, // Reset - input wire aclear, // Async clear - input wire [C_FIFO_WIDTH-1:0] s_mesg, // Input data - input wire s_valid, // Input data valid - output wire [C_FIFO_WIDTH-1:0] m_mesg, // Output data - output wire m_valid, // Output data valid - input wire m_ready // Output data ready - ); - - genvar i; - - generate - - localparam integer P_FIFO_DEPTH = 2**C_FIFO_SIZE; - localparam [C_FIFO_SIZE-1:0] P_EMPTY = {C_FIFO_SIZE{1'b1}}; - localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}}; - - localparam M_VALID_0 = 1'b0; - localparam M_VALID_1 = 1'b1; - localparam SRL_VALID_0 = 1'b0; - localparam SRL_VALID_1 = 1'b1; - localparam S_VALID_0 = 1'b0; - localparam S_VALID_1 = 1'b1; - localparam M_READY_0 = 1'b0; - localparam M_READY_1 = 1'b1; - - localparam [1:0] K_EMPTY = {SRL_VALID_0, M_VALID_0}; - localparam [1:0] K_HAS1 = {SRL_VALID_0, M_VALID_1}; - localparam [1:0] K_MIN2 = {SRL_VALID_1, M_VALID_1}; - - reg push; // SRL push - reg pop; // SRL pop - wire [C_FIFO_WIDTH-1:0] srl_reg; - reg [C_FIFO_SIZE-1:0] fifoaddr = P_EMPTY; - - wire [1:0] state; // State vector register - reg [1:0] next; // Next state value - wire [1:0] next_qual; // Next state value - - reg load_mesg; // Load output register - reg srl2mesg; // Output reg loads from SRL (else from s_mesg) - reg [C_FIFO_WIDTH-1:0] mesg_reg; // No initial state - reg m_valid_d; - wire m_valid_q; - - assign m_valid = m_valid_q; - assign next_qual = areset ? K_EMPTY : next; - assign m_mesg = mesg_reg; - - FDCE #( - .INIT(1'b0) - ) asyncclear_mvalid_inst ( - .Q (m_valid_q), - .C (aclk), - .CE (1'b1), - .CLR (aclear), - .D (m_valid_d) - ); - - FDCE #( - .INIT(1'b0) - ) asyncclear_state0_inst ( - .Q (state[0]), - .C (aclk), - .CE (1'b1), - .CLR (aclear), - .D (next_qual[0]) - ); - - FDCE #( - .INIT(1'b0) - ) asyncclear_state1_inst ( - .Q (state[1]), - .C (aclk), - .CE (1'b1), - .CLR (aclear), - .D (next_qual[1]) - ); - - always @ * begin - next = state; // Default: hold state unless re-assigned - m_valid_d = m_valid_q & ~areset; - load_mesg = 1'b1; - srl2mesg = 1'b0; - push = 1'b0; - pop = 1'b0; - case (state) - K_EMPTY: begin // FIFO Empty; pre-assert s_ready - load_mesg = s_valid; - srl2mesg = 1'b0; - push = 1'b0; - pop = 1'b0; - if (s_valid & ~areset) begin - next = K_HAS1; - m_valid_d = 1'b0; - end - end // EMPTY - - K_HAS1: begin // FIFO contains 1 item in the output register (SRL empty) - srl2mesg = 1'b0; - pop = 1'b0; - casex ({s_valid,m_ready}) - {S_VALID_1,M_READY_0}: begin // Receive a 2nd item, push into SRL - next = K_MIN2; - load_mesg = 1'b0; - push = 1'b1; - m_valid_d = 1'b1; - end - - {S_VALID_0,M_READY_1}: begin // Pop to empty - next = K_EMPTY; - load_mesg = 1'b1; // Inconsequential - push = 1'b0; - m_valid_d = 1'b0; - end - - {S_VALID_1,M_READY_1}: begin // Push a new item while popping; replace contents of output reg - next = K_HAS1; - load_mesg = 1'b1; - push = 1'b0; - m_valid_d = 1'b1; - end - - default: begin // s_valid=0, m_ready=0: hold state - next = K_HAS1; - load_mesg = 1'b0; - push = 1'b0; - m_valid_d = 1'b1; - end - endcase - end // HAS1 - - K_MIN2: begin // FIFO contains >1 item, some in SRL - srl2mesg = 1'b1; - m_valid_d = 1'b1; - casex ({s_valid,m_ready}) - {S_VALID_1,M_READY_0}: begin // Receive a new item, push into SRL - next = K_MIN2; - load_mesg = 1'b0; - push = 1'b1; - pop = 1'b0; - end - - {S_VALID_0,M_READY_1}: begin // Pop SRL to replace output reg - next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2; - load_mesg = 1'b1; - push = 1'b0; - pop = 1'b1; - end - - {S_VALID_1,M_READY_1}: begin // Push a new item while popping - next = K_MIN2; - load_mesg = 1'b1; - push = 1'b1; - pop = 1'b1; - end - - default: begin // s_valid=0, m_ready=0: hold state - next = K_MIN2; - load_mesg = 1'b0; - push = 1'b0; - pop = 1'b0; - end - endcase - end // MIN2 - - default: begin // Same as RESET - next = K_EMPTY; - end // default - endcase - end - - always @(posedge aclk) begin // Payload reg needs no reset - if (load_mesg) begin - mesg_reg <= srl2mesg ? srl_reg : s_mesg; - end - end - - // SRL FIFO address pointer - always @(posedge aclk) begin - if (areset) begin - fifoaddr <= P_EMPTY; - end else begin - if (push & ~pop) begin - fifoaddr <= fifoaddr + 1; - end else if (~push & pop) begin - fifoaddr <= fifoaddr - 1; - end - end - end - - //--------------------------------------------------------------------------- - // Instantiate SRLs - //--------------------------------------------------------------------------- - for (i=0;i= 1) - ) - ( - input wire clk, // Clock - input wire [C_A_WIDTH-1:0] a, // Address - input wire ce, // Clock Enable - input wire d, // Input Data - output wire q // Output Data - ); - - localparam integer P_SRLDEPTH = 2**C_A_WIDTH; - - reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}}; - always @(posedge clk) - if (ce) - shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d}; - assign q = shift_reg[a]; - -endmodule // srl_rtl - - -// (c) Copyright 2019, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -(* autopipeline_module="yes" *) -module axis_register_slice_v1_1_29_auto_slr # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - wire handshake_pipe; - wire ready_pipe; - wire [C_DATA_WIDTH-1:0] payload_pipe; - (* keep="true" *) reg s_aclear = 1'b0; - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0; - (* autopipeline_group="resp" *) reg s_areset_resp = 1'b0; - (* keep="true" *) reg s_areset_resp2 = 1'b0; - (* keep="true" *) reg m_aclear = 1'b0; - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0; - (* autopipeline_group="resp" *) reg m_areset_resp = 1'b0; - (* keep="true" *) reg m_areset_resp2 = 1'b0; - - // Global Reset pipelining - - always @(posedge ACLK) begin - s_aclear <= ARESET; - s_areset_fwd <= ARESET; - s_areset_resp <= s_areset_fwd; // Auto-pipeline - s_areset_resp2 <= s_areset_resp; // Auto-pipeline - end - - always @(posedge ACLK) begin - m_aclear <= ARESET; - m_areset_fwd <= ARESET; - m_areset_resp <= m_areset_fwd; // Auto-pipeline - m_areset_resp2 <= m_areset_resp; // Auto-pipeline - end - - // Source-side submodule - - axis_register_slice_v1_1_29_auto_src # - ( - .C_DATA_WIDTH (C_DATA_WIDTH) - ) - slr_auto_src - ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .s_aclear (s_aclear), - .s_areset_resp2 (s_areset_resp2), - .S_VALID (S_VALID), - .S_READY (S_READY), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .ready_pipe (ready_pipe), - .handshake_pipe (handshake_pipe), - .payload_pipe (payload_pipe) - ); - - // Destination-side submodule - - axis_register_slice_v1_1_29_auto_dest # - ( - .C_DATA_WIDTH (C_DATA_WIDTH) - ) - slr_auto_dest - ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .m_aclear (m_aclear), - .m_areset_resp2 (m_areset_resp2), - .M_READY (M_READY), - .M_VALID (M_VALID), - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .handshake_pipe (handshake_pipe), - .ready_pipe (ready_pipe), - .payload_pipe (payload_pipe) - ); - -endmodule // auto_slr - -module axis_register_slice_v1_1_29_auto_src # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - input wire ACLK, - input wire ACLKEN, - input wire s_aclear, - input wire s_areset_resp2, - input wire S_VALID, - input wire ready_pipe, - output wire S_READY, - output wire handshake_pipe, - output wire [C_DATA_WIDTH-1:0] payload_pipe, - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA - ); - - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r; - (* keep="true" *) reg [2:0] s_aresetn_resp4 = 3'b000; - wire s_aresetn_resp3; - wire s_aresetn_d; - wire s_aresetn_q; - wire s_handshake_d; - wire s_ready_i; - - assign S_READY = s_ready_i & s_aresetn_q; - assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q; - assign s_handshake_d = S_VALID & s_ready_i & ACLKEN & s_aresetn_q; - assign payload_pipe = payload_pipe_r; - - always @(posedge ACLK or posedge s_aclear) begin - if (s_aclear) begin - s_aresetn_resp4 <= 3'b000; - end else begin - s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3}; - end - end - - always @(posedge ACLK) begin - payload_pipe_r <= S_PAYLOAD_DATA; - end - - FDCE #( - .INIT(1'b0) - ) s_aresetn_resp3_inst ( - .Q (s_aresetn_resp3), - .C (ACLK), - .CE (1'b1), - .CLR (1'b0), - .D (~s_areset_resp2) - ); - - // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2. - FDCE #( - .INIT(1'b0) - ) reset_asyncclear ( - .Q (s_aresetn_q), - .C (ACLK), - .CE (1'b1), - .CLR (s_aclear), - .D (s_aresetn_d) - ); - - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) - FDCE #( - .INIT(1'b0) - ) handshake_asyncclear ( - .Q (handshake_pipe), - .C (ACLK), - .CE (1'b1), - .CLR (s_aclear), - .D (s_handshake_d) - ); - - FDCE #( - .INIT(1'b0) - ) ready_asyncclear ( - .Q (s_ready_i), - .C (ACLK), - .CE (ACLKEN), - .CLR (s_aclear), - .D (ready_pipe) - ); - -endmodule // auto_src - -module axis_register_slice_v1_1_29_auto_dest # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - input wire ACLK, - input wire ACLKEN, - input wire m_aclear, - input wire m_areset_resp2, - input wire M_READY, - input wire handshake_pipe, - output wire ready_pipe, - output wire M_VALID, - input wire [C_DATA_WIDTH-1:0] payload_pipe, - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA - ); - - (* keep="true" *) reg [2:0] m_aresetn_resp4 = 3'b000; - wire m_aresetn_resp3; - wire m_aresetn_d; - wire m_aresetn_q; - wire m_valid_i; - wire pop; - wire m_ready_d; - wire m_handshake_q; - reg [C_DATA_WIDTH-1:0] m_payload_q; - - assign M_VALID = m_valid_i; - assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q; - assign m_ready_d = (M_READY | ~m_valid_i) & ACLKEN & m_aresetn_q; - assign pop = M_READY & m_valid_i & ACLKEN; - - always @(posedge ACLK or posedge m_aclear) begin - if (m_aclear) begin - m_aresetn_resp4 <= 3'b000; - end else begin - m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3}; - end - end - - always @(posedge ACLK) begin - m_payload_q <= payload_pipe; - end - - FDCE #( - .INIT(1'b0) - ) m_aresetn_resp3_inst ( - .Q (m_aresetn_resp3), - .C (ACLK), - .CE (1'b1), - .CLR (1'b0), - .D (~m_areset_resp2) - ); - - // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2. - FDCE #( - .INIT(1'b0) - ) reset_asyncclear ( - .Q (m_aresetn_q), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (m_aresetn_d) - ); - - FDCE #( - .INIT(1'b0) - ) handshake_asyncclear ( - .Q (m_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (handshake_pipe) - ); - - (* autopipeline_group="resp" *) - FDCE #( - .INIT(1'b0) - ) ready_asyncclear ( - .Q (ready_pipe), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (m_ready_d) - ); - - axis_register_slice_v1_1_29_axic_reg_srl_fifo # - ( - .C_FIFO_WIDTH (C_DATA_WIDTH), - .C_FIFO_SIZE (5) - ) - srl_fifo - ( - .aclk (ACLK), - .areset (~m_aresetn_q), - .aclear (m_aclear), - .s_mesg (m_payload_q), - .s_valid (m_handshake_q), - .m_mesg (M_PAYLOAD_DATA), - .m_valid (m_valid_i), - .m_ready (pop) - ); - -endmodule // auto_dest - - -// (c) Copyright 2010-2011, 2013-2014, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Register Slice -// Generic single-channel AXI pipeline register on forward and/or reverse signal path -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axic_register_slice -// -//-------------------------------------------------------------------------- - -`timescale 1ps/1ps - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_axisc_register_slice # - ( - parameter C_FAMILY = "virtex6", - parameter C_DATA_WIDTH = 32, - parameter C_REG_CONFIG = 32'h00000001, - // C_REG_CONFIG: - // 0 => BYPASS = The channel is just wired through the module. - // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID - // 2 => FWD = The master VALID and payload signals are registrated. - // 3 => REV = The slave ready signal is registrated - // 4 => RESERVED (all outputs driven to 0). - // 5 => RESERVED (all outputs driven to 0). - // 6 => INPUTS = Slave and Master side inputs are registrated. - // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining - // 8 => FWD_REV = Both FWD and REV (fully-registered) - // 10 => NO_READY = Assume no ready signal - // 12 => SLR Crossing (source->dest flops, full-width payload, single clock) - // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock) - // 15 => Variable SLR Crossings (single clock) - // 16 -> Auto-pipelining - parameter integer C_NUM_SLR_CROSSINGS = 0, - parameter integer C_PIPELINES_MASTER = 0, - parameter integer C_PIPELINES_SLAVE = 0, - parameter integer C_PIPELINES_MIDDLE = 0 - ) - ( - // System Signals - input wire ACLK, - input wire ACLK2X, - input wire ARESET, - input wire ACLKEN, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - generate - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 0 - // Bypass mode - // - //////////////////////////////////////////////////////////////////// - if (C_REG_CONFIG == 32'h00000000) - begin - assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; - assign M_VALID = S_VALID; - assign S_READY = M_READY; - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 17 - // Preserve SI - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 17) begin : gen_pres_si - - axis_register_slice_v1_1_29_test_slave # ( - .C_DATA_WIDTH ( C_DATA_WIDTH ) - ) - auto ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Slave side - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY) - ); - - // Master side - assign M_PAYLOAD_DATA = 0; - assign M_VALID = 1'b0; - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 18 - // Preserve MI - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 18) begin : gen_pres_mi - - axis_register_slice_v1_1_29_test_master # ( - .C_DATA_WIDTH ( C_DATA_WIDTH ) - ) - auto ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Master side - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - - // Slave side - assign S_READY = 1'b0; - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 16 - // Multi SLR Crossing - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 16) begin : gen_auto_slr - - axis_register_slice_v1_1_29_auto_slr # ( - .C_DATA_WIDTH ( C_DATA_WIDTH ) - ) - auto ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Slave side - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - - // Master side - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 15 - // Multi SLR Crossing - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 15) begin : gen_multi_slr - - axis_register_slice_v1_1_29_multi_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) , - .C_PIPELINES_MASTER (C_PIPELINES_MASTER) , - .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) , - .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE) - ) - multi ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Slave side - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - - // Master side - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 12 or 13 - // TDM SLR Crossing - // - //////////////////////////////////////////////////////////////////// - else if ((C_REG_CONFIG == 32'h0000000C) || (C_REG_CONFIG == 32'h0000000D)) - begin : gen_slr_crossing - localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH; - localparam integer P_TDM_WIDTH = P_EVEN_WIDTH/2; - localparam integer P_SLR_WIDTH = (C_REG_CONFIG == 13) ? P_TDM_WIDTH : C_DATA_WIDTH; - - wire [P_SLR_WIDTH-1:0] slr_payload; - wire slr_handshake; - wire slr_ready; - - axis_register_slice_v1_1_29_source_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( C_REG_CONFIG ) , - .C_PIPELINES (0), - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( P_SLR_WIDTH ) - ) - slr_source_0 ( - .ACLK ( ACLK ) , - .ACLK2X ( ACLK2X ) , - .ARESET (ARESET), - .ACLKEN ( ACLKEN ) , - .laguna_m_reset_out ( ) , - .S_PAYLOAD_DATA ( S_PAYLOAD_DATA ) , - .S_VALID ( S_VALID ) , - .S_READY ( S_READY ) , - .laguna_m_payload ( slr_payload ) , - .laguna_m_handshake ( slr_handshake ) , - .laguna_m_ready ( slr_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( C_REG_CONFIG ) , - .C_PIPELINES (0), - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( P_SLR_WIDTH ) - ) - slr_dest_0 ( - .ACLK ( ACLK ) , - .ACLK2X ( ACLK2X ) , - .ARESET (ARESET), - .ACLKEN ( ACLKEN ) , - .laguna_s_reset_in ( 1'b0 ) , - .laguna_s_payload ( slr_payload ) , - .laguna_s_handshake ( slr_handshake ) , - .laguna_s_ready ( slr_ready ) , - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - - end // if (C_REG_CONFIG == 12 or 13 ) - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 10 - // No ready, single stage register - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h0000000A) - begin : NO_READY - - reg [C_DATA_WIDTH-1:0] storage_data1; - reg m_valid_r = 1'b0; //local signal of output - - // assign local signal to its output signal - assign S_READY = 1'b1; - assign M_VALID = m_valid_r; - - // Load storage1 with slave side data - always @(posedge ACLK) - begin - if (ACLKEN) begin - storage_data1 <= S_PAYLOAD_DATA; - m_valid_r <= S_VALID; - end - end - - assign M_PAYLOAD_DATA = storage_data1; - - - end // if (C_REG_CONFIG == 10 ) - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 1 - // Minimized fanout on input signals M_READY and S_TVALID - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000001) begin : gen_AB_reg_slice - // /----------S_READY - // |/---------M_VALID - localparam SM_RESET = 2'b00; - localparam SM_IDLE = 2'b10; - localparam SM_ONE = 2'b11; - localparam SM_FULL = 2'b01; - - (* fsm_encoding = "none" *) reg [1:0] state = SM_RESET; - reg [C_DATA_WIDTH-1:0] payload_a; - reg [C_DATA_WIDTH-1:0] payload_b; - reg sel_rd = 1'b0; - reg sel_wr = 1'b0; - wire sel; - wire load_a; - wire load_b; - - assign M_VALID = state[0]; - assign S_READY = state[1]; - - always @(posedge ACLK) begin - if (ARESET) begin - state <= SM_RESET; - end - else if (ACLKEN) begin - case (state) - SM_IDLE: - if (S_VALID) - state <= SM_ONE; - SM_ONE: - if (S_VALID & ~M_READY) - state <= SM_FULL; - else if (~S_VALID & M_READY) - state <= SM_IDLE; - SM_FULL: - if (M_READY) - state <= SM_ONE; - // SM_RESET: - default: - state <= SM_IDLE; - endcase - end - end - - assign sel = sel_rd; - - always @(posedge ACLK) begin - if (ARESET) begin - sel_rd <= 1'b0; - end - else if (ACLKEN) begin - sel_rd <= (M_READY & M_VALID) ? ~sel_rd : sel_rd; - end - end - - assign load_a = ~sel_wr & (state != SM_FULL); - assign load_b = sel_wr & (state != SM_FULL); - always @(posedge ACLK) begin - if (ARESET) begin - sel_wr <= 1'b0; - end - else if (ACLKEN) begin - sel_wr <= (S_READY & S_VALID) ? ~sel_wr : sel_wr; - end - end - - always @(posedge ACLK) begin - if (ACLKEN) begin - payload_a <= load_a ? S_PAYLOAD_DATA : payload_a; - end - end - - always @(posedge ACLK) begin - if (ACLKEN) begin - payload_b <= load_b ? S_PAYLOAD_DATA : payload_b; - end - end - - assign M_PAYLOAD_DATA = sel ? payload_b : payload_a; - - end // if (C_REG_CONFIG == 1 ) - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 8 - // Both FWD and REV mode - // - //////////////////////////////////////////////////////////////////// - else if ((C_REG_CONFIG == 32'h00000008)) - begin - localparam [1:0] - ZERO = 2'b10, - ONE = 2'b11, - TWO = 2'b01; - (* fsm_encoding = "none" *) reg [1:0] state = ZERO; - - reg [C_DATA_WIDTH-1:0] storage_data1; - reg [C_DATA_WIDTH-1:0] storage_data2; - reg load_s1; - wire load_s2; - wire load_s1_from_s2; - reg s_ready_i = 1'b0; //local signal of output - wire m_valid_i; //local signal of output - - // assign local signal to its output signal - assign S_READY = s_ready_i; - assign M_VALID = m_valid_i; - - (* equivalent_register_removal = "no" *) reg [1:0] aresetn_d = 2'b00; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - aresetn_d <= {aresetn_d[0], ~ARESET}; - end - end - - // Load storage1 with either slave side data or from storage2 - always @(posedge ACLK) - begin - if (ACLKEN) begin - storage_data1 <= ~load_s1 ? storage_data1 : - load_s1_from_s2 ? storage_data2 : - S_PAYLOAD_DATA; - end - end - - // Load storage2 with slave side data - always @(posedge ACLK) - begin - if (ACLKEN) begin - storage_data2 <= load_s2 ? S_PAYLOAD_DATA : storage_data2; - end - end - - assign M_PAYLOAD_DATA = storage_data1; - - // Always load s2 on a valid transaction even if it's unnecessary - assign load_s2 = S_VALID & s_ready_i; - - // Loading s1 - always @ * - begin - if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction - // Load when ONE if we both have read and write at the same time - ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || - // Load when TWO and we have a transaction on Master side - ((state == TWO) && (M_READY == 1))) - load_s1 = 1'b1; - else - load_s1 = 1'b0; - end // always @ * - - assign load_s1_from_s2 = (state == TWO); - - // State Machine for handling output signals - always @(posedge ACLK) begin - if (ARESET) begin - s_ready_i <= 1'b0; - state <= ZERO; - end else if (ACLKEN && aresetn_d == 2'b01) begin - s_ready_i <= 1'b1; - state <= ZERO; - end else if (ACLKEN && aresetn_d[0]) begin - case (state) - // No transaction stored locally - ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE - - // One transaction stored locally - ONE: begin - if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO - if (~M_READY & S_VALID) begin - state <= TWO; // Got another one so move to TWO - s_ready_i <= 1'b0; - end - end - - // TWO transaction stored locally - TWO: if (M_READY) begin - state <= ONE; // Read out one so move to ONE - s_ready_i <= 1'b1; - end - - default: - state <= ZERO; - - endcase // case (state) - end - end // always @ (posedge ACLK) - - assign m_valid_i = state[0]; - - end // if (C_REG_CONFIG == 8) - - //////////////////////////////////////////////////////////////////// - // NOT SUPPORTED - // C_REG_CONFIG = 2 - // Only FWD mode - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000002) - begin - reg [C_DATA_WIDTH-1:0] storage_data; - wire s_ready_i; //local signal of output - reg m_valid_i = 1'b0; //local signal of output - - // assign local signal to its output signal - assign S_READY = s_ready_i; - assign M_VALID = m_valid_i; - - (* equivalent_register_removal = "no" *) reg [1:0] areset_d; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - areset_d <= {areset_d[0], ARESET}; - end - end - - // Save payload data whenever we have a transaction on the slave side - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data; - end - - assign M_PAYLOAD_DATA = storage_data; - - // M_Valid set to high when we have a completed transfer on slave side - // Is removed on a M_READY except if we have a new transfer on the slave side - always @(posedge ACLK) begin - if (areset_d) begin - m_valid_i <= 1'b0; - end - else if (ACLKEN) begin - m_valid_i <= S_VALID ? 1'b1 : // Always set m_valid_i when slave side is valid - M_READY ? 1'b0 : // Clear (or keep) when no slave side is valid but master side is ready - m_valid_i; - end - end // always @ (posedge ACLK) - - // Slave Ready is either when Master side drives M_Ready or we have space in our storage data - assign s_ready_i = (M_READY | ~m_valid_i) & ~|areset_d; - - end // if (C_REG_CONFIG == 2) - //////////////////////////////////////////////////////////////////// - // - // NOT SUPPORTED - // C_REG_CONFIG = 3 - // Only REV mode - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000003) - begin - reg [C_DATA_WIDTH-1:0] storage_data; - reg s_ready_i = 1'b0; //local signal of output - reg has_valid_storage_i; - reg has_valid_storage; - - (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - areset_d <= ARESET; - end - end - - // Save payload data whenever we have a transaction on the slave side - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data; - end - - assign M_PAYLOAD_DATA = has_valid_storage ? storage_data : S_PAYLOAD_DATA; - - // Need to determine when we need to save a payload - // Need a combinatorial signals since it will also effect S_READY - always @ * - begin - // Set the value if we have a slave transaction but master side is not ready - if (S_VALID & s_ready_i & ~M_READY) - has_valid_storage_i = 1'b1; - - // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side - // transaction - else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0))) - has_valid_storage_i = 1'b0; - else - has_valid_storage_i = has_valid_storage; - end // always @ * - - always @(posedge ACLK) - begin - if (ARESET) begin - has_valid_storage <= 1'b0; - end - else if (ACLKEN) begin - has_valid_storage <= has_valid_storage_i; - end - end - - // S_READY is either clocked M_READY or that we have room in local storage - always @(posedge ACLK) begin - if (ARESET) begin - s_ready_i <= 1'b0; - end - else if (ACLKEN) begin - s_ready_i <= M_READY | ~has_valid_storage_i; - end - end - - // assign local signal to its output signal - assign S_READY = s_ready_i; - - // M_READY is either combinatorial S_READY or that we have valid data in local storage - assign M_VALID = (S_VALID | has_valid_storage) & ~areset_d; - - end // if (C_REG_CONFIG == 3) - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED - // - //////////////////////////////////////////////////////////////////// - else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005)) - begin -// synthesis translate_off - initial begin - $display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED."); - end -// synthesis translate_on - assign M_PAYLOAD_DATA = 0; - assign M_VALID = 1'b0; - assign S_READY = 1'b0; - end - - //////////////////////////////////////////////////////////////////// - // - // NOT SUPPORTED - // C_REG_CONFIG = 6 - // INPUTS mode - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000006) - begin - localparam [1:0] - ZERO = 2'b00, - ONE = 2'b01, - TWO = 2'b11; - reg [1:0] state = ZERO; - reg [1:0] next_state; - - reg [C_DATA_WIDTH-1:0] storage_data1; - reg [C_DATA_WIDTH-1:0] storage_data2; - reg s_valid_d = 1'b0; - reg s_ready_d = 1'b0; - reg m_ready_d = 1'b0; - reg m_valid_d = 1'b0; - reg load_s2; - reg sel_s2; - wire new_access; - wire access_done; - wire s_ready_i; //local signal of output - reg s_ready_ii; - reg m_valid_i; //local signal of output - - (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - areset_d <= ARESET; - end - end - - // assign local signal to its output signal - assign S_READY = (state == ZERO) ? 1'b0 : s_ready_i; - assign M_VALID = (state == ZERO) ? 1'b0 : m_valid_i; - assign s_ready_i = s_ready_ii & ~areset_d; - - // Registrate input control signals - always @(posedge ACLK) - begin - if (ARESET) begin - s_valid_d <= 1'b0; - s_ready_d <= 1'b0; - m_ready_d <= 1'b0; - end else if (ACLKEN) begin - s_valid_d <= S_VALID; - s_ready_d <= s_ready_i; - m_ready_d <= M_READY; - end - end // always @ (posedge ACLK) - - // Load storage1 with slave side payload data when slave side ready is high - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data1 <= (s_ready_i) ? S_PAYLOAD_DATA : storage_data1; - end - - // Load storage2 with storage data - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data2 <= load_s2 ? storage_data1 : storage_data2; - end - - always @(posedge ACLK) - begin - if (ARESET) - m_valid_d <= 1'b0; - else if (ACLKEN) - m_valid_d <= m_valid_i; - end - - // Local help signals - assign new_access = s_ready_d & s_valid_d; - assign access_done = m_ready_d & m_valid_d; - - - // State Machine for handling output signals - always @* - begin - next_state = state; // Stay in the same state unless we need to move to another state - load_s2 = 0; - sel_s2 = 0; - m_valid_i = 0; - s_ready_ii = 0; - case (state) - // No transaction stored locally - ZERO: begin - load_s2 = 0; - sel_s2 = 0; - m_valid_i = 0; - s_ready_ii = 1; - if (new_access) begin - next_state = ONE; // Got one so move to ONE - load_s2 = 1; - m_valid_i = 0; - end - else begin - next_state = next_state; - load_s2 = load_s2; - m_valid_i = m_valid_i; - end - - end // case: ZERO - - // One transaction stored locally - ONE: begin - load_s2 = 0; - sel_s2 = 1; - m_valid_i = 1; - s_ready_ii = 1; - if (~new_access & access_done) begin - next_state = ZERO; // Read out one so move to ZERO - m_valid_i = 0; - end - else if (new_access & ~access_done) begin - next_state = TWO; // Got another one so move to TWO - s_ready_ii = 0; - end - else if (new_access & access_done) begin - load_s2 = 1; - sel_s2 = 0; - end - else begin - load_s2 = load_s2; - sel_s2 = sel_s2; - end - - - end // case: ONE - - // TWO transaction stored locally - TWO: begin - load_s2 = 0; - sel_s2 = 1; - m_valid_i = 1; - s_ready_ii = 0; - if (access_done) begin - next_state = ONE; // Read out one so move to ONE - s_ready_ii = 1; - load_s2 = 1; - sel_s2 = 0; - end - else begin - next_state = next_state; - s_ready_ii = s_ready_ii; - load_s2 = load_s2; - sel_s2 = sel_s2; - end - end // case: TWO - endcase // case (state) - end // always @ * - - - // State Machine for handling output signals - always @(posedge ACLK) - begin - if (ARESET) - state <= ZERO; - else if (ACLKEN) - state <= next_state; // Stay in the same state unless we need to move to another state - end - - // Master Payload mux - assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1; - - end // if (C_REG_CONFIG == 6) - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 7 - // Light-weight mode. - // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining - // Operates same as 1-deep FIFO - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000007) - begin - reg [C_DATA_WIDTH-1:0] storage_data1; - reg s_ready_i = 1'b0; //local signal of output - reg m_valid_i = 1'b0; //local signal of output - - // assign local signal to its output signal - assign S_READY = s_ready_i; - assign M_VALID = m_valid_i; - - (* equivalent_register_removal = "no" *) reg [1:0] aresetn_d = 2'b00; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - aresetn_d <= {aresetn_d[0], ~ARESET}; - end - end - - // Load storage1 with slave side data - always @(posedge ACLK) - begin - if (ARESET) begin - s_ready_i <= 1'b0; - m_valid_i <= 1'b0; - end else if (ACLKEN) begin - if (aresetn_d == 2'b01) begin - s_ready_i <= 1'b1; - end else if (aresetn_d[0]) begin - if (m_valid_i & M_READY) begin - s_ready_i <= 1'b1; - m_valid_i <= 1'b0; - end else if (S_VALID & s_ready_i) begin - s_ready_i <= 1'b0; - m_valid_i <= 1'b1; - end - end - if (~m_valid_i) begin - storage_data1 <= S_PAYLOAD_DATA; - end - end - end - assign M_PAYLOAD_DATA = storage_data1; - end // if (C_REG_CONFIG == 7) - - else begin : default_case - // Passthrough - assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; - assign M_VALID = S_VALID; - assign S_READY = M_READY; - end - - endgenerate -endmodule // axisc_register_slice - - - -// (c) Copyright 2011-2014, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Register Slice -// Generic single-channel AXIS pipeline register on forward and/or reverse signal path. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_register_slice -// util_axis2vector -// axisc_register_slice -// util_vector2axis -// -//-------------------------------------------------------------------------- - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_axis_register_slice # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter C_FAMILY = "virtex6", - parameter integer C_AXIS_TDATA_WIDTH = 8, - parameter integer C_AXIS_TID_WIDTH = 1, - parameter integer C_AXIS_TDEST_WIDTH = 1, - parameter integer C_AXIS_TUSER_WIDTH = 1, - parameter [31:0] C_AXIS_SIGNAL_SET = 32'h3, - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - parameter integer C_REG_CONFIG = 1, - // C_REG_CONFIG: - // 0 => BYPASS = The channel is just wired through the module. - // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID - // 2 => FWD = The master VALID and payload signals are registrated. - // 3 => REV = The slave ready signal is registrated - // 4 => RESERVED (all outputs driven to 0). - // 5 => RESERVED (all outputs driven to 0). - // 6 => INPUTS = Slave and Master side inputs are registrated. - // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining - // 8 => FWD_REV = Both FWD and REV (fully-registered) - // 10 => NO_READY = Assume no ready signal - // 12 => SLR Crossing (source->dest flops, full-width payload, single clock) - // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock) - // 15 => Variable SLR Crossings (single clock) - // 16 -> Auto-pipelining - parameter integer C_NUM_SLR_CROSSINGS = 0, - parameter integer C_PIPELINES_MASTER = 0, - parameter integer C_PIPELINES_SLAVE = 0, - parameter integer C_PIPELINES_MIDDLE = 0 - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // System Signals - input wire aclk, - input wire aclk2x, - input wire aresetn, - input wire aclken, - - // Slave side - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, - input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb, - input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep, - input wire s_axis_tlast, - input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid, - input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, - input wire [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, - - // Master side - output wire m_axis_tvalid, - input wire m_axis_tready, - output wire [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, - output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb, - output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep, - output wire m_axis_tlast, - output wire [C_AXIS_TID_WIDTH-1:0] m_axis_tid, - output wire [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, - output wire [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser - ); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - localparam P_TPAYLOAD_WIDTH = f_payload_width(C_AXIS_TDATA_WIDTH, C_AXIS_TID_WIDTH, - C_AXIS_TDEST_WIDTH, C_AXIS_TUSER_WIDTH, - C_AXIS_SIGNAL_SET); - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -wire [P_TPAYLOAD_WIDTH-1:0] s_axis_tpayload; -wire [P_TPAYLOAD_WIDTH-1:0] m_axis_tpayload; - -reg areset_r = 1'b0; -always @(posedge aclk) begin - areset_r <= ~aresetn; -end - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - axis_infrastructure_v1_1_1_util_axis2vector #( - .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET ) - ) - util_axis2vector_0 ( - .TDATA ( s_axis_tdata ) , - .TSTRB ( s_axis_tstrb ) , - .TKEEP ( s_axis_tkeep ) , - .TLAST ( s_axis_tlast ) , - .TID ( s_axis_tid ) , - .TDEST ( s_axis_tdest ) , - .TUSER ( s_axis_tuser ) , - .TPAYLOAD ( s_axis_tpayload ) - ); - - axis_register_slice_v1_1_29_axisc_register_slice #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_REG_CONFIG ( (C_AXIS_SIGNAL_SET[0] == 0) ? 32'hA : C_REG_CONFIG), - .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) , - .C_PIPELINES_MASTER (C_PIPELINES_MASTER) , - .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) , - .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE) - ) - axisc_register_slice_0 ( - .ACLK ( aclk ) , - .ACLK2X ( aclk2x ) , - .ARESET ( areset_r ) , - .ACLKEN ( aclken ) , - .S_VALID ( s_axis_tvalid ) , - .S_READY ( s_axis_tready ) , - .S_PAYLOAD_DATA ( s_axis_tpayload ) , - - .M_VALID ( m_axis_tvalid ) , - .M_READY ( (C_AXIS_SIGNAL_SET[0] == 0) ? 1'b1 : m_axis_tready ) , - .M_PAYLOAD_DATA ( m_axis_tpayload ) - ); - - axis_infrastructure_v1_1_1_util_vector2axis #( - .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET ) - ) - util_vector2axis_0 ( - .TPAYLOAD ( m_axis_tpayload ) , - .TDATA ( m_axis_tdata ) , - .TSTRB ( m_axis_tstrb ) , - .TKEEP ( m_axis_tkeep ) , - .TLAST ( m_axis_tlast ) , - .TID ( m_axis_tid ) , - .TDEST ( m_axis_tdest ) , - .TUSER ( m_axis_tuser ) - ); - - -endmodule // axis_register_slice - -`default_nettype wire - - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v deleted file mode 100644 index 4388ff0..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v +++ /dev/null @@ -1,125 +0,0 @@ -// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:axis_register_slice:1.1 -// IP Revision: 29 - -(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *) -(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *) -(* CORE_GENERATION_INFO = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_register_slice,x_ipVersion=1.1,x_ipCoreRevision=29,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011,C_REG_CONFIG=8,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER=0,C_PIPELINES_SLAVE=0,C_PIPELINES_MIDDLE=0}" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) -module axis_register_slice_32 ( - aclk, - aresetn, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata -); - -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) -input wire aclk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) -input wire aresetn; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) -input wire s_axis_tvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) -output wire s_axis_tready; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) -input wire [31 : 0] s_axis_tdata; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) -output wire m_axis_tvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) -input wire m_axis_tready; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) -output wire [31 : 0] m_axis_tdata; - - axis_register_slice_v1_1_29_axis_register_slice #( - .C_FAMILY("zynquplus"), - .C_AXIS_TDATA_WIDTH(32), - .C_AXIS_TID_WIDTH(1), - .C_AXIS_TDEST_WIDTH(1), - .C_AXIS_TUSER_WIDTH(1), - .C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011), - .C_REG_CONFIG(8), - .C_NUM_SLR_CROSSINGS(0), - .C_PIPELINES_MASTER(0), - .C_PIPELINES_SLAVE(0), - .C_PIPELINES_MIDDLE(0) - ) inst ( - .aclk(aclk), - .aclk2x(1'H0), - .aresetn(aresetn), - .aclken(1'H1), - .s_axis_tvalid(s_axis_tvalid), - .s_axis_tready(s_axis_tready), - .s_axis_tdata(s_axis_tdata), - .s_axis_tstrb(4'HF), - .s_axis_tkeep(4'HF), - .s_axis_tlast(1'H1), - .s_axis_tid(1'H0), - .s_axis_tdest(1'H0), - .s_axis_tuser(1'H0), - .m_axis_tvalid(m_axis_tvalid), - .m_axis_tready(m_axis_tready), - .m_axis_tdata(m_axis_tdata), - .m_axis_tstrb(), - .m_axis_tkeep(), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser() - ); -endmodule diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci b/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci index cd633f0..6f0c562 100644 --- a/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci +++ b/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci @@ -4,7 +4,7 @@ "xci_name": "addsub", "component_reference": "xilinx.com:ip:c_addsub:12.0", "ip_revision": "16", - "gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/addsub", + "gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/addsub", "parameters": { "component_parameters": { "Component_Name": [ { "value": "addsub", "resolve_type": "user", "usage": "all" } ], diff --git a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd index e25d70b..09ccd56 100644 --- a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd +++ b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd @@ -35,7 +35,6 @@ entity qsfp_intfc_v1_0 is -- sysref_in : in std_logic; ref_clk_div2_in : in std_logic; qsfp2_clk_in : in std_logic; - qsfp3_clk_in : in std_logic; pl_clk3_0 : in std_logic; QSFP1_SI570_CLOCK_P : in std_logic; @@ -63,6 +62,14 @@ entity qsfp_intfc_v1_0 is QSFP1_RESETL_LS : out std_logic; QSFP1_MODPRSL_LS : in std_logic; QSFP1_INTL_LS : in std_logic; +----------------- + QSFP2_RESETL_LS : out std_logic; + QSFP2_MODPRSL_LS : in std_logic; + QSFP2_INTL_LS : in std_logic; +----------------- + QSFP3_RESETL_LS : out std_logic; + QSFP3_MODPRSL_LS : in std_logic; + QSFP3_INTL_LS : in std_logic; ----------------- QSFP4_SI570_CLOCK_P : in std_logic; QSFP4_SI570_CLOCK_N : in std_logic; @@ -107,7 +114,7 @@ entity qsfp_intfc_v1_0 is qsfp1_capture_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0); qsfp1_tx_fifo_128_aempty_cnt_in : in std_logic_vector(31 downto 0); qsfp1_capture_rx_data_ready_cnt_in : in std_logic_vector(31 downto 0); - qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); + qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); mem_xfer_tx_upload_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); dac_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); @@ -117,42 +124,13 @@ entity qsfp_intfc_v1_0 is qsfp4_playback_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0); fiber_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); + cmac_0_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0); + cmac_0_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0); cnt_reset_out : out std_logic; slv_reg9_out : out std_logic_vector(31 downto 0); slv_reg10_out : out std_logic_vector(31 downto 0); - - slv_reg21_out : out std_logic_vector(31 downto 0); - slv_reg22_out : out std_logic_vector(31 downto 0); - slv_reg23_out : out std_logic_vector(31 downto 0); - slv_reg24_out : out std_logic_vector(31 downto 0); - slv_reg25_out : out std_logic_vector(31 downto 0); - slv_reg26_out : out std_logic_vector(31 downto 0); - slv_reg27_out : out std_logic_vector(31 downto 0); - slv_reg28_out : out std_logic_vector(31 downto 0); - slv_reg29_out : out std_logic_vector(31 downto 0); - slv_reg30_out : out std_logic_vector(31 downto 0); - - slv_reg31_out : out std_logic_vector(31 downto 0); - slv_reg32_out : out std_logic_vector(31 downto 0); - slv_reg33_out : out std_logic_vector(31 downto 0); - slv_reg34_out : out std_logic_vector(31 downto 0); - slv_reg35_out : out std_logic_vector(31 downto 0); - slv_reg36_out : out std_logic_vector(31 downto 0); - slv_reg37_out : out std_logic_vector(31 downto 0); - slv_reg38_out : out std_logic_vector(31 downto 0); - slv_reg39_out : out std_logic_vector(31 downto 0); - slv_reg40_out : out std_logic_vector(31 downto 0); - - slv_reg41_out : out std_logic_vector(31 downto 0); - slv_reg42_out : out std_logic_vector(31 downto 0); - slv_reg43_out : out std_logic_vector(31 downto 0); - slv_reg44_out : out std_logic_vector(31 downto 0); - slv_reg45_out : out std_logic_vector(31 downto 0); - slv_reg46_out : out std_logic_vector(31 downto 0); - slv_reg47_out : out std_logic_vector(31 downto 0); - slv_reg48_out : out std_logic_vector(31 downto 0); -- User ports ends -- Do not modify the ports beyond this line @@ -226,6 +204,16 @@ architecture arch_imp of qsfp_intfc_v1_0 is signal qsfp1_m_axis_tdata : std_logic_vector(239 downto 0); signal qsfp1_m_axis_tvalid : std_logic; +-- + signal qsfp2_reset_n_i : std_logic; + signal qsfp2_modprsl : std_logic; + signal qsfp2_intl : std_logic; + signal qsfp2_reset_n : std_logic; +-- + signal qsfp3_reset_n_i : std_logic; + signal qsfp3_modprsl : std_logic; + signal qsfp3_intl : std_logic; + signal qsfp3_reset_n : std_logic; -- signal qsfp4_axis_aclk : std_logic; signal qsfp4_axis_aresetn : std_logic; @@ -284,10 +272,6 @@ architecture arch_imp of qsfp_intfc_v1_0 is signal qsfp2_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0'); signal qsfp2_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp3_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal qsfp3_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp3_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - signal slv_reg0 : std_logic_vector(31 downto 0); signal slv_reg1 : std_logic_vector(31 downto 0); signal slv_reg2 : std_logic_vector(31 downto 0); @@ -375,39 +359,39 @@ begin slv_reg19_in => clk_250_freq_r, -- 0x8000_004C slv_reg20_in => clk_250_cnt_r, -- 0x8000_0050 - slv_reg21_out => slv_reg21_out, -- 0x8000_0054 - slv_reg22_out => slv_reg22_out, -- 0x8000_0058 - slv_reg23_out => slv_reg23_out, -- 0x8000_005C * - slv_reg24_out => slv_reg24_out, -- 0x8000_0060 - slv_reg25_out => slv_reg25_out, -- 0x8000_0064 * - slv_reg26_out => slv_reg26_out, -- 0x8000_0068 * - slv_reg27_out => slv_reg27_out, -- 0x8000_006C - slv_reg28_out => slv_reg28_out, -- 0x8000_0070 + slv_reg21_out => open, -- 0x8000_0054 + slv_reg22_out => open, -- 0x8000_0058 + slv_reg23_out => open, -- 0x8000_005C + slv_reg24_out => open, -- 0x8000_0060 + slv_reg25_out => open, -- 0x8000_0064 + slv_reg26_out => open, -- 0x8000_0068 + slv_reg27_out => open, -- 0x8000_006C + slv_reg28_out => open, -- 0x8000_0070 - slv_reg29_out => slv_reg29_out, -- 0x8000_0074 - slv_reg30_out => slv_reg30_out, -- 0x8000_0078 - slv_reg31_out => slv_reg31_out, -- 0x8000_007C * - slv_reg32_out => slv_reg32_out, -- 0x8000_0080 - slv_reg33_out => slv_reg33_out, -- 0x8000_0084 * - slv_reg34_out => slv_reg34_out, -- 0x8000_0088 * - slv_reg35_out => slv_reg35_out, -- 0x8000_008C - slv_reg36_out => slv_reg36_out, -- 0x8000_0090 + slv_reg29_out => open, -- 0x8000_0074 + slv_reg30_out => open, -- 0x8000_0078 + slv_reg31_out => open, -- 0x8000_007C + slv_reg32_out => open, -- 0x8000_0080 + slv_reg33_out => open, -- 0x8000_0084 + slv_reg34_out => open, -- 0x8000_0088 + slv_reg35_out => open, -- 0x8000_008C + slv_reg36_out => open, -- 0x8000_0090 - slv_reg37_out => slv_reg37_out, -- 0x8000_0094 - slv_reg38_out => slv_reg38_out, -- 0x8000_0098 - slv_reg39_out => slv_reg39_out, -- 0x8000_009C * - slv_reg40_out => slv_reg40_out, -- 0x8000_00A0 - slv_reg41_out => slv_reg41_out, -- 0x8000_00A4 * - slv_reg42_out => slv_reg42_out, -- 0x8000_00A8 * - slv_reg43_out => slv_reg43_out, -- 0x8000_00AC - slv_reg44_out => slv_reg44_out, -- 0x8000_00B0 - - slv_reg45_out => slv_reg45_out, -- 0x8000_00B4 - slv_reg46_out => slv_reg46_out, -- 0x8000_00B8 - slv_reg47_out => slv_reg47_out, -- 0x8000_00BC * - slv_reg48_out => slv_reg48_out, -- 0x8000_00C0 - slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4 * - slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8 * + slv_reg37_out => open, -- 0x8000_0094 + slv_reg38_out => open, -- 0x8000_0098 + slv_reg39_out => open, -- 0x8000_009C + slv_reg40_out => open, -- 0x8000_00A0 + slv_reg41_out => open, -- 0x8000_00A4 + slv_reg42_out => open, -- 0x8000_00A8 + slv_reg43_out => open, -- 0x8000_00AC + slv_reg44_out => open, -- 0x8000_00B0 + + slv_reg45_out => open, -- 0x8000_00B4 + slv_reg46_out => open, -- 0x8000_00B8 + slv_reg47_in => cmac_0_tx_tvalid_512b_cnt_in, -- 0x8000_00BC + slv_reg48_in => cmac_0_rx_tvalid_512b_cnt_in, -- 0x8000_00C0 + slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4 + slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8 slv_reg51_in => dig_iq_interface_ready_1_cnt_r, -- 0x8000_00CC slv_reg52_in => adc_rx_tvalid_128b_overflow_cnt_in, -- 0x8000_00D0 @@ -415,7 +399,7 @@ begin slv_reg54_in => qsfp1_capture_overflow_240b_cnt_in, -- 0x8000_00D8 slv_reg55_in => qsfp4_playback_tvalid_128b_cnt_in, -- 0x8000_00DC - slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0 + slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0 slv_reg57_in => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 0x8000_00E4 slv_reg58_in => adc_rx_tvalid_128b_cnt_in, -- 0x8000_00E8 slv_reg59_in => fiber_tx_tvalid_128b_cnt_in, -- 0x8000_00EC @@ -455,12 +439,12 @@ begin slv_reg1(2) <= qsfp1_intl; slv_reg1(3) <= '0'; slv_reg1(4) <= '0'; --dig_iq_interface_ready_1(0); - slv_reg1(5) <= '1'; --qsfp2_modprsl; - slv_reg1(6) <= '1'; --qsfp2_intl; + slv_reg1(5) <= qsfp2_modprsl; + slv_reg1(6) <= qsfp2_intl; slv_reg1(7) <= '0'; slv_reg1(8) <= '0'; --dig_iq_interface_ready_1(1); - slv_reg1(9) <= '1'; --qsfp3_modprsl; - slv_reg1(10) <= '1'; --qsfp3_intl; + slv_reg1(9) <= qsfp3_modprsl; + slv_reg1(10) <= qsfp3_intl; slv_reg1(11) <= '0'; slv_reg1(12) <= dig_iq_interface_ready(1); slv_reg1(13) <= qsfp4_modprsl; @@ -477,7 +461,9 @@ begin -- dig_iq_cmd_strb_i <= slv_reg5(0); -- 0x8000_0014 qsfp1_reset_n_i <= slv_reg5(16); - qsfp4_reset_n_i <= slv_reg5(24); + qsfp2_reset_n_i <= slv_reg5(20); + qsfp3_reset_n_i <= slv_reg5(24); + qsfp4_reset_n_i <= slv_reg5(28); -- dig_iq_cmd_wdata_i <= slv_reg6(31 downto 0); -- 0x8000_0018 -- @@ -512,6 +498,14 @@ begin QSFP1_RESETL_LS <= qsfp1_reset_n; qsfp1_modprsl <= QSFP1_MODPRSL_LS; qsfp1_intl <= QSFP1_INTL_LS; +------- + QSFP2_RESETL_LS <= qsfp2_reset_n; + qsfp2_modprsl <= QSFP2_MODPRSL_LS; + qsfp2_intl <= QSFP2_INTL_LS; +------- + QSFP3_RESETL_LS <= qsfp3_reset_n; + qsfp3_modprsl <= QSFP3_MODPRSL_LS; + qsfp3_intl <= QSFP3_INTL_LS; ------- QSFP4_TX1_P <= qsfp4_tx_txp(0); QSFP4_TX1_N <= qsfp4_tx_txn(0); @@ -545,6 +539,8 @@ begin qsfp1_reset_n <= qsfp1_reset_n_i; dig_iq_interface_reset(0) <= not qsfp1_reset_n; + qsfp2_reset_n <= qsfp2_reset_n_i; + qsfp3_reset_n <= qsfp3_reset_n_i; qsfp4_reset_n <= qsfp4_reset_n_i; dig_iq_interface_reset(1) <= not qsfp4_reset_n; @@ -870,20 +866,6 @@ begin end if; end process; - process(qsfp3_clk_in) - begin - if (rising_edge(qsfp3_clk_in)) then - qsfp3_clk_tick_1ms_r <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms; - if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then - qsfp3_clk_freq_r <= qsfp3_clk_cnt_r; - qsfp3_clk_cnt_r <= (others => '0'); - else - qsfp3_clk_cnt_r <= qsfp3_clk_cnt_r + 1; - end if; - end if; - end process; - - process(pl_clk3_0) begin if (rising_edge(pl_clk3_0)) then diff --git a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd index 39c8905..86bc56c 100644 --- a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd +++ b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd @@ -68,8 +68,8 @@ entity qsfp_intfc_v1_0_S00_AXI is slv_reg44_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg45_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg46_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - slv_reg47_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - slv_reg48_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + slv_reg47_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + slv_reg48_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg49_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg50_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg51_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); @@ -374,41 +374,41 @@ begin slv_reg19 <= (others => '0'); slv_reg20 <= (others => '0'); - slv_reg21 <= x"00008000"; --(UP-SWEEP) from 1MHz to 5MHz in 5uS - slv_reg22 <= x"00000000"; - slv_reg23 <= x"0000D6BF"; - slv_reg24 <= x"00000000"; - slv_reg25 <= x"000004E2"; --(~5 us) - slv_reg26 <= x"010624DD"; --(~1 MHz) - slv_reg27 <= x"00000000"; - slv_reg28 <= x"00008000"; + slv_reg21 <= (others => '0'); + slv_reg22 <= (others => '0'); + slv_reg23 <= (others => '0'); + slv_reg24 <= (others => '0'); + slv_reg25 <= (others => '0'); + slv_reg26 <= (others => '0'); + slv_reg27 <= (others => '0'); + slv_reg28 <= (others => '0'); - slv_reg29 <= x"00008000"; --(DOWN-SWEEP) - slv_reg30 <= x"00000000"; - slv_reg31 <= x"00FEF391"; - slv_reg32 <= x"00000000"; - slv_reg33 <= x"000004E2"; --(~5 us) - slv_reg34 <= x"0624DD2F"; --(~6 MHz) - slv_reg35 <= x"00000000"; - slv_reg36 <= x"00008000"; + slv_reg29 <= (others => '0'); + slv_reg30 <= (others => '0'); + slv_reg31 <= (others => '0'); + slv_reg32 <= (others => '0'); + slv_reg33 <= (others => '0'); + slv_reg34 <= (others => '0'); + slv_reg35 <= (others => '0'); + slv_reg36 <= (others => '0'); - slv_reg37 <= x"00008000"; --(CW) - slv_reg38 <= x"00000000"; - slv_reg39 <= x"00000000"; - slv_reg40 <= x"00000000"; - slv_reg41 <= x"000004E2"; --(~5 us) - slv_reg42 <= x"0A3D70A3"; --(~10 MHz) - slv_reg43 <= x"00000000"; - slv_reg44 <= x"00008000"; + slv_reg37 <= (others => '0'); + slv_reg38 <= (others => '0'); + slv_reg39 <= (others => '0'); + slv_reg40 <= (others => '0'); + slv_reg41 <= (others => '0'); + slv_reg42 <= (others => '0'); + slv_reg43 <= (others => '0'); + slv_reg44 <= (others => '0'); - slv_reg45 <= x"00008000"; --(CW) - slv_reg46 <= x"00000000"; - slv_reg47 <= x"00000000"; - slv_reg48 <= x"00000000"; - slv_reg49 <= x"000004E2"; --(~5 us) - slv_reg50 <= x"0F5C28F5"; --(~15 MHz) - slv_reg51 <= x"00000000"; - slv_reg52 <= x"00008000"; + slv_reg45 <= (others => '0'); + slv_reg46 <= (others => '0'); + slv_reg47 <= (others => '0'); + slv_reg48 <= (others => '0'); + slv_reg49 <= (others => '0'); + slv_reg50 <= (others => '0'); + slv_reg51 <= (others => '0'); + slv_reg52 <= (others => '0'); slv_reg53 <= (others => '0'); slv_reg54 <= (others => '0'); @@ -1202,9 +1202,9 @@ begin when b"101110" => reg_data_out <= slv_reg46; when b"101111" => - reg_data_out <= slv_reg47; + reg_data_out <= slv_reg47_in; when b"110000" => - reg_data_out <= slv_reg48; + reg_data_out <= slv_reg48_in; when b"110001" => reg_data_out <= slv_reg49_in; --slv_reg49; when b"110010" => @@ -1314,8 +1314,6 @@ begin slv_reg44_out <= slv_reg44; slv_reg45_out <= slv_reg45; slv_reg46_out <= slv_reg46; - slv_reg47_out <= slv_reg47; - slv_reg48_out <= slv_reg48; -- User logic ends diff --git a/sim/dds_wrapper_tb.vhd b/sim/dds_wrapper_tb.vhd deleted file mode 100644 index c833f3d..0000000 --- a/sim/dds_wrapper_tb.vhd +++ /dev/null @@ -1,316 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:53:22 03/24/2017 --- Design Name: --- Module Name: --- Project Name: xem7350 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: dac_interface --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE IEEE.STD_LOGIC_arith.ALL; -USE IEEE.STD_LOGIC_unsigned.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -Library xpm; -use xpm.vcomponents.all; - ---library UNISIM; ---use UNISIM.VComponents.all; - -entity dds_wrapper_tb is -end dds_wrapper_tb; - -architecture behavior of dds_wrapper_tb is - - -- Clock period definitions - constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz - constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz - constant CLK_100_PERIOD : time := 10 ns; -- 100 MHz - constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz - constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz - constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - - signal clk_100 : std_logic := '0'; - signal clk_100_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_250 : std_logic := '0'; - signal clk_250_aresetn : std_logic_vector(0 to 63) := x"0000_FFFF_0000_0000";--(others => '0'); - - signal m_axis_tready_r : std_logic := '0'; - signal m_axis_tdata : std_logic_vector(127 downto 0); - signal m_axis_tvalid : std_logic; - signal m_axis_tready : std_logic; - - signal util_mxfe_upack_s_axis_tdata_pipe : std_logic_vector(127 downto 0); - signal util_mxfe_upack_s_axis_tvalid_pipe : std_logic; - - signal m_axis_tdata_1 : std_logic_vector(127 downto 0); - signal m_axis_tvalid_1 : std_logic; - signal m_axis_tready_1 : std_logic; - - signal cmd_send_i : std_logic_vector(0 to 3) := (others => '0'); - signal dac_holdoff_r : std_logic := '1'; - - signal chan1_i : std_logic_vector(15 downto 0); - signal chan1_q : std_logic_vector(15 downto 0); - signal chan2_i : std_logic_vector(15 downto 0); - signal chan2_q : std_logic_vector(15 downto 0); - signal chan3_i : std_logic_vector(15 downto 0); - signal chan3_q : std_logic_vector(15 downto 0); - signal chan4_i : std_logic_vector(15 downto 0); - signal chan4_q : std_logic_vector(15 downto 0); - - signal cmd_send_0_r : std_logic_vector(0 to 2) := (others => '0'); - signal cmd_send_1_r : std_logic_vector(0 to 2) := (others => '0'); - signal cmd_send_2_r : std_logic_vector(0 to 2) := (others => '0'); - signal cmd_send_3_r : std_logic_vector(0 to 2) := (others => '0'); - signal cnt_reset : std_logic := '0'; - -begin - - clk_100 <= not clk_100 after CLK_100_PERIOD/2; - clk_250 <= not clk_250 after CLK_250_PERIOD/2; - - --- - process(clk_100) - begin - if (rising_edge(clk_100)) then - clk_100_aresetn <= clk_100_aresetn(1 to 15) & '1'; - end if; - end process; - --- - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_aresetn <= clk_250_aresetn(1 to 63) & '1'; - end if; - end process; - - - process (clk_100) - begin - if rising_edge(clk_100) then - if (cmd_send_i(0) = '1') then - cmd_send_0_r <= "111"; - else - cmd_send_0_r <= cmd_send_0_r(1 to 2) & '0'; - end if; - - if (cmd_send_i(1) = '1') then - cmd_send_1_r <= "111"; - else - cmd_send_1_r <= cmd_send_1_r(1 to 2) & '0'; - end if; - - if (cmd_send_i(2) = '1') then - cmd_send_2_r <= "111"; - else - cmd_send_2_r <= cmd_send_2_r(1 to 2) & '0'; - end if; - - if (cmd_send_i(3) = '1') then - cmd_send_3_r <= "111"; - else - cmd_send_3_r <= cmd_send_3_r(1 to 2) & '0'; - end if; - end if; - end process; - - - i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4 - port map ( - s_axi_aclk_in => clk_100, - s_axi_aresetn_in => clk_100_aresetn(0), - - cmd_idx_in => "000", - dac_holdoff_in => dac_holdoff_r, - dds_chan_en_in => "1111", - - cmd_send_0_in => cmd_send_0_r(0), - scale_0_in => x"8000", - dds_phase_inc_dwell_time_0_in => x"00000000", - dds_phase_inc_step_size_0_in => x"0000D6BF", - idle_samples_0_in => x"00000000", - dds_samples_0_in => x"000004E2", - phase_inc_0_in => x"010624DD", - phase_off_0_in => x"00000000", - swap_sf_0_in => x"00008000", - - cmd_send_1_in => cmd_send_1_r(0), - scale_1_in => x"8000", - dds_phase_inc_dwell_time_1_in => x"00000000", - dds_phase_inc_step_size_1_in => x"0000D6BF", - idle_samples_1_in => x"00000000", - dds_samples_1_in => x"000014E2", --x"000004E2", - phase_inc_1_in => x"010624DD", - phase_off_1_in => x"00000000", - swap_sf_1_in => x"00008000", - - cmd_send_2_in => cmd_send_2_r(0), - scale_2_in => x"8000", - dds_phase_inc_dwell_time_2_in => x"00000000", - dds_phase_inc_step_size_2_in => x"0000D6BF", - idle_samples_2_in => x"00000000", - dds_samples_2_in => x"000004E2", - phase_inc_2_in => x"010624DD", - phase_off_2_in => x"00000000", - swap_sf_2_in => x"00008000", - - cmd_send_3_in => cmd_send_3_r(0), - scale_3_in => x"8000", - dds_phase_inc_dwell_time_3_in => x"00000000", - dds_phase_inc_step_size_3_in => x"0000D6BF", - idle_samples_3_in => x"00000000", - dds_samples_3_in => x"000004E2", - phase_inc_3_in => x"010624DD", - phase_off_3_in => x"00000000", - swap_sf_3_in => x"00008000", - - m_axis_aclk_in => clk_250, - m_axis_aresetn_in => clk_250_aresetn(0), - m_axis_tdata_out => m_axis_tdata, - m_axis_tvalid_out => m_axis_tvalid, - m_axis_tready_in => m_axis_tready, - - cnt_reset_in => cnt_reset, - m_axis_tvalid_cnt_out => open, - dds_pulse_data_cnt_out => open - ); - - - -- big FIFO before JESD TX PORT - i_dac_data_fifo_32kx128 : entity work.axis_data_fifo_32kx128 - port map ( - s_axis_aclk => clk_250, -- in - s_axis_aresetn => clk_250_aresetn(0), -- in - s_axis_tdata => m_axis_tdata, -- in - s_axis_tvalid => m_axis_tvalid, -- in - s_axis_tready => m_axis_tready, -- out - - m_axis_tdata => m_axis_tdata_1, -- out - m_axis_tvalid => m_axis_tvalid_1, -- out - m_axis_tready => m_axis_tready_1 -- in - ); - - -- big FIFO before JESD TX PORT - i_dac_data_fifo_32kx128_1 : entity work.axis_data_fifo_32kx128 - port map ( - s_axis_aclk => clk_250, -- in - s_axis_aresetn => clk_250_aresetn(0), -- in - s_axis_tdata => m_axis_tdata_1, -- in - s_axis_tvalid => m_axis_tvalid_1, -- in - s_axis_tready => m_axis_tready_1, -- out - - m_axis_tdata => util_mxfe_upack_s_axis_tdata_pipe, -- out - m_axis_tvalid => util_mxfe_upack_s_axis_tvalid_pipe, -- out - m_axis_tready => m_axis_tready_r -- in - ); - - - chan1_i <= util_mxfe_upack_s_axis_tdata_pipe(15 downto 0); - chan1_q <= util_mxfe_upack_s_axis_tdata_pipe(31 downto 16); - - chan2_i <= util_mxfe_upack_s_axis_tdata_pipe(47 downto 32); - chan2_q <= util_mxfe_upack_s_axis_tdata_pipe(63 downto 48); - - chan3_i <= util_mxfe_upack_s_axis_tdata_pipe(79 downto 64); - chan3_q <= util_mxfe_upack_s_axis_tdata_pipe(95 downto 80); - - chan4_i <= util_mxfe_upack_s_axis_tdata_pipe(111 downto 96); - chan4_q <= util_mxfe_upack_s_axis_tdata_pipe(127 downto 112); - - -- Stimulus process - stim_proc: process - begin - - wait until clk_100_aresetn(0) = '1'; - - -- wait for 24 us; - - wait until rising_edge(clk_250); - m_axis_tready_r <= '1'; - wait for 1 us; - - wait until rising_edge(clk_100); - cmd_send_i(0) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(0) <= '0'; - wait for 1 us; - wait until rising_edge(clk_100); - cmd_send_i(1) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(1) <= '0'; - - wait for 1 us; - wait until rising_edge(clk_100); - cmd_send_i(2) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(2) <= '0'; - - wait for 1 us; - wait until rising_edge(clk_100); - cmd_send_i(3) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(3) <= '0'; - - wait for 1 us; - wait until rising_edge(clk_100); - dac_holdoff_r <= '0'; - - - wait for 8 us; - cnt_reset <= '1'; - wait until rising_edge(clk_100); - cnt_reset <= '0'; - - -- m_axis_tready_r <= '0'; - -- wait until rising_edge(clk_250); - - - -- m_axis_tready_r <= '1'; - -- wait until rising_edge(clk_250); - - - -- m_axis_tready_r <= '0'; - -- wait until rising_edge(clk_250); - - - -- m_axis_tready_r <= '1'; - - wait until rising_edge(clk_100); - - wait; -- wait here forever - end process; - - - -end; diff --git a/sim/tb_cap_plybk.vhd b/sim/tb_cap_plybk.vhd deleted file mode 100644 index 3d7d0b6..0000000 --- a/sim/tb_cap_plybk.vhd +++ /dev/null @@ -1,286 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:53:22 03/24/2017 --- Design Name: --- Module Name: --- Project Name: xem7350 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: dac_interface --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE IEEE.STD_LOGIC_arith.ALL; -USE IEEE.STD_LOGIC_unsigned.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -entity tb_cap_plybk is -end tb_cap_plybk; - -architecture behavior of tb_cap_plybk is - - constant C_M_AXI_DATA_WIDTH : integer := 32; - constant C_M_AXI_ADDR_WIDTH : integer := 32; - - -- Clock period definitions - constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz - constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz - constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz - constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz - constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - - signal clk_125 : std_logic := '0'; - signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_125_reset : std_logic; - - signal clk_250 : std_logic := '0'; - signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_250_areset : std_logic; - - signal tx_device_clk_1 : std_logic := '0'; - signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal tx_device_clk_aresetn : std_logic; - - signal rx_device_clk_1 : std_logic := '0'; - signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal rx_device_clk_aresetn : std_logic; - signal rx_device_clk_areset : std_logic; - - signal qsfp4_playback_aclk : std_logic := '0'; - signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp4_playback_aresetn : std_logic; - - signal qsfp1_capture_aclk : std_logic; - signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp1_capture_aresetn : std_logic; - - --- - signal tick_1ms : std_logic; - - signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - - signal adc_rx_tdata_128b : std_logic_vector(127 downto 0) := (others => '0'); - signal adc_rx_tvalid_128b : std_logic := '0'; - signal adc_rx_tready_128b : std_logic; - signal adc_rx_tvalid_128b_cnt : std_logic_vector(31 downto 0); - - - - signal qsfp4_playback_tdata_240b : std_logic_vector(239 downto 0); - signal qsfp4_playback_tvalid_240b : std_logic; - signal qsfp4_playback_tready_240b : std_logic := '1'; - - - signal qsfp1_capture_tdata_240b : std_logic_vector(239 downto 0); - signal qsfp1_capture_tvalid_240b : std_logic; - - - signal tx_tdata_128b : std_logic_vector(127 downto 0); - signal tx_tvalid_128b : std_logic; - signal tx_tready_128b : std_logic := '1'; - - signal qsfp1_capture_rx_data_ready : std_logic; - - signal playback_data_path_enable_n : std_logic := '1'; - - signal adc_rx_tvalid_128b_ena : std_logic; - -begin - - clk_125 <= not clk_125 after CLK_125_PERIOD/2; - clk_250 <= not clk_250 after CLK_250_PERIOD/2; - tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2; - rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2; - - qsfp4_playback_aclk <= not qsfp4_playback_aclk after QSFP4_AXIS_ACLK_PERIOD/2; --- qsfp1_capture_aclk <= not qsfp1_capture_aclk after QSFP1_AXIS_ACLK_PERIOD/2; - --- - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_125_reset <= not clk_125_aresetn(0); --- - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_250_areset <= not clk_250_aresetn(0); --- - process(tx_device_clk_1) - begin - if (rising_edge(tx_device_clk_1)) then - tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1'; - end if; - end process; - - tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0); - --- - process(rx_device_clk_1) - begin - if (rising_edge(rx_device_clk_1)) then - rx_device_clk_aresetn_r <= rx_device_clk_aresetn_r(1 to 15) & '1'; - end if; - end process; - - rx_device_clk_aresetn <= rx_device_clk_aresetn_r(0); - --- - process(qsfp4_playback_aclk) - begin - if (rising_edge(qsfp4_playback_aclk)) then - qsfp4_axis_aresetn_r <= qsfp4_axis_aresetn_r(1 to 15) & '1'; - end if; - end process; - - qsfp4_playback_aresetn <= qsfp4_axis_aresetn_r(0); - - --- - process(rx_device_clk_1) - begin - if (rising_edge(rx_device_clk_1)) then - adc_rx_tdata_128b <= adc_rx_tdata_128b + x"0003_0002_0001_0004_0005_0006_0007_0008"; - end if; - end process; - --- - process(qsfp1_capture_aclk) - begin - if (rising_edge(qsfp1_capture_aclk)) then - qsfp1_axis_aresetn_r <= qsfp1_axis_aresetn_r(1 to 15) & '1'; - end if; - end process; - - qsfp1_capture_aresetn <= qsfp1_axis_aresetn_r(0); - - adc_rx_tvalid_128b_ena <= adc_rx_tvalid_128b and qsfp1_capture_rx_data_ready; - - i_qsfp4_playback_intfc : entity work.qsfp4_playback_intfc - port map ( - rx_device_clk_in => rx_device_clk_1, - rx_device_clk_aresetn_in => rx_device_clk_aresetn, - rx_tdata_128b_in => adc_rx_tdata_128b, - rx_tvalid_128b_in => adc_rx_tvalid_128b_ena, - rx_tready_128b_out => adc_rx_tready_128b, - rx_tvalid_128b_cnt_out => adc_rx_tvalid_128b_cnt, - rx_tvalid_128b_en_cnt_out => open, - playback_data_path_enable_n_in => playback_data_path_enable_n, - - qsfp4_playback_aclk_in => qsfp4_playback_aclk, - qsfp4_playback_aresetn_in => qsfp4_playback_aresetn, - qsfp4_playback_tdata_240b_out => qsfp4_playback_tdata_240b, - qsfp4_playback_tvalid_240b_out => qsfp4_playback_tvalid_240b, - qsfp4_playback_tready_240b_in => qsfp4_playback_tready_240b, - qsfp4_playback_tvalid_240b_cnt_out => open, - - cnt_reset_in => '0' - ); - ---/////////////////////////////// - - qsfp1_capture_aclk <= qsfp4_playback_aclk; -- - qsfp1_capture_tdata_240b <= qsfp4_playback_tdata_240b; -- - qsfp1_capture_tvalid_240b <= qsfp4_playback_tvalid_240b; -- - - ---/////////////////////////////// ---// ****>>>> FROM QSFP1 CAPTURE INTERFACE - i_qsfp1_capture_intfc : entity work.qsfp1_capture_intfc - port map ( - qsfp1_capture_aclk_in => qsfp1_capture_aclk, - qsfp1_capture_aresetn_in => qsfp1_capture_aresetn, - qsfp1_capture_tdata_240b_in => qsfp1_capture_tdata_240b, - qsfp1_capture_tvalid_240b_in => qsfp1_capture_tvalid_240b, - qsfp1_capture_tvalid_240b_cnt_out => open, - qsfp1_capture_fifo_aempty_512b_cnt_out => open, - qsfp1_capture_iq_240b_to_512b_overflow_cnt_out => open, - - qsfp1_capture_rx_data_ready_out => qsfp1_capture_rx_data_ready, - qsfp1_capture_rx_data_ready_cnt_out => open, - - tx_device_clk_in => tx_device_clk_1, - tx_device_clk_aresetn_in => tx_device_clk_aresetn, - tx_tdata_128b_out => tx_tdata_128b, -- out - tx_tvalid_128b_out => tx_tvalid_128b, -- out - tx_tready_128b_in => tx_tready_128b, -- in - tx_tvalid_128b_cnt_out => open, - - cnt_reset_in => '0' - ); - - - - -- Stimulus process - stim_proc: process - begin - - wait until rx_device_clk_aresetn = '1'; - - wait for 200 ns; - - - wait until rising_edge(rx_device_clk_1); - adc_rx_tvalid_128b <= '1'; - - wait for 500 ns; - wait until rising_edge(rx_device_clk_1); - playback_data_path_enable_n <= '0'; - - wait for 5 us; - wait until rising_edge(qsfp4_playback_aclk); - playback_data_path_enable_n <='0'; - - wait for 5 us; - wait until rising_edge(qsfp4_playback_aclk); - qsfp4_playback_tready_240b <='1'; - - wait; -- wait here forever - end process; - - -end; diff --git a/sim/tb_cap_plybk_behav.wcfg b/sim/tb_cap_plybk_behav.wcfg deleted file mode 100644 index 1f35420..0000000 --- a/sim/tb_cap_plybk_behav.wcfg +++ /dev/null @@ -1,141 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - rx_device_clk_1 - rx_device_clk_1 - - - rx_device_clk_aresetn_r[0:15] - rx_device_clk_aresetn_r[0:15] - - - rx_device_clk_aresetn - rx_device_clk_aresetn - - - qsfp4_playback_aclk - qsfp4_playback_aclk - - - qsfp4_axis_aresetn_r[0:15] - qsfp4_axis_aresetn_r[0:15] - - - qsfp4_playback_aresetn - qsfp4_playback_aresetn - - - adc_rx_tdata_128b[127:0] - adc_rx_tdata_128b[127:0] - - - adc_rx_tvalid_128b - adc_rx_tvalid_128b - - - adc_rx_tready_128b - adc_rx_tready_128b - - - adc_rx_tdata_128b_overflow - adc_rx_tdata_128b_overflow - - - rx_tvalid_128b_cnt_out[31:0] - rx_tvalid_128b_cnt_out[31:0] - - - rx_tvalid_128b_en_cnt_out[31:0] - rx_tvalid_128b_en_cnt_out[31:0] - - - qsfp4_playback_tdata_240b[239:0] - qsfp4_playback_tdata_240b[239:0] - - - qsfp4_playback_tvalid_240b - qsfp4_playback_tvalid_240b - - - qsfp4_playback_tready_240b - qsfp4_playback_tready_240b - - - qsfp4_playback_tvalid_240b_cnt_out[31:0] - qsfp4_playback_tvalid_240b_cnt_out[31:0] - - - playback_data_path_enable_n - playback_data_path_enable_n - - - qsfp1_capture_tdata_240b[239:0] - qsfp1_capture_tdata_240b[239:0] - - - qsfp1_capture_tvalid_240b - qsfp1_capture_tvalid_240b - - - qsfp1_capture_rx_data_ready - qsfp1_capture_rx_data_ready - - - qsfp1_capture_rx_data_ready_cnt_out[31:0] - qsfp1_capture_rx_data_ready_cnt_out[31:0] - - - qsfp1_capture_fifo_aempty_512b_cnt_out[31:0] - qsfp1_capture_fifo_aempty_512b_cnt_out[31:0] - - - qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0] - qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0] - - - tx_tdata_128b[127:0] - tx_tdata_128b[127:0] - - - tx_tvalid_128b - tx_tvalid_128b - - - tx_tready_128b - tx_tready_128b - - - qsfp1_tready_512b - qsfp1_tready_512b - - - qsfp1_tready_512b_pipe - qsfp1_tready_512b_pipe - - - qsfp1_tready_128b - qsfp1_tready_128b - - diff --git a/sim/test_bench.vhd b/sim/test_bench.vhd deleted file mode 100644 index 5fbe485..0000000 --- a/sim/test_bench.vhd +++ /dev/null @@ -1,188 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:53:22 03/24/2017 --- Design Name: --- Module Name: --- Project Name: xem7350 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: dac_interface --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE IEEE.STD_LOGIC_arith.ALL; -USE IEEE.STD_LOGIC_unsigned.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -entity test_bench is -end test_bench; - -architecture behavior of test_bench is - - constant C_M_AXI_DATA_WIDTH : integer := 32; - constant C_M_AXI_ADDR_WIDTH : integer := 32; - - -- Clock period definitions - constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz - constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz - constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz - constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz - constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - - signal clk_125 : std_logic := '0'; - signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_125_reset : std_logic; - - signal clk_250 : std_logic := '0'; - signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_250_areset : std_logic; - - signal tx_device_clk_1 : std_logic := '0'; - signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal tx_device_clk_aresetn : std_logic; - - signal rx_device_clk_1 : std_logic := '0'; - signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal rx_device_clk_aresetn : std_logic; - signal rx_device_clk_areset : std_logic; - - signal qsfp4_axis_aclk : std_logic := '0'; - signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp4_axis_aresetn : std_logic; - - signal qsfp1_axis_aclk : std_logic := '0'; - signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp1_axis_aresetn : std_logic; - - --- - signal tick_1ms : std_logic; - - signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - - -begin - - clk_125 <= not clk_125 after CLK_125_PERIOD/2; - clk_250 <= not clk_250 after CLK_250_PERIOD/2; - tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2; - rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2; - - qsfp4_axis_aclk <= not qsfp4_axis_aclk after QSFP4_AXIS_ACLK_PERIOD/2; - qsfp1_axis_aclk <= not qsfp1_axis_aclk after QSFP1_AXIS_ACLK_PERIOD/2; - --- - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_125_reset <= not clk_125_aresetn(0); --- - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_250_areset <= not clk_250_aresetn(0); --- - process(tx_device_clk_1) - begin - if (rising_edge(tx_device_clk_1)) then - tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1'; - end if; - end process; - - tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0); - - ------------------------------------------------- - i_tick_gen : entity work.tick_gen - generic map ( - CLOCK_SPEED_MHZ => 125 - ) - port map ( - clk_in => clk_125, - - tick_1us_out => open, - tick_1ms_out => tick_1ms, - tick_500ms_out => open, - tick_750ms_out => open, - tick_1s_out => open, - - prog_us_tick_rate_in => x"0000_0000", - prog_us_tick_out => open, - - reset_in => clk_125_reset - ); - - - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms; - if (clk_125_tick_1ms_r(0 to 1) = "01") then - clk_125_freq_r <= clk_125_cnt_r; - clk_125_cnt_r <= (others => '0'); - else - clk_125_cnt_r <= clk_125_cnt_r + 1; - end if; - end if; - end process; - - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms; - if (clk_250_tick_1ms_r(0 to 1) = "01") then - clk_250_freq_r <= clk_250_cnt_r; - clk_250_cnt_r <= (others => '0'); - else - clk_250_cnt_r <= clk_250_cnt_r + 1; - end if; - end if; - end process; - - - - -end; diff --git a/source/axis_demux_128b.vhd b/source/axis_demux_128b.vhd new file mode 100644 index 0000000..b63bf2e --- /dev/null +++ b/source/axis_demux_128b.vhd @@ -0,0 +1,46 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library xpm; +use xpm.vcomponents.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity axis_demux_128b is + port ( + aselect : in std_logic; + + s_axis_tdata : in std_logic_vector(127 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + + m0_axis_tdata : out std_logic_vector(127 downto 0); + m0_axis_tvalid : out std_logic; + m0_axis_tready : in std_logic; + + m1_axis_tdata : out std_logic_vector(127 downto 0); + m1_axis_tvalid : out std_logic; + m1_axis_tready : in std_logic + ); +end entity axis_demux_128b; + +architecture imp of axis_demux_128b is + +begin + + m0_axis_tdata <= s_axis_tdata; + m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0'; + + m1_axis_tdata <= s_axis_tdata; + m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0'; + + s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready; + +end imp; + diff --git a/source/axis_mux_128b.vhd b/source/axis_mux_128b.vhd index 7783575..fbd3207 100644 --- a/source/axis_mux_128b.vhd +++ b/source/axis_mux_128b.vhd @@ -14,9 +14,7 @@ use xpm.vcomponents.all; entity axis_mux_128b is port ( - aclk : in STD_LOGIC; - aresetn : in std_logic; - aselect : in std_logic_vector(1 downto 0); + aselect : in std_logic_vector(2 downto 0); s0_axis_tdata : in std_logic_vector(127 downto 0); s0_axis_tvalid : in std_logic; @@ -34,6 +32,10 @@ entity axis_mux_128b is s3_axis_tvalid : in std_logic; s3_axis_tready : out std_logic; + s4_axis_tdata : in std_logic_vector(127 downto 0); + s4_axis_tvalid : in std_logic; + s4_axis_tready : out std_logic; + m_axis_tdata : out std_logic_vector(127 downto 0); m_axis_tvalid : out std_logic; m_axis_tready : in std_logic @@ -43,23 +45,24 @@ end entity axis_mux_128b; architecture imp of axis_mux_128b is begin - - m_axis_tdata <= s0_axis_tdata when aselect = "00" else - s1_axis_tdata when aselect = "01" else - s2_axis_tdata when aselect = "10" else - s3_axis_tdata; + m_axis_tdata <= s0_axis_tdata when aselect = "000" else + s1_axis_tdata when aselect = "001" else + s2_axis_tdata when aselect = "010" else + s3_axis_tdata when aselect = "011" else + s4_axis_tdata; - m_axis_tvalid <= s0_axis_tvalid when aselect = "00" else - s1_axis_tvalid when aselect = "01" else - s2_axis_tvalid when aselect = "10" else - s3_axis_tvalid; + m_axis_tvalid <= s0_axis_tvalid when aselect = "000" else + s1_axis_tvalid when aselect = "001" else + s2_axis_tvalid when aselect = "010" else + s3_axis_tvalid when aselect = "011" else + s4_axis_tvalid; - s0_axis_tready <= m_axis_tready when aselect = "00" else '0'; - s1_axis_tready <= m_axis_tready when aselect = "01" else '0'; - s2_axis_tready <= m_axis_tready when aselect = "10" else '0'; - s3_axis_tready <= m_axis_tready when aselect = "11" else '0'; - + s0_axis_tready <= m_axis_tready when aselect = "000" else '0'; + s1_axis_tready <= m_axis_tready when aselect = "001" else '0'; + s2_axis_tready <= m_axis_tready when aselect = "010" else '0'; + s3_axis_tready <= m_axis_tready when aselect = "011" else '0'; + s4_axis_tready <= m_axis_tready when aselect = "100" else '0'; end imp; diff --git a/source/axis_mux_512b.vhd b/source/axis_mux_512b.vhd new file mode 100644 index 0000000..36a9109 --- /dev/null +++ b/source/axis_mux_512b.vhd @@ -0,0 +1,47 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library xpm; +use xpm.vcomponents.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity axis_mux_512b is + port ( + aselect : in std_logic; + + s0_axis_tdata : in std_logic_vector(511 downto 0); + s0_axis_tvalid : in std_logic; + s0_axis_tready : out std_logic; + + s1_axis_tdata : in std_logic_vector(511 downto 0); + s1_axis_tvalid : in std_logic; + s1_axis_tready : out std_logic; + + m_axis_tdata : out std_logic_vector(511 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic + ); +end entity axis_mux_512b; + +architecture imp of axis_mux_512b is + +begin + + m_axis_tdata <= s0_axis_tdata when aselect = '0' else + s1_axis_tdata; + + m_axis_tvalid <= s0_axis_tvalid when aselect = '0' else + s1_axis_tvalid; + + s0_axis_tready <= m_axis_tready when aselect = '0' else '0'; + s1_axis_tready <= m_axis_tready when aselect = '1' else '0'; + +end imp; + diff --git a/source/axis_mux_s2_128b.vhd b/source/axis_mux_s2_128b.vhd index 2490caa..7663261 100644 --- a/source/axis_mux_s2_128b.vhd +++ b/source/axis_mux_s2_128b.vhd @@ -14,8 +14,6 @@ use xpm.vcomponents.all; entity axis_mux_s2_128b is port ( - aclk : in STD_LOGIC; - aresetn : in std_logic; aselect : in std_logic; s0_axis_tdata : in std_logic_vector(127 downto 0); diff --git a/source/eth_flowctrl_rx.vhd b/source/eth_flowctrl_rx.vhd new file mode 100644 index 0000000..9c05693 --- /dev/null +++ b/source/eth_flowctrl_rx.vhd @@ -0,0 +1,79 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M Blevins +-- +-- Create Date: 01/05/2026 11:59:12 AM +-- Design Name: +-- Module Name: eth_flowctrl_rx - behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eth_flowctrl_rx is + Port ( + clk : in STD_LOGIC; + resetn : in STD_LOGIC; + rx_pause : in STD_LOGIC; + rx_pause_quanta8 : in STD_LOGIC_VECTOR(15 downto 0); + rx_pause_cnt : out std_logic_vector(31 downto 0); + pause : out STD_LOGIC + ); +end eth_flowctrl_rx; + +architecture behavioral of eth_flowctrl_rx is + + signal pause_r : std_logic := '0'; + signal cnt_r : unsigned(15 downto 0) := (others => '0'); + signal rx_pause_cnt_r : unsigned(31 downto 0) := (others => '0'); + +begin + + pause <= pause_r; + rx_pause_cnt <= std_logic_vector(rx_pause_cnt_r); + + process(clk) + begin + if(rising_edge(clk))then + if(resetn = '0')then + cnt_r <= (others => '0'); + pause_r <= '0'; + rx_pause_cnt_r <= (others => '0'); + else + if(rx_pause = '1')then + rx_pause_cnt_r <= rx_pause_cnt_r +1; + cnt_r <= unsigned(rx_pause_quanta8); + if(unsigned(rx_pause_quanta8) = 0)then + pause_r <= '0'; + else + pause_r <= '1'; + end if; + else + if(cnt_r > 0)then + cnt_r <= cnt_r -1; + end if; + if(cnt_r = 1)then + pause_r <= '0'; + end if; + end if; + end if; + end if; + end process; + + +end behavioral; diff --git a/source/eth_flowctrl_tx.vhd b/source/eth_flowctrl_tx.vhd new file mode 100644 index 0000000..364133c --- /dev/null +++ b/source/eth_flowctrl_tx.vhd @@ -0,0 +1,135 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M Blevins +-- +-- Create Date: 01/05/2026 11:59:12 AM +-- Design Name: +-- Module Name: eth_flowctrl_tx - behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eth_flowctrl_tx is + Port ( + clk : in STD_LOGIC; + resetn : in STD_LOGIC; + prog_full_manual : in STD_LOGIC; + data_cnt : in STD_LOGIC_VECTOR(31 downto 0); + prog_full_on : in STD_LOGIC_VECTOR(31 downto 0); + prog_full_off : in STD_LOGIC_VECTOR(31 downto 0); + ctl_tx_resend_pause : out STD_LOGIC; + ctl_tx_pause_req : out STD_LOGIC_VECTOR (8 downto 0); + tx_pause_cnt : out std_logic_vector(31 downto 0) + ); +end eth_flowctrl_tx; + +architecture behavioral of eth_flowctrl_tx is + + signal cnt : unsigned(3 downto 0); + signal cnt_r : unsigned(3 downto 0) := (others => '0'); + signal tx_pause_cnt_i : unsigned(31 downto 0); + signal tx_pause_cnt_r : unsigned(31 downto 0) := (others => '0'); + type state_type is (s0, s1, s2, s3); + signal state : state_type; + signal state_r : state_type := s0; + signal resend_pause : std_logic; + signal pause_req : std_logic_vector(8 downto 0); + signal resend_pause_r : std_logic := '0'; + signal pause_req_r : std_logic_vector(8 downto 0) := (others => '0'); + signal prog_full_r : std_logic := '0'; + +begin + + ctl_tx_resend_pause <= resend_pause_r; + ctl_tx_pause_req <= pause_req_r; + tx_pause_cnt <= std_logic_vector(tx_pause_cnt_r); + + process(clk) + begin + if(rising_edge(clk))then + if(resetn = '0')then + resend_pause_r <= '0'; + pause_req_r <= (others => '0'); + state_r <= s0; + cnt_r <= (others => '0'); + prog_full_r <= '0'; + tx_pause_cnt_r <= (others => '0'); + else + resend_pause_r <= resend_pause; + pause_req_r <= pause_req; + state_r <= state; + cnt_r <= cnt; + tx_pause_cnt_r <= tx_pause_cnt_i; + if(unsigned(data_cnt) > unsigned(prog_full_on) or prog_full_manual = '1')then + prog_full_r <= '1'; + elsif (unsigned(data_cnt) <= unsigned(prog_full_off) and prog_full_manual = '0')then + prog_full_r <= '0'; + end if; + end if; + end if; + end process; + + process(state_r, cnt_r, prog_full_r, resend_pause_r, pause_req_r, tx_pause_cnt_r) + begin + -- defaults + state <= state_r; + cnt <= cnt_r; + resend_pause <= resend_pause_r; + pause_req <= pause_req_r; + tx_pause_cnt_i <= tx_pause_cnt_r; + + case state_r is + when s0 => + if(prog_full_r = '1')then + state <= s1; + tx_pause_cnt_i <= tx_pause_cnt_r +1; + end if; + + when s1 => + pause_req <= "100000000"; + cnt <= cnt_r +1; + if(cnt_r = 15)then + state <= s2; + end if; + + when s2 => + if(prog_full_r = '0')then + state <= s3; + tx_pause_cnt_i <= tx_pause_cnt_r +1; + end if; + + when s3 => + pause_req <= (others => '0'); + cnt <= cnt_r +1; + if(cnt_r = 0)then + resend_pause <= '1'; + else + resend_pause <= '0'; + end if; + if(cnt_r = 15)then + state <= s0; + end if; + + when others => + end case; + + end process; + + +end behavioral; diff --git a/source/eth_frame_packer.vhd b/source/eth_frame_packer.vhd new file mode 100644 index 0000000..bad0e22 --- /dev/null +++ b/source/eth_frame_packer.vhd @@ -0,0 +1,258 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/30/2025 05:40:20 PM +-- Design Name: +-- Module Name: eth_frame_packer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity eth_frame_packer is + port ( + clk : in std_logic; + resetn : in std_logic; + + pause : in std_logic := '0'; + cfg_dst_mac : in std_logic_vector(47 downto 0); -- DA + cfg_src_mac : in std_logic_vector(47 downto 0); -- SA + cfg_eth_type : in std_logic_vector(15 downto 0); -- EtherType/Length + + -- AXIS payload in (512-bit, 64B beats; multiples of 64B, aligned) + s_axis_tdata : in std_logic_vector(511 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + s_axis_tlast : in std_logic; + + -- AXIS to CMAC TX client (512-bit) + m_axis_tdata : out std_logic_vector(511 downto 0); + m_axis_tkeep : out std_logic_vector(63 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic; + m_axis_tlast : out std_logic; + m_axis_tuser : out std_logic; -- error flag to CMAC + + tx_cnt : out std_logic_vector(31 downto 0); + underrun_cnt : out std_logic_vector(31 downto 0) := (others => '0') + ); +end entity; + +architecture rtl of eth_frame_packer is + + --------------------------------------------------------------------------- + -- Functions (VHDL-93 safe) + --------------------------------------------------------------------------- + function mk_header( + da : std_logic_vector(47 downto 0); + sa : std_logic_vector(47 downto 0); + ety : std_logic_vector(15 downto 0) + ) return std_logic_vector is + variable h : std_logic_vector(111 downto 0); + begin + -- DA [0..5] + h( 7 downto 0) := da(47 downto 40); + h( 15 downto 8) := da(39 downto 32); + h( 23 downto 16) := da(31 downto 24); + h( 31 downto 24) := da(23 downto 16); + h( 39 downto 32) := da(15 downto 8); + h( 47 downto 40) := da( 7 downto 0); + -- SA [6..11] + h( 55 downto 48) := sa(47 downto 40); + h( 63 downto 56) := sa(39 downto 32); + h( 71 downto 64) := sa(31 downto 24); + h( 79 downto 72) := sa(23 downto 16); + h( 87 downto 80) := sa(15 downto 8); + h( 95 downto 88) := sa( 7 downto 0); + -- Type/Len [12..13] + h(103 downto 96) := ety(15 downto 8); + h(111 downto 104) := ety( 7 downto 0); + return h; + end function; + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + type state_type is (IDLE, RUN, FLUSH); + signal state : state_type; + signal state_r : state_type := IDLE; + signal carry_r : std_logic_vector(111 downto 0) := (others => '0'); + signal carry : std_logic_vector(111 downto 0); + signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0'); + signal m_tdata : std_logic_vector(511 downto 0); + signal m_tkeep_r : std_logic_vector(63 downto 0) := (others => '1'); + signal m_tkeep : std_logic_vector(63 downto 0); + signal m_tlast_r : std_logic := '0'; + signal m_tlast : std_logic; + signal m_tvalid_r : std_logic := '0'; + signal m_tvalid : std_logic; + signal m_tuser_r : std_logic := '0'; + signal m_tuser : std_logic; + signal header : std_logic_vector(111 downto 0); + signal underrun_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + signal tx_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + +begin + + header <= mk_header(cfg_dst_mac, cfg_src_mac, cfg_eth_type); + + --------------------------------------------------------------------------- + -- Drive Outputs + --------------------------------------------------------------------------- + m_axis_tuser <= m_tuser_r; + m_axis_tdata <= m_tdata_r; + m_axis_tkeep <= m_tkeep_r; + m_axis_tlast <= m_tlast_r; + m_axis_tvalid <= m_tvalid_r; + underrun_cnt <= underrun_cnt_r; + tx_cnt <= tx_cnt_r; + + --------------------------------------------------------------------------- + -- Combinational next-state / next-data + --------------------------------------------------------------------------- + process(state_r, carry_r, s_axis_tlast, s_axis_tvalid, m_axis_tready, m_tvalid_r, + m_tdata_r, m_tkeep_r, m_tlast_r, m_tuser_r, header, s_axis_tdata, pause) + begin + -- Defaults + state <= state_r; + carry <= carry_r; + m_tdata <= m_tdata_r; + m_tkeep <= m_tkeep_r; + m_tlast <= m_tlast_r; + m_tuser <= m_tuser_r; + m_tvalid <= m_tvalid_r; + s_axis_tready <= '0'; + + case state_r is + ----------------------------------------------------------------------- + when IDLE => + + --s_axis_tready <= m_axis_tready or not(m_tvalid_r); + + --m_tvalid <= (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0')) or (not(m_axis_tready) and m_tvalid_r); + if(m_axis_tready = '1')then + m_tvalid <= '0'; + end if; + + if (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0') and pause = '0') then + + s_axis_tready <= '1'; + + -- Emit first beat = [14B header] ++ [first 50B payload] + m_tdata <= s_axis_tdata(399 downto 0) & header; + m_tkeep <= (others => '1'); + m_tvalid <= '1'; + m_tuser <= '0'; + m_tlast <= '0'; + + -- Next carry = bytes 50..63 + carry <= s_axis_tdata(511 downto 400); + + if s_axis_tlast = '1' then + state <= FLUSH; + else + state <= RUN; + end if; + + end if; + + ----------------------------------------------------------------------- + when RUN => + + s_axis_tready <= m_axis_tready; + + if(s_axis_tvalid = '0')then + m_tuser <= '1'; -- s_axis_tvalid must be '1' or else this is an error condition, tx data underrun. + end if; + + if (m_axis_tready = '1') then + + -- Steady-state emit = [prev carry 14B] ++ [new payload 0..49] + m_tdata <= s_axis_tdata(399 downto 0) & carry_r; + --m_tkeep <= (others => '1'); + --m_tvalid <= '1'; + --m_tlast <= '0'; + + -- Next carry = bytes 50..63 + carry <= s_axis_tdata(511 downto 400); + + if s_axis_tlast = '1' then + state <= FLUSH; + else + state <= RUN; + end if; + end if; + + ----------------------------------------------------------------------- + when FLUSH => + + --s_axis_tready <= '0'; + + -- if(s_axis_tvalid = '0')then + -- m_tuser <= '1'; + -- end if; + + if (m_axis_tready = '1') then + + -- Emit the final 14B tail + m_tdata <= std_logic_vector(to_unsigned(0, 400)) & carry_r; + m_tkeep <= x"0000000000003FFF"; + m_tlast <= '1'; + --m_tvalid <= '1'; + + state <= IDLE; + end if; + + --when others => + + end case; + end process; + + --------------------------------------------------------------------------- + -- Registers + --------------------------------------------------------------------------- + seq_proc : process(clk) + begin + if rising_edge(clk) then + if resetn = '0' then + state_r <= IDLE; + m_tvalid_r <= '0'; + underrun_cnt_r <= (others => '0'); + tx_cnt_r <= (others => '0'); + else + state_r <= state; + m_tvalid_r <= m_tvalid; + + if(m_tlast_r = '1' and m_tvalid_r = '1' and m_tuser_r = '1' and m_axis_tready = '1')then + underrun_cnt_r <= std_logic_vector(unsigned(underrun_cnt_r) +1); + end if; + + if(m_tlast_r = '1' and m_tvalid_r = '1' and m_axis_tready = '1')then + tx_cnt_r <= std_logic_vector(unsigned(tx_cnt_r) +1); + end if; + + end if; + carry_r <= carry; + m_tdata_r <= m_tdata; + m_tkeep_r <= m_tkeep; + m_tlast_r <= m_tlast; + m_tuser_r <= m_tuser; + end if; + end process; + +end architecture; + diff --git a/source/eth_frame_unpacker.vhd b/source/eth_frame_unpacker.vhd new file mode 100644 index 0000000..e084880 --- /dev/null +++ b/source/eth_frame_unpacker.vhd @@ -0,0 +1,145 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/30/2025 05:47:45 PM +-- Design Name: +-- Module Name: eth_frame_unpacker - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity eth_frame_unpacker is + port ( + clk : in std_logic; + resetn : in std_logic; -- active-low synchronous reset + + s_axis_tdata : in std_logic_vector(511 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tlast : in std_logic; + s_axis_tkeep : in std_logic_vector(63 downto 0); + s_axis_tuser : in std_logic; -- frame error indicator (qualified by s_axis_tvalid and s_axis_tlast) + + m_axis_tdata : out std_logic_vector(511 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tlast : out std_logic; + m_axis_tuser : out std_logic; -- frame error indicator (qualified by m_axis_tvalid and m_axis_tlast) + + rx_frame_err_cnt : out std_logic_vector(31 downto 0); + rx_frame_cnt : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture rtl of eth_frame_unpacker is + + type state_type is (IDLE, RUN); + + signal state_r : state_type := IDLE; + signal state : state_type; + signal carry : std_logic_vector(399 downto 0); + signal carry_r : std_logic_vector(399 downto 0) := (others => '0'); + signal frame_err_cnt_i : std_logic_vector(31 downto 0); + signal frame_err_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + signal frame_cnt_i : std_logic_vector(31 downto 0); + signal frame_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + signal m_tvalid : std_logic; + signal m_tvalid_r : std_logic := '0'; + signal m_tdata : std_logic_vector(511 downto 0); + signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0'); + signal m_tuser : std_logic; + signal m_tuser_r : std_logic := '0'; + signal m_tlast : std_logic; + signal m_tlast_r : std_logic := '0'; + +begin + + -- Drive outputs + m_axis_tuser <= m_tuser_r; + m_axis_tdata <= m_tdata_r; + m_axis_tlast <= m_tlast_r; + m_axis_tvalid <= m_tvalid_r; + rx_frame_err_cnt <= frame_err_cnt_r; + rx_frame_cnt <= frame_cnt_r; + + ----------------------------------------------------------------------------- + -- Combinational next-state / next-data + ----------------------------------------------------------------------------- + process(state_r, carry_r, m_tdata_r, m_tuser_r, m_tlast_r, frame_err_cnt_r, + s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser, frame_cnt_r) + begin + -- Defaults + state <= state_r; + carry <= carry_r; + frame_err_cnt_i <= frame_err_cnt_r; + frame_cnt_i <= frame_cnt_r; + m_tvalid <= '0'; + m_tdata <= m_tdata_r; + m_tuser <= m_tuser_r; + m_tlast <= m_tlast_r; + + case state_r is + ------------------------------------------------------------------------- + when IDLE => + if s_axis_tvalid = '1' then + -- cache high 50B; no output yet (need second beat to form first 64B payload) + carry(399 downto 0) <= s_axis_tdata(511 downto 112); + state <= RUN; + end if; + ------------------------------------------------------------------------- + when RUN => + if s_axis_tvalid = '1' then + carry(399 downto 0) <= s_axis_tdata(511 downto 112); + m_tdata <= s_axis_tdata(111 downto 0) & carry_r; + m_tvalid <= '1'; + m_tuser <= s_axis_tuser; + m_tlast <= s_axis_tlast; + if(s_axis_tlast = '1')then + state <= IDLE; + frame_cnt_i <= std_logic_vector(unsigned(frame_cnt_r) +1); + end if; + if(s_axis_tlast = '1' and s_axis_tuser = '1')then + frame_err_cnt_i <= std_logic_vector(unsigned(frame_err_cnt_r) +1); + end if; + end if; + ------------------------------------------------------------------------- + end case; + end process; + + ----------------------------------------------------------------------------- + -- Regs + ----------------------------------------------------------------------------- + seq_proc : process(clk) + begin + if rising_edge(clk) then + if resetn = '0' then + state_r <= IDLE; + frame_err_cnt_r <= (others => '0'); + frame_cnt_r <= (others => '0'); + m_tvalid_r <= '0'; + else + state_r <= state; + frame_err_cnt_r <= frame_err_cnt_i; + frame_cnt_r <= frame_cnt_i; + m_tvalid_r <= m_tvalid; + end if; + carry_r <= carry; + m_tdata_r <= m_tdata; + m_tuser_r <= m_tuser; + m_tlast_r <= m_tlast; + end if; + end process; +end architecture; + diff --git a/source/system_top.v b/source/system_top.v index a393f45..7cab684 100644 --- a/source/system_top.v +++ b/source/system_top.v @@ -37,8 +37,8 @@ module system_top #( - parameter FPGA_REVISION_DATE = 32'h05282026, - parameter MINOR_REV = 8'h04, + parameter FPGA_REVISION_DATE = 32'h07162026, + parameter MINOR_REV = 8'h01, parameter TX_JESD_L = 8, parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 8, @@ -69,6 +69,35 @@ module system_top #( output QSFP1_TX3_P, output QSFP1_TX4_N, output QSFP1_TX4_P, +// + input QSFP2_INTL_LS, + input QSFP2_MODPRSL_LS, + output QSFP2_RESETL_LS, + input QSFP2_SI570_CLOCK_N,//CLK3_N + input QSFP2_SI570_CLOCK_P, +// + input QSFP3_INTL_LS, + input QSFP3_MODPRSL_LS, + output QSFP3_RESETL_LS, + input QSFP3_RX1_N, + input QSFP3_RX1_P, + input QSFP3_RX2_N, + input QSFP3_RX2_P, + input QSFP3_RX3_N, + input QSFP3_RX3_P, + input QSFP3_RX4_N, + input QSFP3_RX4_P, + input QSFP3_SI570_CLOCK_N,//CLK1_N + input QSFP3_SI570_CLOCK_P, + output QSFP3_TX1_N, + output QSFP3_TX1_P, + output QSFP3_TX2_N, + output QSFP3_TX2_P, + output QSFP3_TX3_N, + output QSFP3_TX3_P, + output QSFP3_TX4_N, + output QSFP3_TX4_P, +// input QSFP4_INTL_LS, input QSFP4_MODPRSL_LS, output QSFP4_RESETL_LS, @@ -90,14 +119,7 @@ module system_top #( output QSFP4_TX3_P, output QSFP4_TX4_N, output QSFP4_TX4_P, - - input QSFP2_SI570_CLOCK_N,//CLK3_N - input QSFP2_SI570_CLOCK_P, - - input QSFP3_SI570_CLOCK_N,//CLK1_N - input QSFP3_SI570_CLOCK_P, - - +// inout pll_scl, inout pll_sda, @@ -220,13 +242,13 @@ module system_top #( wire qsfp1_capture_tvalid_240b; wire [31:0] qsfp1_capture_tvalid_240b_cnt; - wire [31:0] qsfp1_tx_fifo_128_aempty_cnt; + wire [31:0] qsfp1_fifo_128_aempty_cnt; - wire [127:0] tx_tdata_128b; - wire tx_tvalid_128b; - wire tx_tready_128b; + wire [127:0] qsfp1_tdata_128b; + wire qsfp1_tvalid_128b; + wire qsfp1_tready_128b; - wire [31:0] qsfp1_tx_fifo_tvalid_128b_cnt; + wire [31:0] qsfp1_fifo_tvalid_128b_cnt; wire qsfp1_capture_rx_data_ready; wire [31:0] qsfp1_capture_rx_data_ready_cnt; @@ -253,38 +275,7 @@ module system_top #( wire [31:0] slv_reg9; wire [31:0] slv_reg10; - wire [31:0] slv_reg21; - wire [31:0] slv_reg22; - wire [31:0] slv_reg23; - wire [31:0] slv_reg24; - wire [31:0] slv_reg25; - wire [31:0] slv_reg26; - wire [31:0] slv_reg27; - wire [31:0] slv_reg28; - wire [31:0] slv_reg29; - wire [31:0] slv_reg30; - - wire [31:0] slv_reg31; - wire [31:0] slv_reg32; - wire [31:0] slv_reg33; - wire [31:0] slv_reg34; - wire [31:0] slv_reg35; - wire [31:0] slv_reg36; - wire [31:0] slv_reg37; - wire [31:0] slv_reg38; - wire [31:0] slv_reg39; - wire [31:0] slv_reg40; - - wire [31:0] slv_reg41; - wire [31:0] slv_reg42; - wire [31:0] slv_reg43; - wire [31:0] slv_reg44; - wire [31:0] slv_reg45; - wire [31:0] slv_reg46; - wire [31:0] slv_reg47; - wire [31:0] slv_reg48; - - wire [1:0] dac_src_data_sel; + wire [2:0] dac_src_data_sel; wire chan1to4_mode_sel; wire qsfp4_playback_path_data_enable_n; @@ -292,9 +283,6 @@ module system_top #( wire qsfp2_clk; wire qsfp2_clk_bufg; - wire qsfp3_clk; - wire qsfp3_clk_bufg; - wire clk_100; wire clk_100_aresetn; wire [31:0] M11_AXI_0_araddr; @@ -337,6 +325,26 @@ module system_top #( wire [3:0] M12_AXI_0_wstrb; wire M12_AXI_0_wvalid; + wire [31:0] M13_AXI_0_araddr; + wire [2:0] M13_AXI_0_arprot; + wire M13_AXI_0_arready; + wire M13_AXI_0_arvalid; + wire [31:0] M13_AXI_0_awaddr; + wire [2:0] M13_AXI_0_awprot; + wire M13_AXI_0_awready; + wire M13_AXI_0_awvalid; + wire M13_AXI_0_bready; + wire [1:0] M13_AXI_0_bresp; + wire M13_AXI_0_bvalid; + wire [31:0] M13_AXI_0_rdata; + wire M13_AXI_0_rready; + wire [1:0] M13_AXI_0_rresp; + wire M13_AXI_0_rvalid; + wire [31:0] M13_AXI_0_wdata; + wire M13_AXI_0_wready; + wire [3:0] M13_AXI_0_wstrb; + wire M13_AXI_0_wvalid; + wire sda_i; wire sda_o; wire sda_t; @@ -357,6 +365,10 @@ module system_top #( wire m1_dds_pulse_tvalid_128b; wire m1_dds_pulse_tready_128b; + wire [127:0] m1_dds_pulse_fifo_tdata_128b; + wire m1_dds_pulse_fifo_tvalid_128b; + wire m1_dds_pulse_fifo_tready_128b; + wire [127:0] fiber_tx_tdata_128b; wire fiber_tx_tvalid_128b; wire fiber_tx_tready_128b; @@ -369,6 +381,47 @@ module system_top #( wire qsfp1_capture_en_n; wire qsfp1_capture_rst; + + wire [3:0] cmac_gt_0_grx_n; + wire [3:0] cmac_gt_0_grx_p; + wire [3:0] cmac_gt_0_gtx_n; + wire [3:0] cmac_gt_0_gtx_p; + wire cmac_refclk_0_clk_n; + wire cmac_refclk_0_clk_p; + + wire cmac_tx_intfc_en; + wire cmac_rx_intfc_en; + +//// + wire [511:0] cmac_0_tx_tdata_512b; + wire cmac_0_tx_tvalid_512b; + wire cmac_0_tx_tvalid_512b_en; + wire cmac_0_tx_tready_512b; + wire cmac_0_tx_tready_512b_en; + reg [31:0] cmac_0_tx_tvalid_512b_cnt_r = 32'h0; + + wire [511:0] cmac_0_rx_tdata_512b; + wire cmac_0_rx_tvalid_512b; + wire cmac_0_rx_tvalid_512b_en; + wire cmac_0_rx_tready_512b; + wire cmac_0_rx_tready_512b_en; + reg [31:0] cmac_0_rx_tvalid_512b_cnt_r = 32'h0; + + wire [127:0] cmac_0_rx_tdata_128b; + wire cmac_0_rx_tvalid_128b; + wire cmac_0_rx_tready_128b; + + wire [127:0] dds2cmac_fifo_tdata_128b; + wire dds2cmac_fifo_tvalid_128b; + wire dds2cmac_fifo_tready_128b; + + wire dds_out_dest_sel; + wire cmac_tx_src_data_sel; + + wire [511:0] adc_tdata_512b; + wire adc_tvalid_512b; + wire adc_tready_512b; + //////////////////////////////////////////////////////////////// // instantiations @@ -472,27 +525,6 @@ module system_top #( .DIV (3'b000), .O (qsfp2_clk_bufg) ); - -////////// - IBUFDS_GTE4 i_ibufds_qsfp3 ( - .I (QSFP3_SI570_CLOCK_P), - .IB (QSFP3_SI570_CLOCK_N), - .CEB (1'b0), - .O (), - .ODIV2 (qsfp3_clk) - ); - - BUFG_GT i_bufgt_qsfp3 ( - .I (qsfp3_clk), - .CE (1'b1), - .CEMASK (1'b0), - .CLR (1'b0), - .CLRMASK (1'b0), - .DIV (3'b000), - .O (qsfp3_clk_bufg) - ); - - // assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal; @@ -736,6 +768,26 @@ module system_top #( .M12_AXI_0_wstrb (M12_AXI_0_wstrb), .M12_AXI_0_wvalid (M12_AXI_0_wvalid), + .M13_AXI_0_araddr (M13_AXI_0_araddr), + .M13_AXI_0_arprot (M13_AXI_0_arprot), + .M13_AXI_0_arready (M13_AXI_0_arready), + .M13_AXI_0_arvalid (M13_AXI_0_arvalid), + .M13_AXI_0_awaddr (M13_AXI_0_awaddr), + .M13_AXI_0_awprot (M13_AXI_0_awprot), + .M13_AXI_0_awready (M13_AXI_0_awready), + .M13_AXI_0_awvalid (M13_AXI_0_awvalid), + .M13_AXI_0_bready (M13_AXI_0_bready), + .M13_AXI_0_bresp (M13_AXI_0_bresp), + .M13_AXI_0_bvalid (M13_AXI_0_bvalid), + .M13_AXI_0_rdata (M13_AXI_0_rdata), + .M13_AXI_0_rready (M13_AXI_0_rready), + .M13_AXI_0_rresp (M13_AXI_0_rresp), + .M13_AXI_0_rvalid (M13_AXI_0_rvalid), + .M13_AXI_0_wdata (M13_AXI_0_wdata), + .M13_AXI_0_wready (M13_AXI_0_wready), + .M13_AXI_0_wstrb (M13_AXI_0_wstrb), + .M13_AXI_0_wvalid (M13_AXI_0_wvalid), + .Res_0 (), //mxfe_rx_data_offload_s_axis_tready from Rx DMA engine .pl_clk3_0 (pl_clk3_0), @@ -781,7 +833,6 @@ module system_top #( // .sysref_in (sysref), .ref_clk_div2_in (ref_clk_div2_bufg), .qsfp2_clk_in (qsfp2_clk_bufg), - .qsfp3_clk_in (qsfp3_clk_bufg), .pl_clk3_0 (pl_clk3_0), .QSFP1_INTL_LS (QSFP1_INTL_LS), @@ -805,6 +856,15 @@ module system_top #( .QSFP1_TX3_P (QSFP1_TX3_P), .QSFP1_TX4_N (QSFP1_TX4_N), .QSFP1_TX4_P (QSFP1_TX4_P), +/////////// + .QSFP2_RESETL_LS (QSFP2_RESETL_LS), + .QSFP2_MODPRSL_LS (QSFP2_MODPRSL_LS), + .QSFP2_INTL_LS (QSFP2_INTL_LS), +/////////// + .QSFP3_RESETL_LS (QSFP3_RESETL_LS), + .QSFP3_MODPRSL_LS (QSFP3_MODPRSL_LS), + .QSFP3_INTL_LS (QSFP3_INTL_LS), +/////////// .QSFP4_INTL_LS (QSFP4_INTL_LS), .QSFP4_MODPRSL_LS (QSFP4_MODPRSL_LS), .QSFP4_RESETL_LS (QSFP4_RESETL_LS), @@ -842,9 +902,9 @@ module system_top #( .qsfp1_capture_tvalid_240b_cnt_in (qsfp1_capture_tvalid_240b_cnt), .qsfp1_capture_overflow_240b_cnt_in (qsfp1_capture_overflow_240b_cnt), .qsfp1_capture_tvalid_512b_cnt_in (qsfp1_capture_tvalid_512b_cnt), - .qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_tx_fifo_128_aempty_cnt), + .qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_fifo_128_aempty_cnt), .qsfp1_capture_rx_data_ready_cnt_in (qsfp1_capture_rx_data_ready_cnt), - .qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_tx_fifo_tvalid_128b_cnt), + .qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_fifo_tvalid_128b_cnt), .mem_xfer_tx_upload_tvalid_128b_cnt_in (mem_xfer_tx_upload_tvalid_128b_cnt_r), .dac_tx_tvalid_128b_cnt_in (dac_tx_tvalid_128b_cnt_r), @@ -853,44 +913,17 @@ module system_top #( .qsfp4_playback_tvalid_128b_cnt_in (qsfp4_playback_tvalid_128b_cnt), .qsfp4_playback_tvalid_240b_cnt_in (qsfp4_playback_tvalid_240b_cnt), - .fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r), + .fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r), + .cmac_0_tx_tvalid_512b_cnt_in (cmac_0_tx_tvalid_512b_cnt_r), + .cmac_0_rx_tvalid_512b_cnt_in (cmac_0_rx_tvalid_512b_cnt_r), + + .cnt_reset_out (cnt_reset), .slv_reg9_out (slv_reg9), .slv_reg10_out (slv_reg10), - .slv_reg21_out (slv_reg21), - .slv_reg22_out (slv_reg22), - .slv_reg23_out (slv_reg23), - .slv_reg24_out (slv_reg24), - .slv_reg25_out (slv_reg25), - .slv_reg26_out (slv_reg26), - .slv_reg27_out (slv_reg27), - .slv_reg28_out (slv_reg28), - .slv_reg29_out (slv_reg29), - .slv_reg30_out (slv_reg30), - - .slv_reg31_out (slv_reg31), - .slv_reg32_out (slv_reg32), - .slv_reg33_out (slv_reg33), - .slv_reg34_out (slv_reg34), - .slv_reg35_out (slv_reg35), - .slv_reg36_out (slv_reg36), - .slv_reg37_out (slv_reg37), - .slv_reg38_out (slv_reg38), - .slv_reg39_out (slv_reg39), - .slv_reg40_out (slv_reg40), - - .slv_reg41_out (slv_reg41), - .slv_reg42_out (slv_reg42), - .slv_reg43_out (slv_reg43), - .slv_reg44_out (slv_reg44), - .slv_reg45_out (slv_reg45), - .slv_reg46_out (slv_reg46), - .slv_reg47_out (slv_reg47), - .slv_reg48_out (slv_reg48), - .sys_cpu_clk_in (clk_100), .s00_axi_aresetn (clk_100_aresetn), .s00_axi_awaddr (M11_AXI_0_awaddr[7:0]), @@ -918,12 +951,19 @@ module system_top #( //assign = slv_reg10[3:1]; assign qsfp1_capture_rst = slv_reg10[4]; //assign = slv_reg10[7:5]; - assign dac_src_data_sel = slv_reg10[9:8]; -//assign = slv_reg10[11:10]; + assign dac_src_data_sel = slv_reg10[10:8]; +//assign = slv_reg10[11]; assign chan1to4_mode_sel = slv_reg10[12]; //assign = slv_reg10[14:13]; assign qsfp1_capture_en_n = slv_reg10[15]; -//assign = slv_reg10[30:16]; +//assign = slv_reg10[18:16]; + assign cmac_tx_src_data_sel = slv_reg10[19]; +//assign = slv_reg10[23:20]; + assign dds_out_dest_sel = slv_reg10[24]; +//assign = slv_reg10[27:25]; + assign cmac_tx_intfc_en = slv_reg10[28]; + assign cmac_rx_intfc_en = slv_reg10[29]; +//assign = slv_reg10[30]; assign qsfp4_playback_path_data_enable_n = slv_reg10[31]; /////////////////////////////// @@ -942,11 +982,11 @@ module system_top #( .tx_device_clk_in (tx_device_clk_1), .tx_device_clk_aresetn_in (tx_device_clk_aresetn), - .tx_fifo_tdata_128b_out (tx_tdata_128b), // out - .tx_fifo_tvalid_128b_out (tx_tvalid_128b), // out - .tx_fifo_tready_128b_in (tx_tready_128b), // in - .qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_tx_fifo_tvalid_128b_cnt), - .qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_tx_fifo_128_aempty_cnt), + .tx_fifo_tdata_128b_out (qsfp1_tdata_128b), // out + .tx_fifo_tvalid_128b_out (qsfp1_tvalid_128b), // out + .tx_fifo_tready_128b_in (qsfp1_tready_128b), // in + .qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_fifo_tvalid_128b_cnt), + .qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_fifo_128_aempty_cnt), .qsfp1_capture_en_n_in (qsfp1_capture_en_n), .qsfp1_capture_rst_in (qsfp1_capture_rst), @@ -957,17 +997,15 @@ module system_top #( //// to DAC - data source from DMA Tx axis data, QSFP1 and ADC_INTFC ///////////////////////////////////////////// axis_mux_128b i_dac_axis_mux_128b ( - .aclk (tx_device_clk_1), // input - .aresetn (tx_device_clk_aresetn), // input .aselect (dac_src_data_sel), // input .s0_axis_tdata (mem_xfer_tx_upload_tdata_128b), // input .s0_axis_tvalid (mem_xfer_tx_upload_tvalid_128b), // input .s0_axis_tready (mem_xfer_tx_upload_tready_128b), // output - .s1_axis_tdata (tx_tdata_128b), // input - .s1_axis_tvalid (tx_tvalid_128b), // input - .s1_axis_tready (tx_tready_128b), // output + .s1_axis_tdata (qsfp1_tdata_128b), // input + .s1_axis_tvalid (qsfp1_tvalid_128b), // input + .s1_axis_tready (qsfp1_tready_128b), // output .s2_axis_tdata (adc_loopback_tdata_128b_mux), // input .s2_axis_tvalid (adc_loopback_tvalid_128b), // input @@ -977,6 +1015,10 @@ module system_top #( .s3_axis_tvalid (m0_dds_pulse_tvalid_128b), // input .s3_axis_tready (m0_dds_pulse_tready_128b), // output + .s4_axis_tdata (cmac_0_rx_tdata_128b), // input + .s4_axis_tvalid (cmac_0_rx_tvalid_128b), // input + .s4_axis_tready (cmac_0_rx_tready_128b), // output + .m_axis_tdata (dac_tx_tdata_128b), // output .m_axis_tvalid (dac_tx_tvalid_128b), // output .m_axis_tready (dac_tx_tready_128b) // input @@ -1004,14 +1046,28 @@ module system_top #( .s_axis_tready (m1_dds_pulse_tready_128b), // out .m_axis_aclk (rx_device_clk_1), // in - .m_axis_tdata (dds2fiber_fifo_tdata_128b), // out - .m_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out - .m_axis_tready (dds2fiber_fifo_tready_128b) // in + .m_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // out + .m_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // out + .m_axis_tready (m1_dds_pulse_fifo_tready_128b) // in + ); + + axis_demux_128b i_axis_demux_128b ( + .aselect (dds_out_dest_sel), // in + + .s_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // in + .s_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // in + .s_axis_tready (m1_dds_pulse_fifo_tready_128b), // out + + .m0_axis_tdata (dds2fiber_fifo_tdata_128b), // out + .m0_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out + .m0_axis_tready (dds2fiber_fifo_tready_128b), // in + + .m1_axis_tdata (dds2cmac_fifo_tdata_128b), // out + .m1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // out + .m1_axis_tready (dds2cmac_fifo_tready_128b) // in ); axis_mux_s2_128b i_axis_mux_s2_128b ( - .aclk (rx_device_clk_1), // input - .aresetn (rx_device_clk_aresetn), // input .aselect (fiber_tx_src_data_sel), // input .s0_axis_tdata (adc_rx_tdata_128b), // input @@ -1151,6 +1207,145 @@ module system_top #( .s00_axi_rready (M12_AXI_0_rready) ); +/////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + + assign cmac_refclk_0_clk_p = QSFP3_SI570_CLOCK_P; + assign cmac_refclk_0_clk_n = QSFP3_SI570_CLOCK_N; + + assign cmac_gt_0_grx_p[0] = QSFP3_RX1_P; + assign cmac_gt_0_grx_n[0] = QSFP3_RX1_N; + assign cmac_gt_0_grx_p[1] = QSFP3_RX2_P; + assign cmac_gt_0_grx_n[1] = QSFP3_RX2_N; + assign cmac_gt_0_grx_p[2] = QSFP3_RX3_P; + assign cmac_gt_0_grx_n[2] = QSFP3_RX3_N; + assign cmac_gt_0_grx_p[3] = QSFP3_RX4_P; + assign cmac_gt_0_grx_n[3] = QSFP3_RX4_N; + + assign QSFP3_TX1_P = cmac_gt_0_gtx_p[0]; + assign QSFP3_TX1_N = cmac_gt_0_gtx_n[0]; + assign QSFP3_TX2_P = cmac_gt_0_gtx_p[1]; + assign QSFP3_TX2_N = cmac_gt_0_gtx_n[1]; + assign QSFP3_TX3_P = cmac_gt_0_gtx_p[2]; + assign QSFP3_TX3_N = cmac_gt_0_gtx_n[2]; + assign QSFP3_TX4_P = cmac_gt_0_gtx_p[3]; + assign QSFP3_TX4_N = cmac_gt_0_gtx_n[3]; + + raw_eth_wrapper i_raw_eth_cmac_0 ( + .clk_100_0 (clk_100), + .clk_100_reset_0 (clk_100_areset), + + .cmac_gt_0_grx_n (cmac_gt_0_grx_n), //in + .cmac_gt_0_grx_p (cmac_gt_0_grx_p), //in + .cmac_gt_0_gtx_n (cmac_gt_0_gtx_n), //out + .cmac_gt_0_gtx_p (cmac_gt_0_gtx_p), //out + .cmac_refclk_0_clk_n (cmac_refclk_0_clk_n), + .cmac_refclk_0_clk_p (cmac_refclk_0_clk_p), + + .m_axis_aclk (tx_device_clk_1), + .m_axis_aresetn (tx_device_clk_aresetn), + .m_axis_tdata (cmac_0_rx_tdata_512b), // out + .m_axis_tvalid (cmac_0_rx_tvalid_512b), // out + .m_axis_tready (cmac_0_rx_tready_512b_en), // in + + .axil_clk_0 (clk_100), + .axil_resetn_0 (clk_100_aresetn), + + .s_axil_0_awaddr (M13_AXI_0_awaddr), + .s_axil_0_awprot (M13_AXI_0_awprot), + .s_axil_0_awvalid (M13_AXI_0_awvalid), + .s_axil_0_awready (M13_AXI_0_awready), + + .s_axil_0_wdata (M13_AXI_0_wdata), + .s_axil_0_wstrb (M13_AXI_0_wstrb), + .s_axil_0_wvalid (M13_AXI_0_wvalid), + .s_axil_0_wready (M13_AXI_0_wready), + + .s_axil_0_bresp (M13_AXI_0_bresp), + .s_axil_0_bvalid (M13_AXI_0_bvalid), + .s_axil_0_bready (M13_AXI_0_bready), + + .s_axil_0_araddr (M13_AXI_0_araddr), + .s_axil_0_arprot (M13_AXI_0_arprot), + .s_axil_0_arvalid (M13_AXI_0_arvalid), + .s_axil_0_arready (M13_AXI_0_arready), + + .s_axil_0_rdata (M13_AXI_0_rdata), + .s_axil_0_rresp (M13_AXI_0_rresp), + .s_axil_0_rvalid (M13_AXI_0_rvalid), + .s_axil_0_rready (M13_AXI_0_rready), + + .s_axis_clk (rx_device_clk_1), + .s_axis_aresetn (rx_device_clk_aresetn), + .s_axis_tdata (cmac_0_tx_tdata_512b), // in + .s_axis_tvalid (cmac_0_tx_tvalid_512b_en), // in + .s_axis_tready (cmac_0_tx_tready_512b) // out + ); + + axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b ( + .aclk (rx_device_clk_1), // in + .aresetn (rx_device_clk_aresetn), // in + + .s_axis_tdata (adc_rx_tdata_128b), // in + .s_axis_tvalid (adc_rx_tvalid_128b), // in + .s_axis_tready ( ), // out + + .m_axis_tdata (adc_tdata_512b), // out + .m_axis_tvalid (adc_tvalid_512b), // out + .m_axis_tready (adc_tready_512b) // in + ); + + axis_mux_512b i_axis_mux_512b ( + .aselect (cmac_tx_src_data_sel), // input + + .s0_axis_tdata (adc_tdata_512b), // input + .s0_axis_tvalid (adc_tvalid_512b), // input + .s0_axis_tready (adc_tready_512b), // output + + .s1_axis_tdata (dds2cmac_fifo_tdata_128b), // input + .s1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // input + .s1_axis_tready (dds2cmac_fifo_tready_128b), // output + + .m_axis_tdata (cmac_0_tx_tdata_512b), // output + .m_axis_tvalid (cmac_0_tx_tvalid_512b), // output + .m_axis_tready (cmac_0_tx_tready_512b_en) // input + ); + + assign cmac_0_tx_tvalid_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tvalid_512b : 1'b0; + assign cmac_0_tx_tready_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tready_512b : 1'b0; + + always @(posedge rx_device_clk_1) + begin + if (rx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1) + cmac_0_tx_tvalid_512b_cnt_r <= 32'h0; + else if (cmac_0_tx_tvalid_512b_en == 1'b1 && cmac_0_tx_tready_512b_en == 1'b1) + cmac_0_tx_tvalid_512b_cnt_r <= cmac_0_tx_tvalid_512b_cnt_r + 1; + end +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + assign cmac_0_rx_tvalid_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tvalid_512b : 1'b0; + assign cmac_0_rx_tready_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tready_512b : 1'b0; + + axis_dwidth_converter_512b_to_128b i_axis_dwidth_converter_512b_to_128b_cmac_0 ( + .aclk (tx_device_clk_1), // in + .aresetn (tx_device_clk_aresetn), // in + + .s_axis_tdata (cmac_0_rx_tdata_512b), // in + .s_axis_tvalid (cmac_0_rx_tvalid_512b_en), // in + .s_axis_tready (cmac_0_rx_tready_512b), // out + + .m_axis_tdata (cmac_0_rx_tdata_128b), // out + .m_axis_tvalid (cmac_0_rx_tvalid_128b), // out + .m_axis_tready (cmac_0_rx_tready_128b) // in + ); + + always @(posedge tx_device_clk_1) + begin + if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1) + cmac_0_rx_tvalid_512b_cnt_r <= 32'h0; + else if (cmac_0_rx_tvalid_512b_en == 1'b1 && cmac_0_rx_tready_512b_en == 1'b1) + cmac_0_rx_tvalid_512b_cnt_r <= cmac_0_rx_tvalid_512b_cnt_r + 1; + end ////////////////////////// si5332_wrapper i_si5332_wrapper ( @@ -1163,10 +1358,7 @@ module system_top #( .scl_in (scl_i), .scl_out (scl_o), - .scl_t_out (scl_t), - - .qsfp2_clk_in (qsfp2_clk_bufg), - .qsfp3_clk_in (qsfp3_clk_bufg) + .scl_t_out (scl_t) ); IOBUF i_scl_iobuf (