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nsantana
2026-07-18 14:19:50 -04:00
parent 9fc4cf25a4
commit 494ada36f0
16 changed files with 0 additions and 10021 deletions
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc
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###############################################################################################################
# Core-Level Timing Constraints for axi_register_slice Component "axis_register_slice_32"
###############################################################################################################
#
# This component is not configured in a multi-SLR crossing or auto-pipelining mode.
# No timing core-level constraints are needed.
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc
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# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 100 -name aclk [get_ports aclk]
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
// Date : Thu Apr 23 10:08:03 2026
// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
// Command : write_verilog -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
// axis_register_slice_32_ axis_register_slice_32_stub.v
// Design : axis_register_slice_32
// Purpose : Stub declaration of top-level module interface
// Device : xczu19eg-ffvc1760-2-i
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
module axis_register_slice_32(aclk, aresetn, s_axis_tvalid, s_axis_tready,
s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata)
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [31:0]s_axis_tdata;
output m_axis_tvalid;
input m_axis_tready;
output [31:0]m_axis_tdata;
endmodule
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
-- Date : Thu Apr 23 10:08:04 2026
-- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
-- axis_register_slice_32_ axis_register_slice_32_stub.vhdl
-- Design : axis_register_slice_32
-- Purpose : Stub declaration of top-level module interface
-- Device : xczu19eg-ffvc1760-2-i
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity axis_register_slice_32 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end axis_register_slice_32;
architecture stub of axis_register_slice_32 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2";
begin
end;
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh
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// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Global Parameters:
//
// Functions:
// f_clogb2
// f_gcd
// f_lcm
// f_get_tdata_indx
// f_get_tstrb_indx
// f_get_tkeep_indx
// f_get_tlast_indx
// f_get_tid_indx
// f_get_tdest_indx
// f_get_tuser_indx
// f_payload_width
// Tasks:
// t_display_tdata_error
//--------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// BEGIN Global Parameters
///////////////////////////////////////////////////////////////////////////////
// Define Signal Set indices
localparam G_INDX_SS_TREADY = 0;
localparam G_INDX_SS_TDATA = 1;
localparam G_INDX_SS_TSTRB = 2;
localparam G_INDX_SS_TKEEP = 3;
localparam G_INDX_SS_TLAST = 4;
localparam G_INDX_SS_TID = 5;
localparam G_INDX_SS_TDEST = 6;
localparam G_INDX_SS_TUSER = 7;
localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
// Task DRC error levels
localparam G_TASK_SEVERITY_ERR = 2;
localparam G_TASK_SEVERITY_WARNING = 1;
localparam G_TASK_SEVERITY_INFO = 0;
///////////////////////////////////////////////////////////////////////////////
// BEGIN Functions
///////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
// Calculates the Greatest Common Divisor between two integers using the
// euclidean algorithm.
function automatic integer f_gcd (
input integer a,
input integer b
);
begin : main
if (a == 0) begin
f_gcd = b;
end else if (b == 0) begin
f_gcd = a;
end else if (a > b) begin
f_gcd = f_gcd(a % b, b);
end else begin
f_gcd = f_gcd(a, b % a);
end
end
endfunction
// Calculates the Lowest Common Denominator between two integers
function integer f_lcm (
input integer a,
input integer b
);
begin : main
f_lcm = ( a / f_gcd(a, b)) * b;
end
endfunction
// Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tdata_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
f_get_tdata_indx = 0;
end
endfunction
// Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tstrb_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
// If TDATA exists, then add its width to its base to get the tstrb index
f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
end
endfunction
// Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tkeep_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
end
endfunction
// Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tlast_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
end
endfunction
// Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tid_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
end
endfunction
// Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tdest_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
end
endfunction
// Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tuser_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
end
endfunction
// Payload is the sum of all the AXIS signals present except for
// TREADY/TVALID
function integer f_payload_width (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
// Ensure that the return value is never less than 1
f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
end
endfunction
task t_check_tdata_width(
input integer data_width,
input [8*80-1:0] var_name,
input [8*80-1:0] inst_name,
input integer severity_lvl,
output integer ret_val
);
// Severity levels:
// 0 = INFO
// 1 = WARNING
// 2 = ERROR
begin : t_check_tdata_width
if (data_width%8 != 0) begin
// 000 1 2 3 4 5 6 7 8
// 012 0 0 0 0 0 0 0 0
if (severity_lvl >= 2) begin
$display("ERROR: %m::%s", inst_name);
end else if (severity_lvl == 1) begin
$display("WARNING: %m::%s", inst_name);
end else begin
$display("INFO: %m::%s", inst_name);
end
$display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
$display(" AXI4-Stream data width is only defined for byte multiples. See the ");
$display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
$display(" information.");
ret_val = 1;
end else begin
ret_val = 0;
end
end
endtask
task t_check_tuser_width(
input integer tuser_width,
input [8*80-1:0] tuser_name,
input integer tdata_width,
input [8*80-1:0] tdata_name,
input [8*80-1:0] inst_name,
input integer severity_lvl,
output integer ret_val
);
// Severity levels:
// 0 = INFO
// 1 = WARNING
// 2 = ERROR
begin : t_check_tuser_width
integer tdata_bytes;
tdata_bytes = tdata_width/8;
if ((tuser_width%tdata_bytes) != 0) begin
// 000 1 2 3 4 5 6 7 8
// 012 0 0 0 0 0 0 0 0
if (severity_lvl >= 2) begin
$display("ERROR: %m::%s", inst_name);
end else if (severity_lvl == 1) begin
$display("WARNING: %m::%s", inst_name);
end else begin
$display("INFO: %m::%s", inst_name);
end
$display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
$display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
$display(" TUSER width in this module is only defined when the TUSER is the");
$display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
$display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
ret_val = 1;
end else begin
ret_val = 0;
end
end
endtask
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_register_slice:1.1
// IP Revision: 29
(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *)
(* CORE_GENERATION_INFO = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_register_slice,x_ipVersion=1.1,x_ipCoreRevision=29,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011,C_REG_CONFIG=8,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER=0,C_PIPELINES_SLAVE=0,C_PIPELINES_MIDDLE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module axis_register_slice_32 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
axis_register_slice_v1_1_29_axis_register_slice #(
.C_FAMILY("zynquplus"),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011),
.C_REG_CONFIG(8),
.C_NUM_SLR_CROSSINGS(0),
.C_PIPELINES_MASTER(0),
.C_PIPELINES_SLAVE(0),
.C_PIPELINES_MIDDLE(0)
) inst (
.aclk(aclk),
.aclk2x(1'H0),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(4'HF),
.s_axis_tkeep(4'HF),
.s_axis_tlast(1'H1),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule
sim/dds_wrapper_tb.vhd
-321
View File
@@ -1,321 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:22 03/24/2017
-- Design Name:
-- Module Name:
-- Project Name: xem7350
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dac_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
Library xpm;
use xpm.vcomponents.all;
--library UNISIM;
--use UNISIM.VComponents.all;
entity dds_wrapper_tb is
end dds_wrapper_tb;
architecture behavior of dds_wrapper_tb is
-- Clock period definitions
constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
constant CLK_100_PERIOD : time := 10 ns; -- 100 MHz
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
signal clk_100 : std_logic := '0';
signal clk_100_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_250 : std_logic := '0';
signal clk_250_aresetn : std_logic_vector(0 to 63) := x"0000_FFFF_0000_0000";--(others => '0');
signal m_axis_tready_r : std_logic := '0';
signal m_axis_tdata : std_logic_vector(127 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal util_mxfe_upack_s_axis_tdata_pipe : std_logic_vector(127 downto 0);
signal util_mxfe_upack_s_axis_tvalid_pipe : std_logic;
signal m_axis_tdata_1 : std_logic_vector(127 downto 0);
signal m_axis_tvalid_1 : std_logic;
signal m_axis_tready_1 : std_logic;
signal cmd_send_i : std_logic_vector(0 to 3) := (others => '0');
signal dac_holdoff_r : std_logic := '1';
signal chan1_i : std_logic_vector(15 downto 0);
signal chan1_q : std_logic_vector(15 downto 0);
signal chan2_i : std_logic_vector(15 downto 0);
signal chan2_q : std_logic_vector(15 downto 0);
signal chan3_i : std_logic_vector(15 downto 0);
signal chan3_q : std_logic_vector(15 downto 0);
signal chan4_i : std_logic_vector(15 downto 0);
signal chan4_q : std_logic_vector(15 downto 0);
signal cmd_send_0_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_1_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_2_r : std_logic_vector(0 to 2) := (others => '0');
signal cmd_send_3_r : std_logic_vector(0 to 2) := (others => '0');
signal cnt_reset : std_logic := '0';
begin
clk_100 <= not clk_100 after CLK_100_PERIOD/2;
clk_250 <= not clk_250 after CLK_250_PERIOD/2;
--
process(clk_100)
begin
if (rising_edge(clk_100)) then
clk_100_aresetn <= clk_100_aresetn(1 to 15) & '1';
end if;
end process;
--
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_aresetn <= clk_250_aresetn(1 to 63) & '1';
end if;
end process;
process (clk_100)
begin
if rising_edge(clk_100) then
if (cmd_send_i(0) = '1') then
cmd_send_0_r <= "111";
else
cmd_send_0_r <= cmd_send_0_r(1 to 2) & '0';
end if;
if (cmd_send_i(1) = '1') then
cmd_send_1_r <= "111";
else
cmd_send_1_r <= cmd_send_1_r(1 to 2) & '0';
end if;
if (cmd_send_i(2) = '1') then
cmd_send_2_r <= "111";
else
cmd_send_2_r <= cmd_send_2_r(1 to 2) & '0';
end if;
if (cmd_send_i(3) = '1') then
cmd_send_3_r <= "111";
else
cmd_send_3_r <= cmd_send_3_r(1 to 2) & '0';
end if;
end if;
end process;
i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4
port map (
s_axi_aclk_in => clk_100,
s_axi_aresetn_in => clk_100_aresetn(0),
cmd_idx_in => "000",
dac_holdoff_in => dac_holdoff_r,
cmd_send_0_in => cmd_send_0_r(0),
scale_0_in => x"8000",
dds_phase_inc_dwell_time_0_in => x"00000000",
dds_phase_inc_step_size_0_in => x"0000D6BF",
idle_samples_0_in => x"00000000",
dds_samples_0_in => x"000004E2",
phase_inc_0_in => x"010624DD",
phase_off_0_in => x"00000000",
swap_sf_0_in => x"00008000",
cmd_send_1_in => cmd_send_1_r(0),
scale_1_in => x"8000",
dds_phase_inc_dwell_time_1_in => x"00000000",
dds_phase_inc_step_size_1_in => x"0000D6BF",
idle_samples_1_in => x"00000000",
dds_samples_1_in => x"000004E2", --x"000004E2",
phase_inc_1_in => x"010624DD",
phase_off_1_in => x"00000000",
swap_sf_1_in => x"00008000",
cmd_send_2_in => cmd_send_2_r(0),
scale_2_in => x"8000",
dds_phase_inc_dwell_time_2_in => x"00000000",
dds_phase_inc_step_size_2_in => x"0000D6BF",
idle_samples_2_in => x"00000000",
dds_samples_2_in => x"000004E2",
phase_inc_2_in => x"010624DD",
phase_off_2_in => x"00000000",
swap_sf_2_in => x"00008000",
cmd_send_3_in => cmd_send_3_r(0),
scale_3_in => x"8000",
dds_phase_inc_dwell_time_3_in => x"00000000",
dds_phase_inc_step_size_3_in => x"0000D6BF",
idle_samples_3_in => x"00000000",
dds_samples_3_in => x"000004E2",
phase_inc_3_in => x"010624DD",
phase_off_3_in => x"00000000",
swap_sf_3_in => x"00008000",
m_axis_aclk_in => clk_250,
m_axis_aresetn_in => clk_250_aresetn(0),
m0_axis_tdata_out => m_axis_tdata,
m0_axis_tvalid_out => m_axis_tvalid,
m0_axis_tready_in => m_axis_tready,
m1_axis_tdata_out => open,
m1_axis_tvalid_out => open,
m1_axis_tready_in => '1',
cnt_reset_in => cnt_reset,
m0_axis_tvalid_cnt_out => open,
m0_dds_pulse_data_cnt_out => open,
m1_axis_tvalid_cnt_out => open,
m1_dds_pulse_data_cnt_out => open
);
-- big FIFO before JESD TX PORT
i_dac_data_fifo_32kx128 : entity work.axis_data_fifo_32kx128
port map (
s_axis_aclk => clk_250, -- in
s_axis_aresetn => clk_250_aresetn(0), -- in
s_axis_tdata => m_axis_tdata, -- in
s_axis_tvalid => m_axis_tvalid, -- in
s_axis_tready => m_axis_tready, -- out
m_axis_tdata => m_axis_tdata_1, -- out
m_axis_tvalid => m_axis_tvalid_1, -- out
m_axis_tready => m_axis_tready_1 -- in
);
-- big FIFO before JESD TX PORT
i_dac_data_fifo_32kx128_1 : entity work.axis_data_fifo_32kx128
port map (
s_axis_aclk => clk_250, -- in
s_axis_aresetn => clk_250_aresetn(0), -- in
s_axis_tdata => m_axis_tdata_1, -- in
s_axis_tvalid => m_axis_tvalid_1, -- in
s_axis_tready => m_axis_tready_1, -- out
m_axis_tdata => util_mxfe_upack_s_axis_tdata_pipe, -- out
m_axis_tvalid => util_mxfe_upack_s_axis_tvalid_pipe, -- out
m_axis_tready => m_axis_tready_r -- in
);
chan1_i <= util_mxfe_upack_s_axis_tdata_pipe(15 downto 0);
chan1_q <= util_mxfe_upack_s_axis_tdata_pipe(31 downto 16);
chan2_i <= util_mxfe_upack_s_axis_tdata_pipe(47 downto 32);
chan2_q <= util_mxfe_upack_s_axis_tdata_pipe(63 downto 48);
chan3_i <= util_mxfe_upack_s_axis_tdata_pipe(79 downto 64);
chan3_q <= util_mxfe_upack_s_axis_tdata_pipe(95 downto 80);
chan4_i <= util_mxfe_upack_s_axis_tdata_pipe(111 downto 96);
chan4_q <= util_mxfe_upack_s_axis_tdata_pipe(127 downto 112);
-- Stimulus process
stim_proc: process
begin
wait until clk_100_aresetn(0) = '1';
-- wait for 24 us;
wait until rising_edge(clk_250);
m_axis_tready_r <= '1';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(0) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(0) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(1) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(1) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(2) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(2) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
cmd_send_i(3) <= '1';
wait for 200 ns;
wait until rising_edge(clk_100);
cmd_send_i(3) <= '0';
wait for 1 us;
wait until rising_edge(clk_100);
dac_holdoff_r <= '0';
wait for 8 us;
cnt_reset <= '1';
wait until rising_edge(clk_100);
cnt_reset <= '0';
-- m_axis_tready_r <= '0';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '1';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '0';
-- wait until rising_edge(clk_250);
-- m_axis_tready_r <= '1';
wait until rising_edge(clk_100);
wait; -- wait here forever
end process;
end;
sim/tb_cap_plybk.vhd
-286
View File
@@ -1,286 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:22 03/24/2017
-- Design Name:
-- Module Name:
-- Project Name: xem7350
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dac_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
entity tb_cap_plybk is
end tb_cap_plybk;
architecture behavior of tb_cap_plybk is
constant C_M_AXI_DATA_WIDTH : integer := 32;
constant C_M_AXI_ADDR_WIDTH : integer := 32;
-- Clock period definitions
constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
signal clk_125 : std_logic := '0';
signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_125_reset : std_logic;
signal clk_250 : std_logic := '0';
signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_250_areset : std_logic;
signal tx_device_clk_1 : std_logic := '0';
signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal tx_device_clk_aresetn : std_logic;
signal rx_device_clk_1 : std_logic := '0';
signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal rx_device_clk_aresetn : std_logic;
signal rx_device_clk_areset : std_logic;
signal qsfp4_playback_aclk : std_logic := '0';
signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp4_playback_aresetn : std_logic;
signal qsfp1_capture_aclk : std_logic;
signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp1_capture_aresetn : std_logic;
--
signal tick_1ms : std_logic;
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal adc_rx_tdata_128b : std_logic_vector(127 downto 0) := (others => '0');
signal adc_rx_tvalid_128b : std_logic := '0';
signal adc_rx_tready_128b : std_logic;
signal adc_rx_tvalid_128b_cnt : std_logic_vector(31 downto 0);
signal qsfp4_playback_tdata_240b : std_logic_vector(239 downto 0);
signal qsfp4_playback_tvalid_240b : std_logic;
signal qsfp4_playback_tready_240b : std_logic := '1';
signal qsfp1_capture_tdata_240b : std_logic_vector(239 downto 0);
signal qsfp1_capture_tvalid_240b : std_logic;
signal tx_tdata_128b : std_logic_vector(127 downto 0);
signal tx_tvalid_128b : std_logic;
signal tx_tready_128b : std_logic := '1';
signal qsfp1_capture_rx_data_ready : std_logic;
signal playback_data_path_enable_n : std_logic := '1';
signal adc_rx_tvalid_128b_ena : std_logic;
begin
clk_125 <= not clk_125 after CLK_125_PERIOD/2;
clk_250 <= not clk_250 after CLK_250_PERIOD/2;
tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2;
rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2;
qsfp4_playback_aclk <= not qsfp4_playback_aclk after QSFP4_AXIS_ACLK_PERIOD/2;
-- qsfp1_capture_aclk <= not qsfp1_capture_aclk after QSFP1_AXIS_ACLK_PERIOD/2;
--
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
clk_125_reset <= not clk_125_aresetn(0);
--
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1';
end if;
end process;
clk_250_areset <= not clk_250_aresetn(0);
--
process(tx_device_clk_1)
begin
if (rising_edge(tx_device_clk_1)) then
tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1';
end if;
end process;
tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0);
--
process(rx_device_clk_1)
begin
if (rising_edge(rx_device_clk_1)) then
rx_device_clk_aresetn_r <= rx_device_clk_aresetn_r(1 to 15) & '1';
end if;
end process;
rx_device_clk_aresetn <= rx_device_clk_aresetn_r(0);
--
process(qsfp4_playback_aclk)
begin
if (rising_edge(qsfp4_playback_aclk)) then
qsfp4_axis_aresetn_r <= qsfp4_axis_aresetn_r(1 to 15) & '1';
end if;
end process;
qsfp4_playback_aresetn <= qsfp4_axis_aresetn_r(0);
--
process(rx_device_clk_1)
begin
if (rising_edge(rx_device_clk_1)) then
adc_rx_tdata_128b <= adc_rx_tdata_128b + x"0003_0002_0001_0004_0005_0006_0007_0008";
end if;
end process;
--
process(qsfp1_capture_aclk)
begin
if (rising_edge(qsfp1_capture_aclk)) then
qsfp1_axis_aresetn_r <= qsfp1_axis_aresetn_r(1 to 15) & '1';
end if;
end process;
qsfp1_capture_aresetn <= qsfp1_axis_aresetn_r(0);
adc_rx_tvalid_128b_ena <= adc_rx_tvalid_128b and qsfp1_capture_rx_data_ready;
i_qsfp4_playback_intfc : entity work.qsfp4_playback_intfc
port map (
rx_device_clk_in => rx_device_clk_1,
rx_device_clk_aresetn_in => rx_device_clk_aresetn,
rx_tdata_128b_in => adc_rx_tdata_128b,
rx_tvalid_128b_in => adc_rx_tvalid_128b_ena,
rx_tready_128b_out => adc_rx_tready_128b,
rx_tvalid_128b_cnt_out => adc_rx_tvalid_128b_cnt,
rx_tvalid_128b_en_cnt_out => open,
playback_data_path_enable_n_in => playback_data_path_enable_n,
qsfp4_playback_aclk_in => qsfp4_playback_aclk,
qsfp4_playback_aresetn_in => qsfp4_playback_aresetn,
qsfp4_playback_tdata_240b_out => qsfp4_playback_tdata_240b,
qsfp4_playback_tvalid_240b_out => qsfp4_playback_tvalid_240b,
qsfp4_playback_tready_240b_in => qsfp4_playback_tready_240b,
qsfp4_playback_tvalid_240b_cnt_out => open,
cnt_reset_in => '0'
);
--///////////////////////////////
qsfp1_capture_aclk <= qsfp4_playback_aclk; --
qsfp1_capture_tdata_240b <= qsfp4_playback_tdata_240b; --
qsfp1_capture_tvalid_240b <= qsfp4_playback_tvalid_240b; --
--///////////////////////////////
--// ****>>>> FROM QSFP1 CAPTURE INTERFACE
i_qsfp1_capture_intfc : entity work.qsfp1_capture_intfc
port map (
qsfp1_capture_aclk_in => qsfp1_capture_aclk,
qsfp1_capture_aresetn_in => qsfp1_capture_aresetn,
qsfp1_capture_tdata_240b_in => qsfp1_capture_tdata_240b,
qsfp1_capture_tvalid_240b_in => qsfp1_capture_tvalid_240b,
qsfp1_capture_tvalid_240b_cnt_out => open,
qsfp1_capture_fifo_aempty_512b_cnt_out => open,
qsfp1_capture_iq_240b_to_512b_overflow_cnt_out => open,
qsfp1_capture_rx_data_ready_out => qsfp1_capture_rx_data_ready,
qsfp1_capture_rx_data_ready_cnt_out => open,
tx_device_clk_in => tx_device_clk_1,
tx_device_clk_aresetn_in => tx_device_clk_aresetn,
tx_tdata_128b_out => tx_tdata_128b, -- out
tx_tvalid_128b_out => tx_tvalid_128b, -- out
tx_tready_128b_in => tx_tready_128b, -- in
tx_tvalid_128b_cnt_out => open,
cnt_reset_in => '0'
);
-- Stimulus process
stim_proc: process
begin
wait until rx_device_clk_aresetn = '1';
wait for 200 ns;
wait until rising_edge(rx_device_clk_1);
adc_rx_tvalid_128b <= '1';
wait for 500 ns;
wait until rising_edge(rx_device_clk_1);
playback_data_path_enable_n <= '0';
wait for 5 us;
wait until rising_edge(qsfp4_playback_aclk);
playback_data_path_enable_n <='0';
wait for 5 us;
wait until rising_edge(qsfp4_playback_aclk);
qsfp4_playback_tready_240b <='1';
wait; -- wait here forever
end process;
end;
sim/tb_cap_plybk_behav.wcfg
-141
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@@ -1,141 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_cap_plybk_behav.wdb" id="1">
<top_modules>
<top_module name="\$unit_xpm_cdc_sv_220102727 " />
<top_module name="glbl" />
<top_module name="tb_cap_plybk" />
<top_module name="vcomponents" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
<ZoomEndTime time="16.000001 us"></ZoomEndTime>
<Cursor1Time time="1.268070 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="375"></NameColumnWidth>
<ValueColumnWidth column_width="73"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="29" />
<wvobject type="logic" fp_name="/tb_cap_plybk/rx_device_clk_1">
<obj_property name="ElementShortName">rx_device_clk_1</obj_property>
<obj_property name="ObjectShortName">rx_device_clk_1</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/rx_device_clk_aresetn_r">
<obj_property name="ElementShortName">rx_device_clk_aresetn_r[0:15]</obj_property>
<obj_property name="ObjectShortName">rx_device_clk_aresetn_r[0:15]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/rx_device_clk_aresetn">
<obj_property name="ElementShortName">rx_device_clk_aresetn</obj_property>
<obj_property name="ObjectShortName">rx_device_clk_aresetn</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_aclk">
<obj_property name="ElementShortName">qsfp4_playback_aclk</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_aclk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/qsfp4_axis_aresetn_r">
<obj_property name="ElementShortName">qsfp4_axis_aresetn_r[0:15]</obj_property>
<obj_property name="ObjectShortName">qsfp4_axis_aresetn_r[0:15]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_aresetn">
<obj_property name="ElementShortName">qsfp4_playback_aresetn</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_aresetn</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/adc_rx_tdata_128b">
<obj_property name="ElementShortName">adc_rx_tdata_128b[127:0]</obj_property>
<obj_property name="ObjectShortName">adc_rx_tdata_128b[127:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tvalid_128b">
<obj_property name="ElementShortName">adc_rx_tvalid_128b</obj_property>
<obj_property name="ObjectShortName">adc_rx_tvalid_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tready_128b">
<obj_property name="ElementShortName">adc_rx_tready_128b</obj_property>
<obj_property name="ObjectShortName">adc_rx_tready_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/adc_rx_tdata_128b_overflow">
<obj_property name="ElementShortName">adc_rx_tdata_128b_overflow</obj_property>
<obj_property name="ObjectShortName">adc_rx_tdata_128b_overflow</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/rx_tvalid_128b_cnt_out">
<obj_property name="ElementShortName">rx_tvalid_128b_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">rx_tvalid_128b_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/rx_tvalid_128b_en_cnt_out">
<obj_property name="ElementShortName">rx_tvalid_128b_en_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">rx_tvalid_128b_en_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/qsfp4_playback_tdata_240b">
<obj_property name="ElementShortName">qsfp4_playback_tdata_240b[239:0]</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tdata_240b[239:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/qsfp4_playback_tvalid_240b">
<obj_property name="ElementShortName">qsfp4_playback_tvalid_240b</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tvalid_240b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp4_playback_tready_240b">
<obj_property name="ElementShortName">qsfp4_playback_tready_240b</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tready_240b</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp4_playback_intfc/qsfp4_playback_tvalid_240b_cnt_out">
<obj_property name="ElementShortName">qsfp4_playback_tvalid_240b_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp4_playback_tvalid_240b_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/playback_data_path_enable_n">
<obj_property name="ElementShortName">playback_data_path_enable_n</obj_property>
<obj_property name="ObjectShortName">playback_data_path_enable_n</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/qsfp1_capture_tdata_240b">
<obj_property name="ElementShortName">qsfp1_capture_tdata_240b[239:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_tdata_240b[239:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp1_capture_tvalid_240b">
<obj_property name="ElementShortName">qsfp1_capture_tvalid_240b</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_tvalid_240b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/qsfp1_capture_rx_data_ready">
<obj_property name="ElementShortName">qsfp1_capture_rx_data_ready</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_rx_data_ready</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_rx_data_ready_cnt_out">
<obj_property name="ElementShortName">qsfp1_capture_rx_data_ready_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_rx_data_ready_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_fifo_aempty_512b_cnt_out">
<obj_property name="ElementShortName">qsfp1_capture_fifo_aempty_512b_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_fifo_aempty_512b_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_capture_iq_240b_to_512b_overflow_cnt_out">
<obj_property name="ElementShortName">qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0]</obj_property>
<obj_property name="ObjectShortName">qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_cap_plybk/tx_tdata_128b">
<obj_property name="ElementShortName">tx_tdata_128b[127:0]</obj_property>
<obj_property name="ObjectShortName">tx_tdata_128b[127:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/tx_tvalid_128b">
<obj_property name="ElementShortName">tx_tvalid_128b</obj_property>
<obj_property name="ObjectShortName">tx_tvalid_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/tx_tready_128b">
<obj_property name="ElementShortName">tx_tready_128b</obj_property>
<obj_property name="ObjectShortName">tx_tready_128b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_512b">
<obj_property name="ElementShortName">qsfp1_tready_512b</obj_property>
<obj_property name="ObjectShortName">qsfp1_tready_512b</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_512b_pipe">
<obj_property name="ElementShortName">qsfp1_tready_512b_pipe</obj_property>
<obj_property name="ObjectShortName">qsfp1_tready_512b_pipe</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_cap_plybk/i_qsfp1_capture_intfc/qsfp1_tready_128b">
<obj_property name="ElementShortName">qsfp1_tready_128b</obj_property>
<obj_property name="ObjectShortName">qsfp1_tready_128b</obj_property>
</wvobject>
</wave_config>
sim/test_bench.vhd
-188
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@@ -1,188 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:22 03/24/2017
-- Design Name:
-- Module Name:
-- Project Name: xem7350
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dac_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
entity test_bench is
end test_bench;
architecture behavior of test_bench is
constant C_M_AXI_DATA_WIDTH : integer := 32;
constant C_M_AXI_ADDR_WIDTH : integer := 32;
-- Clock period definitions
constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz
constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz
constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz
constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz
constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns;
signal clk_125 : std_logic := '0';
signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_125_reset : std_logic;
signal clk_250 : std_logic := '0';
signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0');
signal clk_250_areset : std_logic;
signal tx_device_clk_1 : std_logic := '0';
signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal tx_device_clk_aresetn : std_logic;
signal rx_device_clk_1 : std_logic := '0';
signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal rx_device_clk_aresetn : std_logic;
signal rx_device_clk_areset : std_logic;
signal qsfp4_axis_aclk : std_logic := '0';
signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp4_axis_aresetn : std_logic;
signal qsfp1_axis_aclk : std_logic := '0';
signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0');
signal qsfp1_axis_aresetn : std_logic;
--
signal tick_1ms : std_logic;
signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
clk_125 <= not clk_125 after CLK_125_PERIOD/2;
clk_250 <= not clk_250 after CLK_250_PERIOD/2;
tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2;
rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2;
qsfp4_axis_aclk <= not qsfp4_axis_aclk after QSFP4_AXIS_ACLK_PERIOD/2;
qsfp1_axis_aclk <= not qsfp1_axis_aclk after QSFP1_AXIS_ACLK_PERIOD/2;
--
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1';
end if;
end process;
clk_125_reset <= not clk_125_aresetn(0);
--
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1';
end if;
end process;
clk_250_areset <= not clk_250_aresetn(0);
--
process(tx_device_clk_1)
begin
if (rising_edge(tx_device_clk_1)) then
tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1';
end if;
end process;
tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0);
------------------------------------------------
i_tick_gen : entity work.tick_gen
generic map (
CLOCK_SPEED_MHZ => 125
)
port map (
clk_in => clk_125,
tick_1us_out => open,
tick_1ms_out => tick_1ms,
tick_500ms_out => open,
tick_750ms_out => open,
tick_1s_out => open,
prog_us_tick_rate_in => x"0000_0000",
prog_us_tick_out => open,
reset_in => clk_125_reset
);
process(clk_125)
begin
if (rising_edge(clk_125)) then
clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_125_tick_1ms_r(0 to 1) = "01") then
clk_125_freq_r <= clk_125_cnt_r;
clk_125_cnt_r <= (others => '0');
else
clk_125_cnt_r <= clk_125_cnt_r + 1;
end if;
end if;
end process;
process(clk_250)
begin
if (rising_edge(clk_250)) then
clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
if (clk_250_tick_1ms_r(0 to 1) = "01") then
clk_250_freq_r <= clk_250_cnt_r;
clk_250_cnt_r <= (others => '0');
else
clk_250_cnt_r <= clk_250_cnt_r + 1;
end if;
end if;
end process;
end;