diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp deleted file mode 100755 index 2e8c58c..0000000 Binary files a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp and /dev/null differ diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml deleted file mode 100644 index c36d602..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml +++ /dev/null @@ -1,1711 +0,0 @@ - - - xilinx.com - customized_ip - axis_register_slice_32 - 1.0 - - - RSTIF - RSTIF - - - - - - - RST - - - aresetn - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - CLKIF - CLKIF - - - - - - - CLK - - - aclk - - - - - - FREQ_HZ - aclk frequency - aclk frequency - 10000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - CLKIF2X - CLKIF2X - - - - - - - CLK - - - aclk2x - - - - - - FREQ_HZ - aclk2x frequency - aclk2x frequency - 10000000 - - - FREQ_TOLERANCE_HZ - 0 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_PORT - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - CLKENIF - CLKENIF - - - - - - - CE - - - aclken - - - - - - POLARITY - ACTIVE_LOW - - - none - - - - - - - - false - - - - - - S_AXIS - S_AXIS - - - - - - - TVALID - - - s_axis_tvalid - - - - - TREADY - - - s_axis_tready - - - - - TDATA - - - s_axis_tdata - - - - - TSTRB - - - s_axis_tstrb - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TID - - - s_axis_tid - - - - - TDEST - - - s_axis_tdest - - - - - TUSER - - - s_axis_tuser - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - M_AXIS - M_AXIS - - - - - - - TVALID - - - m_axis_tvalid - - - - - TREADY - - - m_axis_tready - - - - - TDATA - - - m_axis_tdata - - - - - TSTRB - - - m_axis_tstrb - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TID - - - m_axis_tid - - - - - TDEST - - - m_axis_tdest - - - - - TUSER - - - m_axis_tuser - - - - - - TDATA_NUM_BYTES - 4 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 1 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.0 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - - - xilinx_externalfiles - External Files - :vivado.xilinx.com:external.files - - xilinx_externalfiles_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_implementation - Implementation - :vivado.xilinx.com:implementation - axis_register_slice_v1_1_29_axis_register_slice - - xilinx_implementation_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_synthesisconstraints - Synthesis Constraints - :vivado.xilinx.com:synthesis.constraints - - xilinx_synthesisconstraints_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_verilogbehavioralsimulation - Verilog Simulation - verilogSource:vivado.xilinx.com:simulation - verilog - axis_register_slice_v1_1_29_axis_register_slice - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogbehavioralsimulation_view_fileset - - - - GENtimestamp - Wed Jul 15 19:17:47 UTC 2026 - - - outputProductCRC - 9:abb75340 - - - - - xilinx_verilogsimulationwrapper - Verilog Simulation Wrapper - verilogSource:vivado.xilinx.com:simulation.wrapper - verilog - axis_register_slice_32 - - xilinx_verilogsimulationwrapper_view_fileset - - - - GENtimestamp - Wed Jul 15 19:17:47 UTC 2026 - - - outputProductCRC - 9:abb75340 - - - - - xilinx_verilogsynthesis - Verilog Synthesis - verilogSource:vivado.xilinx.com:synthesis - verilog - axis_register_slice_v1_1_29_axis_register_slice - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - - xilinx_verilogsynthesis_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - xilinx_verilogsynthesiswrapper - Verilog Synthesis Wrapper - verilogSource:vivado.xilinx.com:synthesis.wrapper - verilog - axis_register_slice_32 - - xilinx_verilogsynthesiswrapper_view_fileset - - - - GENtimestamp - Tue Jun 02 16:38:12 UTC 2026 - - - outputProductCRC - 9:259644d4 - - - - - - - aclk - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - aclk2x - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - aresetn - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x1 - - - - - aclken - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - s_axis_tvalid - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x0 - - - - - s_axis_tready - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - s_axis_tdata - - in - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x00000000 - - - - - - true - - - - - - s_axis_tstrb - - in - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0xF - - - - - - false - - - - - - s_axis_tkeep - - in - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0xF - - - - - - false - - - - - - s_axis_tlast - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x1 - - - - - - false - - - - - - s_axis_tid - - in - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - s_axis_tdest - - in - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - s_axis_tuser - - in - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x0 - - - - - - false - - - - - - m_axis_tvalid - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - m_axis_tready - - in - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - 0x1 - - - - - - true - - - - - - m_axis_tdata - - out - - 31 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - true - - - - - - m_axis_tstrb - - out - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tkeep - - out - - 3 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tlast - - out - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tid - - out - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tdest - - out - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - m_axis_tuser - - out - - 0 - 0 - - - - wire - xilinx_verilogsynthesis - xilinx_verilogbehavioralsimulation - - - - - - - false - - - - - - - - C_FAMILY - zynquplus - - - C_AXIS_TDATA_WIDTH - 32 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 1 - - - C_AXIS_SIGNAL_SET - 0b00000000000000000000000000000011 - - - C_REG_CONFIG - 8 - - - C_NUM_SLR_CROSSINGS - 0 - - - C_PIPELINES_MASTER - 0 - - - C_PIPELINES_SLAVE - 0 - - - C_PIPELINES_MIDDLE - 0 - - - - - - choice_pairs_37189c7b - 0 - 1 - - - choice_pairs_962b65a8 - 1 - 0 - 8 - 7 - 12 - 13 - 14 - 15 - 16 - 17 - 18 - - - - - xilinx_externalfiles_view_fileset - - axis_register_slice_32_stub.vhdl - vhdlSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - axis_register_slice_32.dcp - dcp - USED_IN_implementation - USED_IN_synthesis - xil_defaultlib - - - axis_register_slice_32_sim_netlist.v - verilogSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axis_register_slice_32_sim_netlist.vhdl - vhdlSource - USED_IN_simulation - USED_IN_single_language - xil_defaultlib - - - axis_register_slice_32_stub.v - verilogSource - USED_IN_synth_blackbox_stub - xil_defaultlib - - - - xilinx_implementation_view_fileset - - axis_register_slice_32_clocks.xdc - xdc - USED_IN_implementation - USED_IN_synthesis - - processing_order - late - - - - - xilinx_synthesisconstraints_view_fileset - - axis_register_slice_32_ooc.xdc - xdc - USED_IN_implementation - USED_IN_out_of_context - USED_IN_synthesis - - - - xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_1.vh - verilogSource - USED_IN_ipstatic - true - axis_infrastructure_v1_1_1 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axis_infrastructure_v1_1_1 - - - - - - - - - - - xilinx_verilogbehavioralsimulation_view_fileset - - hdl/axis_register_slice_v1_1_vl_rfs.v - verilogSource - USED_IN_ipstatic - axis_register_slice_v1_1_29 - - - - xilinx_verilogsimulationwrapper_view_fileset - - sim/axis_register_slice_32.v - verilogSource - xil_defaultlib - - - - xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset - - hdl/axis_infrastructure_v1_1_1.vh - verilogSource - true - axis_infrastructure_v1_1_1 - - - hdl/axis_infrastructure_v1_1_vl_rfs.v - verilogSource - axis_infrastructure_v1_1_1 - - - - - - - - - - - xilinx_verilogsynthesis_view_fileset - - hdl/axis_register_slice_v1_1_vl_rfs.v - verilogSource - axis_register_slice_v1_1_29 - - - - xilinx_verilogsynthesiswrapper_view_fileset - - synth/axis_register_slice_32.v - verilogSource - xil_defaultlib - - - - The AXI4-Stream Register Slice IP provides the infrastructure to insert a pipeline stage between a AXI4-Stream master and slave. - - - TDATA_NUM_BYTES - TDATA Width (bytes) - 4 - - - - true - - - - - - TID_WIDTH - TID Width (bits) - 0 - - - - true - - - - - - TDEST_WIDTH - TDEST Width (bits) - 0 - - - - true - - - - - - TUSER_WIDTH - TUSER Width (bits) - 0 - - - - true - - - - - - REG_CONFIG - Register Pipeline Type - 8 - - - - true - - - - - - HAS_TREADY - Enable TREADY - 1 - - - - true - - - - - - HAS_TSTRB - Enable TSTRB - 0 - - - - true - - - - - - HAS_TKEEP - Enable TKEEP - 0 - - - - true - - - - - - HAS_TLAST - Enable TLAST - 0 - - - - true - - - - - - HAS_ACLKEN - Enable ACLKEN - 0 - - - - true - - - - - - NUM_SLR_CROSSINGS - Number of SLR Crossings - 0 - - - - false - - - - - - PIPELINES_MASTER - Pipeline Stages within Master-side SLR - 0 - - - - false - - - - - - PIPELINES_MIDDLE - Pipeline Stages within Middle SLR - 0 - - - - false - - - - - - PIPELINES_SLAVE - Pipeline Stages within Slave-side SLR - 0 - - - - false - - - - - - Component_Name - axis_register_slice_32 - - - - - AXI4-Stream Register Slice - - XPM_FIFO - XPM_CDC - - 29 - - - - - - - - - 2023.2 - - - - - - - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc deleted file mode 100644 index d5fdeee..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc +++ /dev/null @@ -1,6 +0,0 @@ -############################################################################################################### -# Core-Level Timing Constraints for axi_register_slice Component "axis_register_slice_32" -############################################################################################################### -# -# This component is not configured in a multi-SLR crossing or auto-pipelining mode. -# No timing core-level constraints are needed. diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc deleted file mode 100644 index 9f673bc..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc +++ /dev/null @@ -1,57 +0,0 @@ -# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. -# -# This file contains confidential and proprietary information -# of AMD and is protected under U.S. and international copyright -# and other intellectual property laws. -# -# DISCLAIMER -# This disclaimer is not a license and does not grant any -# rights to the materials distributed herewith. Except as -# otherwise provided in a valid license issued to you by -# AMD, and to the maximum extent permitted by applicable -# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -# (2) AMD shall not be liable (whether in contract or tort, -# including negligence, or under any other theory of -# liability) for any loss or damage of any kind or nature -# related to, arising under or in connection with these -# materials, including for any direct, or any indirect, -# special, incidental, or consequential loss or damage -# (including loss of data, profits, goodwill, or any type of -# loss or damage suffered as a result of any action brought -# by a third party) even if such damage or loss was -# reasonably foreseeable or AMD had been advised of the -# possibility of the same. -# -# CRITICAL APPLICATIONS -# AMD products are not designed or intended to be fail- -# safe, or for use in any application requiring fail-safe -# performance, such as life-support or safety devices or -# systems, Class III medical devices, nuclear facilities, -# applications related to the deployment of airbags, or any -# other applications that could lead to death, personal -# injury, or severe property or environmental damage -# (individually and collectively, "Critical -# Applications"). Customer assumes the sole risk and -# liability of any use of AMD products in Critical -# Applications, subject only to applicable laws and -# regulations governing limitations on product liability. -# -# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -# PART OF THIS FILE AT ALL TIMES. -# -# DO NOT MODIFY THIS FILE. -# ######################################################### -# -# This XDC is used only in OOC mode for synthesis, implementation -# -# ######################################################### - - -create_clock -period 100 -name aclk [get_ports aclk] - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v deleted file mode 100644 index d2ccd4d..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v +++ /dev/null @@ -1,1100 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -// Date : Thu Apr 23 10:08:04 2026 -// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS -// Command : write_verilog -force -mode funcsim -rename_top axis_register_slice_32 -prefix -// axis_register_slice_32_ axis_register_slice_32_sim_netlist.v -// Design : axis_register_slice_32 -// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified -// or synthesized. This netlist cannot be used for SDF annotated simulation. -// Device : xczu19eg-ffvc1760-2-i -// -------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *) -(* NotValidForBitStream *) -module axis_register_slice_32 - (aclk, - aresetn, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata); - (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input aclk; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aresetn; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) input s_axis_tvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) output s_axis_tready; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) input [31:0]s_axis_tdata; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) output m_axis_tvalid; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) input m_axis_tready; - (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) output [31:0]m_axis_tdata; - - wire aclk; - wire aresetn; - wire [31:0]m_axis_tdata; - wire m_axis_tready; - wire m_axis_tvalid; - wire [31:0]s_axis_tdata; - wire s_axis_tready; - wire s_axis_tvalid; - wire NLW_inst_m_axis_tlast_UNCONNECTED; - wire [0:0]NLW_inst_m_axis_tdest_UNCONNECTED; - wire [0:0]NLW_inst_m_axis_tid_UNCONNECTED; - wire [3:0]NLW_inst_m_axis_tkeep_UNCONNECTED; - wire [3:0]NLW_inst_m_axis_tstrb_UNCONNECTED; - wire [0:0]NLW_inst_m_axis_tuser_UNCONNECTED; - - (* C_AXIS_SIGNAL_SET = "3" *) - (* C_AXIS_TDATA_WIDTH = "32" *) - (* C_AXIS_TDEST_WIDTH = "1" *) - (* C_AXIS_TID_WIDTH = "1" *) - (* C_AXIS_TUSER_WIDTH = "1" *) - (* C_FAMILY = "zynquplus" *) - (* C_NUM_SLR_CROSSINGS = "0" *) - (* C_PIPELINES_MASTER = "0" *) - (* C_PIPELINES_MIDDLE = "0" *) - (* C_PIPELINES_SLAVE = "0" *) - (* C_REG_CONFIG = "8" *) - (* DowngradeIPIdentifiedWarnings = "yes" *) - (* G_INDX_SS_TDATA = "1" *) - (* G_INDX_SS_TDEST = "6" *) - (* G_INDX_SS_TID = "5" *) - (* G_INDX_SS_TKEEP = "3" *) - (* G_INDX_SS_TLAST = "4" *) - (* G_INDX_SS_TREADY = "0" *) - (* G_INDX_SS_TSTRB = "2" *) - (* G_INDX_SS_TUSER = "7" *) - (* G_MASK_SS_TDATA = "2" *) - (* G_MASK_SS_TDEST = "64" *) - (* G_MASK_SS_TID = "32" *) - (* G_MASK_SS_TKEEP = "8" *) - (* G_MASK_SS_TLAST = "16" *) - (* G_MASK_SS_TREADY = "1" *) - (* G_MASK_SS_TSTRB = "4" *) - (* G_MASK_SS_TUSER = "128" *) - (* G_TASK_SEVERITY_ERR = "2" *) - (* G_TASK_SEVERITY_INFO = "0" *) - (* G_TASK_SEVERITY_WARNING = "1" *) - (* P_TPAYLOAD_WIDTH = "32" *) - axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice inst - (.aclk(aclk), - .aclk2x(1'b0), - .aclken(1'b1), - .aresetn(aresetn), - .m_axis_tdata(m_axis_tdata), - .m_axis_tdest(NLW_inst_m_axis_tdest_UNCONNECTED[0]), - .m_axis_tid(NLW_inst_m_axis_tid_UNCONNECTED[0]), - .m_axis_tkeep(NLW_inst_m_axis_tkeep_UNCONNECTED[3:0]), - .m_axis_tlast(NLW_inst_m_axis_tlast_UNCONNECTED), - .m_axis_tready(m_axis_tready), - .m_axis_tstrb(NLW_inst_m_axis_tstrb_UNCONNECTED[3:0]), - .m_axis_tuser(NLW_inst_m_axis_tuser_UNCONNECTED[0]), - .m_axis_tvalid(m_axis_tvalid), - .s_axis_tdata(s_axis_tdata), - .s_axis_tdest(1'b0), - .s_axis_tid(1'b0), - .s_axis_tkeep({1'b1,1'b1,1'b1,1'b1}), - .s_axis_tlast(1'b1), - .s_axis_tready(s_axis_tready), - .s_axis_tstrb({1'b1,1'b1,1'b1,1'b1}), - .s_axis_tuser(1'b0), - .s_axis_tvalid(s_axis_tvalid)); -endmodule - -(* C_AXIS_SIGNAL_SET = "3" *) (* C_AXIS_TDATA_WIDTH = "32" *) (* C_AXIS_TDEST_WIDTH = "1" *) -(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "1" *) (* C_FAMILY = "zynquplus" *) -(* C_NUM_SLR_CROSSINGS = "0" *) (* C_PIPELINES_MASTER = "0" *) (* C_PIPELINES_MIDDLE = "0" *) -(* C_PIPELINES_SLAVE = "0" *) (* C_REG_CONFIG = "8" *) (* DowngradeIPIdentifiedWarnings = "yes" *) -(* G_INDX_SS_TDATA = "1" *) (* G_INDX_SS_TDEST = "6" *) (* G_INDX_SS_TID = "5" *) -(* G_INDX_SS_TKEEP = "3" *) (* G_INDX_SS_TLAST = "4" *) (* G_INDX_SS_TREADY = "0" *) -(* G_INDX_SS_TSTRB = "2" *) (* G_INDX_SS_TUSER = "7" *) (* G_MASK_SS_TDATA = "2" *) -(* G_MASK_SS_TDEST = "64" *) (* G_MASK_SS_TID = "32" *) (* G_MASK_SS_TKEEP = "8" *) -(* G_MASK_SS_TLAST = "16" *) (* G_MASK_SS_TREADY = "1" *) (* G_MASK_SS_TSTRB = "4" *) -(* G_MASK_SS_TUSER = "128" *) (* G_TASK_SEVERITY_ERR = "2" *) (* G_TASK_SEVERITY_INFO = "0" *) -(* G_TASK_SEVERITY_WARNING = "1" *) (* P_TPAYLOAD_WIDTH = "32" *) -module axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice - (aclk, - aclk2x, - aresetn, - aclken, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - s_axis_tstrb, - s_axis_tkeep, - s_axis_tlast, - s_axis_tid, - s_axis_tdest, - s_axis_tuser, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata, - m_axis_tstrb, - m_axis_tkeep, - m_axis_tlast, - m_axis_tid, - m_axis_tdest, - m_axis_tuser); - input aclk; - input aclk2x; - input aresetn; - input aclken; - input s_axis_tvalid; - output s_axis_tready; - input [31:0]s_axis_tdata; - input [3:0]s_axis_tstrb; - input [3:0]s_axis_tkeep; - input s_axis_tlast; - input [0:0]s_axis_tid; - input [0:0]s_axis_tdest; - input [0:0]s_axis_tuser; - output m_axis_tvalid; - input m_axis_tready; - output [31:0]m_axis_tdata; - output [3:0]m_axis_tstrb; - output [3:0]m_axis_tkeep; - output m_axis_tlast; - output [0:0]m_axis_tid; - output [0:0]m_axis_tdest; - output [0:0]m_axis_tuser; - - wire \ ; - wire aclk; - wire areset_r; - wire areset_r_i_1_n_0; - wire aresetn; - wire [31:0]m_axis_tdata; - wire m_axis_tready; - wire m_axis_tvalid; - wire [31:0]s_axis_tdata; - wire s_axis_tready; - wire s_axis_tvalid; - - assign m_axis_tdest[0] = \ ; - assign m_axis_tid[0] = \ ; - assign m_axis_tkeep[3] = \ ; - assign m_axis_tkeep[2] = \ ; - assign m_axis_tkeep[1] = \ ; - assign m_axis_tkeep[0] = \ ; - assign m_axis_tlast = \ ; - assign m_axis_tstrb[3] = \ ; - assign m_axis_tstrb[2] = \ ; - assign m_axis_tstrb[1] = \ ; - assign m_axis_tstrb[0] = \ ; - assign m_axis_tuser[0] = \ ; - GND GND - (.G(\ )); - LUT1 #( - .INIT(2'h1)) - areset_r_i_1 - (.I0(aresetn), - .O(areset_r_i_1_n_0)); - FDRE #( - .INIT(1'b0)) - areset_r_reg - (.C(aclk), - .CE(1'b1), - .D(areset_r_i_1_n_0), - .Q(areset_r), - .R(1'b0)); - axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice axisc_register_slice_0 - (.Q(m_axis_tvalid), - .aclk(aclk), - .areset_r(areset_r), - .m_axis_tdata(m_axis_tdata), - .m_axis_tready(m_axis_tready), - .s_axis_tdata(s_axis_tdata), - .s_axis_tready(s_axis_tready), - .s_axis_tvalid(s_axis_tvalid)); -endmodule - -module axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice - (s_axis_tready, - Q, - m_axis_tdata, - aclk, - m_axis_tready, - s_axis_tvalid, - s_axis_tdata, - areset_r); - output s_axis_tready; - output [0:0]Q; - output [31:0]m_axis_tdata; - input aclk; - input m_axis_tready; - input s_axis_tvalid; - input [31:0]s_axis_tdata; - input areset_r; - - wire [0:0]Q; - wire aclk; - wire areset_r; - wire \aresetn_d_reg_n_0_[0] ; - wire \aresetn_d_reg_n_0_[1] ; - wire [31:0]m_axis_tdata; - wire m_axis_tready; - wire [31:0]p_0_in; - wire [0:0]p_1_out; - wire [31:0]s_axis_tdata; - wire s_axis_tready; - wire s_axis_tvalid; - wire s_ready_i0; - wire s_ready_i_i_1_n_0; - wire s_ready_i_i_2_n_0; - wire [1:0]state; - wire \state[0]_i_1_n_0 ; - wire \state[0]_i_2_n_0 ; - wire \state_reg_n_0_[1] ; - wire storage_data1; - wire [31:0]storage_data2; - wire storage_data2_0; - - LUT4 #( - .INIT(16'hE420)) - \__2/i_ - (.I0(\state_reg_n_0_[1] ), - .I1(Q), - .I2(s_axis_tvalid), - .I3(m_axis_tready), - .O(storage_data1)); - LUT1 #( - .INIT(2'h1)) - \aresetn_d[0]_i_1 - (.I0(areset_r), - .O(p_1_out)); - (* equivalent_register_removal = "no" *) - FDRE #( - .INIT(1'b0)) - \aresetn_d_reg[0] - (.C(aclk), - .CE(1'b1), - .D(p_1_out), - .Q(\aresetn_d_reg_n_0_[0] ), - .R(1'b0)); - (* equivalent_register_removal = "no" *) - FDRE #( - .INIT(1'b0)) - \aresetn_d_reg[1] - (.C(aclk), - .CE(1'b1), - .D(\aresetn_d_reg_n_0_[0] ), - .Q(\aresetn_d_reg_n_0_[1] ), - .R(1'b0)); - LUT6 #( - .INIT(64'h00000000E2E2EEE2)) - s_ready_i_i_1 - (.I0(s_axis_tready), - .I1(s_ready_i_i_2_n_0), - .I2(s_ready_i0), - .I3(m_axis_tready), - .I4(\state_reg_n_0_[1] ), - .I5(areset_r), - .O(s_ready_i_i_1_n_0)); - LUT6 #( - .INIT(64'h2808FFFF00000000)) - s_ready_i_i_2 - (.I0(Q), - .I1(m_axis_tready), - .I2(\state_reg_n_0_[1] ), - .I3(s_axis_tvalid), - .I4(\aresetn_d_reg_n_0_[1] ), - .I5(\aresetn_d_reg_n_0_[0] ), - .O(s_ready_i_i_2_n_0)); - LUT2 #( - .INIT(4'h2)) - s_ready_i_i_3 - (.I0(\aresetn_d_reg_n_0_[0] ), - .I1(\aresetn_d_reg_n_0_[1] ), - .O(s_ready_i0)); - FDRE #( - .INIT(1'b0)) - s_ready_i_reg - (.C(aclk), - .CE(1'b1), - .D(s_ready_i_i_1_n_0), - .Q(s_axis_tready), - .R(1'b0)); - LUT3 #( - .INIT(8'hBA)) - \state[0]_i_1 - (.I0(areset_r), - .I1(\aresetn_d_reg_n_0_[1] ), - .I2(\aresetn_d_reg_n_0_[0] ), - .O(\state[0]_i_1_n_0 )); - LUT5 #( - .INIT(32'h2A808A8A)) - \state[0]_i_2 - (.I0(\aresetn_d_reg_n_0_[0] ), - .I1(m_axis_tready), - .I2(Q), - .I3(s_axis_tvalid), - .I4(\state_reg_n_0_[1] ), - .O(\state[0]_i_2_n_0 )); - LUT4 #( - .INIT(16'h7808)) - \state[0]_i_3 - (.I0(m_axis_tready), - .I1(Q), - .I2(\state_reg_n_0_[1] ), - .I3(s_axis_tvalid), - .O(state[0])); - LUT4 #( - .INIT(16'hFD2D)) - \state[1]_i_1 - (.I0(\state_reg_n_0_[1] ), - .I1(s_axis_tvalid), - .I2(Q), - .I3(m_axis_tready), - .O(state[1])); - (* FSM_ENCODING = "none" *) - FDRE #( - .INIT(1'b0)) - \state_reg[0] - (.C(aclk), - .CE(\state[0]_i_2_n_0 ), - .D(state[0]), - .Q(Q), - .R(\state[0]_i_1_n_0 )); - (* FSM_ENCODING = "none" *) - FDSE #( - .INIT(1'b1)) - \state_reg[1] - (.C(aclk), - .CE(\state[0]_i_2_n_0 ), - .D(state[1]), - .Q(\state_reg_n_0_[1] ), - .S(\state[0]_i_1_n_0 )); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[0]_i_1 - (.I0(storage_data2[0]), - .I1(s_axis_tdata[0]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[0])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[10]_i_1 - (.I0(storage_data2[10]), - .I1(s_axis_tdata[10]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[10])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[11]_i_1 - (.I0(storage_data2[11]), - .I1(s_axis_tdata[11]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[11])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[12]_i_1 - (.I0(storage_data2[12]), - .I1(s_axis_tdata[12]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[12])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[13]_i_1 - (.I0(storage_data2[13]), - .I1(s_axis_tdata[13]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[13])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[14]_i_1 - (.I0(storage_data2[14]), - .I1(s_axis_tdata[14]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[14])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[15]_i_1 - (.I0(storage_data2[15]), - .I1(s_axis_tdata[15]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[15])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[16]_i_1 - (.I0(storage_data2[16]), - .I1(s_axis_tdata[16]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[16])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[17]_i_1 - (.I0(storage_data2[17]), - .I1(s_axis_tdata[17]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[17])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[18]_i_1 - (.I0(storage_data2[18]), - .I1(s_axis_tdata[18]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[18])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[19]_i_1 - (.I0(storage_data2[19]), - .I1(s_axis_tdata[19]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[19])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[1]_i_1 - (.I0(storage_data2[1]), - .I1(s_axis_tdata[1]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[1])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[20]_i_1 - (.I0(storage_data2[20]), - .I1(s_axis_tdata[20]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[20])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[21]_i_1 - (.I0(storage_data2[21]), - .I1(s_axis_tdata[21]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[21])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[22]_i_1 - (.I0(storage_data2[22]), - .I1(s_axis_tdata[22]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[22])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[23]_i_1 - (.I0(storage_data2[23]), - .I1(s_axis_tdata[23]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[23])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[24]_i_1 - (.I0(storage_data2[24]), - .I1(s_axis_tdata[24]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[24])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[25]_i_1 - (.I0(storage_data2[25]), - .I1(s_axis_tdata[25]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[25])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[26]_i_1 - (.I0(storage_data2[26]), - .I1(s_axis_tdata[26]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[26])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[27]_i_1 - (.I0(storage_data2[27]), - .I1(s_axis_tdata[27]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[27])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[28]_i_1 - (.I0(storage_data2[28]), - .I1(s_axis_tdata[28]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[28])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[29]_i_1 - (.I0(storage_data2[29]), - .I1(s_axis_tdata[29]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[29])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[2]_i_1 - (.I0(storage_data2[2]), - .I1(s_axis_tdata[2]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[2])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[30]_i_1 - (.I0(storage_data2[30]), - .I1(s_axis_tdata[30]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[30])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[31]_i_1 - (.I0(storage_data2[31]), - .I1(s_axis_tdata[31]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[31])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[3]_i_1 - (.I0(storage_data2[3]), - .I1(s_axis_tdata[3]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[3])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[4]_i_1 - (.I0(storage_data2[4]), - .I1(s_axis_tdata[4]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[4])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[5]_i_1 - (.I0(storage_data2[5]), - .I1(s_axis_tdata[5]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[5])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[6]_i_1 - (.I0(storage_data2[6]), - .I1(s_axis_tdata[6]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[6])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[7]_i_1 - (.I0(storage_data2[7]), - .I1(s_axis_tdata[7]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[7])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[8]_i_1 - (.I0(storage_data2[8]), - .I1(s_axis_tdata[8]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[8])); - LUT4 #( - .INIT(16'hCCAC)) - \storage_data1[9]_i_1 - (.I0(storage_data2[9]), - .I1(s_axis_tdata[9]), - .I2(Q), - .I3(\state_reg_n_0_[1] ), - .O(p_0_in[9])); - FDRE \storage_data1_reg[0] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[0]), - .Q(m_axis_tdata[0]), - .R(1'b0)); - FDRE \storage_data1_reg[10] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[10]), - .Q(m_axis_tdata[10]), - .R(1'b0)); - FDRE \storage_data1_reg[11] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[11]), - .Q(m_axis_tdata[11]), - .R(1'b0)); - FDRE \storage_data1_reg[12] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[12]), - .Q(m_axis_tdata[12]), - .R(1'b0)); - FDRE \storage_data1_reg[13] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[13]), - .Q(m_axis_tdata[13]), - .R(1'b0)); - FDRE \storage_data1_reg[14] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[14]), - .Q(m_axis_tdata[14]), - .R(1'b0)); - FDRE \storage_data1_reg[15] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[15]), - .Q(m_axis_tdata[15]), - .R(1'b0)); - FDRE \storage_data1_reg[16] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[16]), - .Q(m_axis_tdata[16]), - .R(1'b0)); - FDRE \storage_data1_reg[17] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[17]), - .Q(m_axis_tdata[17]), - .R(1'b0)); - FDRE \storage_data1_reg[18] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[18]), - .Q(m_axis_tdata[18]), - .R(1'b0)); - FDRE \storage_data1_reg[19] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[19]), - .Q(m_axis_tdata[19]), - .R(1'b0)); - FDRE \storage_data1_reg[1] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[1]), - .Q(m_axis_tdata[1]), - .R(1'b0)); - FDRE \storage_data1_reg[20] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[20]), - .Q(m_axis_tdata[20]), - .R(1'b0)); - FDRE \storage_data1_reg[21] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[21]), - .Q(m_axis_tdata[21]), - .R(1'b0)); - FDRE \storage_data1_reg[22] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[22]), - .Q(m_axis_tdata[22]), - .R(1'b0)); - FDRE \storage_data1_reg[23] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[23]), - .Q(m_axis_tdata[23]), - .R(1'b0)); - FDRE \storage_data1_reg[24] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[24]), - .Q(m_axis_tdata[24]), - .R(1'b0)); - FDRE \storage_data1_reg[25] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[25]), - .Q(m_axis_tdata[25]), - .R(1'b0)); - FDRE \storage_data1_reg[26] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[26]), - .Q(m_axis_tdata[26]), - .R(1'b0)); - FDRE \storage_data1_reg[27] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[27]), - .Q(m_axis_tdata[27]), - .R(1'b0)); - FDRE \storage_data1_reg[28] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[28]), - .Q(m_axis_tdata[28]), - .R(1'b0)); - FDRE \storage_data1_reg[29] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[29]), - .Q(m_axis_tdata[29]), - .R(1'b0)); - FDRE \storage_data1_reg[2] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[2]), - .Q(m_axis_tdata[2]), - .R(1'b0)); - FDRE \storage_data1_reg[30] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[30]), - .Q(m_axis_tdata[30]), - .R(1'b0)); - FDRE \storage_data1_reg[31] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[31]), - .Q(m_axis_tdata[31]), - .R(1'b0)); - FDRE \storage_data1_reg[3] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[3]), - .Q(m_axis_tdata[3]), - .R(1'b0)); - FDRE \storage_data1_reg[4] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[4]), - .Q(m_axis_tdata[4]), - .R(1'b0)); - FDRE \storage_data1_reg[5] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[5]), - .Q(m_axis_tdata[5]), - .R(1'b0)); - FDRE \storage_data1_reg[6] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[6]), - .Q(m_axis_tdata[6]), - .R(1'b0)); - FDRE \storage_data1_reg[7] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[7]), - .Q(m_axis_tdata[7]), - .R(1'b0)); - FDRE \storage_data1_reg[8] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[8]), - .Q(m_axis_tdata[8]), - .R(1'b0)); - FDRE \storage_data1_reg[9] - (.C(aclk), - .CE(storage_data1), - .D(p_0_in[9]), - .Q(m_axis_tdata[9]), - .R(1'b0)); - LUT2 #( - .INIT(4'h8)) - \storage_data2[31]_i_1 - (.I0(s_axis_tvalid), - .I1(s_axis_tready), - .O(storage_data2_0)); - FDRE \storage_data2_reg[0] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[0]), - .Q(storage_data2[0]), - .R(1'b0)); - FDRE \storage_data2_reg[10] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[10]), - .Q(storage_data2[10]), - .R(1'b0)); - FDRE \storage_data2_reg[11] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[11]), - .Q(storage_data2[11]), - .R(1'b0)); - FDRE \storage_data2_reg[12] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[12]), - .Q(storage_data2[12]), - .R(1'b0)); - FDRE \storage_data2_reg[13] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[13]), - .Q(storage_data2[13]), - .R(1'b0)); - FDRE \storage_data2_reg[14] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[14]), - .Q(storage_data2[14]), - .R(1'b0)); - FDRE \storage_data2_reg[15] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[15]), - .Q(storage_data2[15]), - .R(1'b0)); - FDRE \storage_data2_reg[16] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[16]), - .Q(storage_data2[16]), - .R(1'b0)); - FDRE \storage_data2_reg[17] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[17]), - .Q(storage_data2[17]), - .R(1'b0)); - FDRE \storage_data2_reg[18] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[18]), - .Q(storage_data2[18]), - .R(1'b0)); - FDRE \storage_data2_reg[19] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[19]), - .Q(storage_data2[19]), - .R(1'b0)); - FDRE \storage_data2_reg[1] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[1]), - .Q(storage_data2[1]), - .R(1'b0)); - FDRE \storage_data2_reg[20] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[20]), - .Q(storage_data2[20]), - .R(1'b0)); - FDRE \storage_data2_reg[21] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[21]), - .Q(storage_data2[21]), - .R(1'b0)); - FDRE \storage_data2_reg[22] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[22]), - .Q(storage_data2[22]), - .R(1'b0)); - FDRE \storage_data2_reg[23] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[23]), - .Q(storage_data2[23]), - .R(1'b0)); - FDRE \storage_data2_reg[24] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[24]), - .Q(storage_data2[24]), - .R(1'b0)); - FDRE \storage_data2_reg[25] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[25]), - .Q(storage_data2[25]), - .R(1'b0)); - FDRE \storage_data2_reg[26] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[26]), - .Q(storage_data2[26]), - .R(1'b0)); - FDRE \storage_data2_reg[27] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[27]), - .Q(storage_data2[27]), - .R(1'b0)); - FDRE \storage_data2_reg[28] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[28]), - .Q(storage_data2[28]), - .R(1'b0)); - FDRE \storage_data2_reg[29] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[29]), - .Q(storage_data2[29]), - .R(1'b0)); - FDRE \storage_data2_reg[2] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[2]), - .Q(storage_data2[2]), - .R(1'b0)); - FDRE \storage_data2_reg[30] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[30]), - .Q(storage_data2[30]), - .R(1'b0)); - FDRE \storage_data2_reg[31] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[31]), - .Q(storage_data2[31]), - .R(1'b0)); - FDRE \storage_data2_reg[3] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[3]), - .Q(storage_data2[3]), - .R(1'b0)); - FDRE \storage_data2_reg[4] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[4]), - .Q(storage_data2[4]), - .R(1'b0)); - FDRE \storage_data2_reg[5] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[5]), - .Q(storage_data2[5]), - .R(1'b0)); - FDRE \storage_data2_reg[6] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[6]), - .Q(storage_data2[6]), - .R(1'b0)); - FDRE \storage_data2_reg[7] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[7]), - .Q(storage_data2[7]), - .R(1'b0)); - FDRE \storage_data2_reg[8] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[8]), - .Q(storage_data2[8]), - .R(1'b0)); - FDRE \storage_data2_reg[9] - (.C(aclk), - .CE(storage_data2_0), - .D(s_axis_tdata[9]), - .Q(storage_data2[9]), - .R(1'b0)); -endmodule -`ifndef GLBL -`define GLBL -`timescale 1 ps / 1 ps - -module glbl (); - - parameter ROC_WIDTH = 100000; - parameter TOC_WIDTH = 0; - parameter GRES_WIDTH = 10000; - parameter GRES_START = 10000; - -//-------- STARTUP Globals -------------- - wire GSR; - wire GTS; - wire GWE; - wire PRLD; - wire GRESTORE; - tri1 p_up_tmp; - tri (weak1, strong0) PLL_LOCKG = p_up_tmp; - - wire PROGB_GLBL; - wire CCLKO_GLBL; - wire FCSBO_GLBL; - wire [3:0] DO_GLBL; - wire [3:0] DI_GLBL; - - reg GSR_int; - reg GTS_int; - reg PRLD_int; - reg GRESTORE_int; - -//-------- JTAG Globals -------------- - wire JTAG_TDO_GLBL; - wire JTAG_TCK_GLBL; - wire JTAG_TDI_GLBL; - wire JTAG_TMS_GLBL; - wire JTAG_TRST_GLBL; - - reg JTAG_CAPTURE_GLBL; - reg JTAG_RESET_GLBL; - reg JTAG_SHIFT_GLBL; - reg JTAG_UPDATE_GLBL; - reg JTAG_RUNTEST_GLBL; - - reg JTAG_SEL1_GLBL = 0; - reg JTAG_SEL2_GLBL = 0 ; - reg JTAG_SEL3_GLBL = 0; - reg JTAG_SEL4_GLBL = 0; - - reg JTAG_USER_TDO1_GLBL = 1'bz; - reg JTAG_USER_TDO2_GLBL = 1'bz; - reg JTAG_USER_TDO3_GLBL = 1'bz; - reg JTAG_USER_TDO4_GLBL = 1'bz; - - assign (strong1, weak0) GSR = GSR_int; - assign (strong1, weak0) GTS = GTS_int; - assign (weak1, weak0) PRLD = PRLD_int; - assign (strong1, weak0) GRESTORE = GRESTORE_int; - - initial begin - GSR_int = 1'b1; - PRLD_int = 1'b1; - #(ROC_WIDTH) - GSR_int = 1'b0; - PRLD_int = 1'b0; - end - - initial begin - GTS_int = 1'b1; - #(TOC_WIDTH) - GTS_int = 1'b0; - end - - initial begin - GRESTORE_int = 1'b0; - #(GRES_START); - GRESTORE_int = 1'b1; - #(GRES_WIDTH); - GRESTORE_int = 1'b0; - end - -endmodule -`endif diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl deleted file mode 100644 index 63fbf37..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl +++ /dev/null @@ -1,1366 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 --- Date : Thu Apr 23 10:08:04 2026 --- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS --- Command : write_vhdl -force -mode funcsim -rename_top axis_register_slice_32 -prefix --- axis_register_slice_32_ axis_register_slice_32_sim_netlist.vhdl --- Design : axis_register_slice_32 --- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or --- synthesized. This netlist cannot be used for SDF annotated simulation. --- Device : xczu19eg-ffvc1760-2-i --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice is - port ( - s_axis_tready : out STD_LOGIC; - Q : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - aclk : in STD_LOGIC; - m_axis_tready : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - areset_r : in STD_LOGIC - ); -end axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice; - -architecture STRUCTURE of axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice is - signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; - signal \aresetn_d_reg_n_0_[1]\ : STD_LOGIC; - signal p_0_in : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal p_1_out : STD_LOGIC_VECTOR ( 0 to 0 ); - signal \^s_axis_tready\ : STD_LOGIC; - signal s_ready_i0 : STD_LOGIC; - signal s_ready_i_i_1_n_0 : STD_LOGIC; - signal s_ready_i_i_2_n_0 : STD_LOGIC; - signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); - signal \state[0]_i_1_n_0\ : STD_LOGIC; - signal \state[0]_i_2_n_0\ : STD_LOGIC; - signal \state_reg_n_0_[1]\ : STD_LOGIC; - signal storage_data1 : STD_LOGIC; - signal storage_data2 : STD_LOGIC_VECTOR ( 31 downto 0 ); - signal storage_data2_0 : STD_LOGIC; - attribute equivalent_register_removal : string; - attribute equivalent_register_removal of \aresetn_d_reg[0]\ : label is "no"; - attribute equivalent_register_removal of \aresetn_d_reg[1]\ : label is "no"; - attribute FSM_ENCODING : string; - attribute FSM_ENCODING of \state_reg[0]\ : label is "none"; - attribute FSM_ENCODING of \state_reg[1]\ : label is "none"; -begin - Q(0) <= \^q\(0); - s_axis_tready <= \^s_axis_tready\; -\__2/i_\: unisim.vcomponents.LUT4 - generic map( - INIT => X"E420" - ) - port map ( - I0 => \state_reg_n_0_[1]\, - I1 => \^q\(0), - I2 => s_axis_tvalid, - I3 => m_axis_tready, - O => storage_data1 - ); -\aresetn_d[0]_i_1\: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => areset_r, - O => p_1_out(0) - ); -\aresetn_d_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => p_1_out(0), - Q => \aresetn_d_reg_n_0_[0]\, - R => '0' - ); -\aresetn_d_reg[1]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => \aresetn_d_reg_n_0_[0]\, - Q => \aresetn_d_reg_n_0_[1]\, - R => '0' - ); -s_ready_i_i_1: unisim.vcomponents.LUT6 - generic map( - INIT => X"00000000E2E2EEE2" - ) - port map ( - I0 => \^s_axis_tready\, - I1 => s_ready_i_i_2_n_0, - I2 => s_ready_i0, - I3 => m_axis_tready, - I4 => \state_reg_n_0_[1]\, - I5 => areset_r, - O => s_ready_i_i_1_n_0 - ); -s_ready_i_i_2: unisim.vcomponents.LUT6 - generic map( - INIT => X"2808FFFF00000000" - ) - port map ( - I0 => \^q\(0), - I1 => m_axis_tready, - I2 => \state_reg_n_0_[1]\, - I3 => s_axis_tvalid, - I4 => \aresetn_d_reg_n_0_[1]\, - I5 => \aresetn_d_reg_n_0_[0]\, - O => s_ready_i_i_2_n_0 - ); -s_ready_i_i_3: unisim.vcomponents.LUT2 - generic map( - INIT => X"2" - ) - port map ( - I0 => \aresetn_d_reg_n_0_[0]\, - I1 => \aresetn_d_reg_n_0_[1]\, - O => s_ready_i0 - ); -s_ready_i_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => s_ready_i_i_1_n_0, - Q => \^s_axis_tready\, - R => '0' - ); -\state[0]_i_1\: unisim.vcomponents.LUT3 - generic map( - INIT => X"BA" - ) - port map ( - I0 => areset_r, - I1 => \aresetn_d_reg_n_0_[1]\, - I2 => \aresetn_d_reg_n_0_[0]\, - O => \state[0]_i_1_n_0\ - ); -\state[0]_i_2\: unisim.vcomponents.LUT5 - generic map( - INIT => X"2A808A8A" - ) - port map ( - I0 => \aresetn_d_reg_n_0_[0]\, - I1 => m_axis_tready, - I2 => \^q\(0), - I3 => s_axis_tvalid, - I4 => \state_reg_n_0_[1]\, - O => \state[0]_i_2_n_0\ - ); -\state[0]_i_3\: unisim.vcomponents.LUT4 - generic map( - INIT => X"7808" - ) - port map ( - I0 => m_axis_tready, - I1 => \^q\(0), - I2 => \state_reg_n_0_[1]\, - I3 => s_axis_tvalid, - O => state(0) - ); -\state[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"FD2D" - ) - port map ( - I0 => \state_reg_n_0_[1]\, - I1 => s_axis_tvalid, - I2 => \^q\(0), - I3 => m_axis_tready, - O => state(1) - ); -\state_reg[0]\: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => \state[0]_i_2_n_0\, - D => state(0), - Q => \^q\(0), - R => \state[0]_i_1_n_0\ - ); -\state_reg[1]\: unisim.vcomponents.FDSE - generic map( - INIT => '1' - ) - port map ( - C => aclk, - CE => \state[0]_i_2_n_0\, - D => state(1), - Q => \state_reg_n_0_[1]\, - S => \state[0]_i_1_n_0\ - ); -\storage_data1[0]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(0), - I1 => s_axis_tdata(0), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(0) - ); -\storage_data1[10]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(10), - I1 => s_axis_tdata(10), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(10) - ); -\storage_data1[11]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(11), - I1 => s_axis_tdata(11), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(11) - ); -\storage_data1[12]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(12), - I1 => s_axis_tdata(12), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(12) - ); -\storage_data1[13]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(13), - I1 => s_axis_tdata(13), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(13) - ); -\storage_data1[14]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(14), - I1 => s_axis_tdata(14), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(14) - ); -\storage_data1[15]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(15), - I1 => s_axis_tdata(15), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(15) - ); -\storage_data1[16]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(16), - I1 => s_axis_tdata(16), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(16) - ); -\storage_data1[17]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(17), - I1 => s_axis_tdata(17), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(17) - ); -\storage_data1[18]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(18), - I1 => s_axis_tdata(18), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(18) - ); -\storage_data1[19]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(19), - I1 => s_axis_tdata(19), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(19) - ); -\storage_data1[1]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(1), - I1 => s_axis_tdata(1), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(1) - ); -\storage_data1[20]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(20), - I1 => s_axis_tdata(20), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(20) - ); -\storage_data1[21]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(21), - I1 => s_axis_tdata(21), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(21) - ); -\storage_data1[22]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(22), - I1 => s_axis_tdata(22), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(22) - ); -\storage_data1[23]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(23), - I1 => s_axis_tdata(23), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(23) - ); -\storage_data1[24]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(24), - I1 => s_axis_tdata(24), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(24) - ); -\storage_data1[25]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(25), - I1 => s_axis_tdata(25), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(25) - ); -\storage_data1[26]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(26), - I1 => s_axis_tdata(26), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(26) - ); -\storage_data1[27]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(27), - I1 => s_axis_tdata(27), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(27) - ); -\storage_data1[28]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(28), - I1 => s_axis_tdata(28), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(28) - ); -\storage_data1[29]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(29), - I1 => s_axis_tdata(29), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(29) - ); -\storage_data1[2]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(2), - I1 => s_axis_tdata(2), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(2) - ); -\storage_data1[30]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(30), - I1 => s_axis_tdata(30), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(30) - ); -\storage_data1[31]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(31), - I1 => s_axis_tdata(31), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(31) - ); -\storage_data1[3]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(3), - I1 => s_axis_tdata(3), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(3) - ); -\storage_data1[4]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(4), - I1 => s_axis_tdata(4), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(4) - ); -\storage_data1[5]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(5), - I1 => s_axis_tdata(5), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(5) - ); -\storage_data1[6]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(6), - I1 => s_axis_tdata(6), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(6) - ); -\storage_data1[7]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(7), - I1 => s_axis_tdata(7), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(7) - ); -\storage_data1[8]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(8), - I1 => s_axis_tdata(8), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(8) - ); -\storage_data1[9]_i_1\: unisim.vcomponents.LUT4 - generic map( - INIT => X"CCAC" - ) - port map ( - I0 => storage_data2(9), - I1 => s_axis_tdata(9), - I2 => \^q\(0), - I3 => \state_reg_n_0_[1]\, - O => p_0_in(9) - ); -\storage_data1_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(0), - Q => m_axis_tdata(0), - R => '0' - ); -\storage_data1_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(10), - Q => m_axis_tdata(10), - R => '0' - ); -\storage_data1_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(11), - Q => m_axis_tdata(11), - R => '0' - ); -\storage_data1_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(12), - Q => m_axis_tdata(12), - R => '0' - ); -\storage_data1_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(13), - Q => m_axis_tdata(13), - R => '0' - ); -\storage_data1_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(14), - Q => m_axis_tdata(14), - R => '0' - ); -\storage_data1_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(15), - Q => m_axis_tdata(15), - R => '0' - ); -\storage_data1_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(16), - Q => m_axis_tdata(16), - R => '0' - ); -\storage_data1_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(17), - Q => m_axis_tdata(17), - R => '0' - ); -\storage_data1_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(18), - Q => m_axis_tdata(18), - R => '0' - ); -\storage_data1_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(19), - Q => m_axis_tdata(19), - R => '0' - ); -\storage_data1_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(1), - Q => m_axis_tdata(1), - R => '0' - ); -\storage_data1_reg[20]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(20), - Q => m_axis_tdata(20), - R => '0' - ); -\storage_data1_reg[21]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(21), - Q => m_axis_tdata(21), - R => '0' - ); -\storage_data1_reg[22]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(22), - Q => m_axis_tdata(22), - R => '0' - ); -\storage_data1_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(23), - Q => m_axis_tdata(23), - R => '0' - ); -\storage_data1_reg[24]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(24), - Q => m_axis_tdata(24), - R => '0' - ); -\storage_data1_reg[25]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(25), - Q => m_axis_tdata(25), - R => '0' - ); -\storage_data1_reg[26]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(26), - Q => m_axis_tdata(26), - R => '0' - ); -\storage_data1_reg[27]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(27), - Q => m_axis_tdata(27), - R => '0' - ); -\storage_data1_reg[28]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(28), - Q => m_axis_tdata(28), - R => '0' - ); -\storage_data1_reg[29]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(29), - Q => m_axis_tdata(29), - R => '0' - ); -\storage_data1_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(2), - Q => m_axis_tdata(2), - R => '0' - ); -\storage_data1_reg[30]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(30), - Q => m_axis_tdata(30), - R => '0' - ); -\storage_data1_reg[31]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(31), - Q => m_axis_tdata(31), - R => '0' - ); -\storage_data1_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(3), - Q => m_axis_tdata(3), - R => '0' - ); -\storage_data1_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(4), - Q => m_axis_tdata(4), - R => '0' - ); -\storage_data1_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(5), - Q => m_axis_tdata(5), - R => '0' - ); -\storage_data1_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(6), - Q => m_axis_tdata(6), - R => '0' - ); -\storage_data1_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(7), - Q => m_axis_tdata(7), - R => '0' - ); -\storage_data1_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(8), - Q => m_axis_tdata(8), - R => '0' - ); -\storage_data1_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data1, - D => p_0_in(9), - Q => m_axis_tdata(9), - R => '0' - ); -\storage_data2[31]_i_1\: unisim.vcomponents.LUT2 - generic map( - INIT => X"8" - ) - port map ( - I0 => s_axis_tvalid, - I1 => \^s_axis_tready\, - O => storage_data2_0 - ); -\storage_data2_reg[0]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(0), - Q => storage_data2(0), - R => '0' - ); -\storage_data2_reg[10]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(10), - Q => storage_data2(10), - R => '0' - ); -\storage_data2_reg[11]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(11), - Q => storage_data2(11), - R => '0' - ); -\storage_data2_reg[12]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(12), - Q => storage_data2(12), - R => '0' - ); -\storage_data2_reg[13]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(13), - Q => storage_data2(13), - R => '0' - ); -\storage_data2_reg[14]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(14), - Q => storage_data2(14), - R => '0' - ); -\storage_data2_reg[15]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(15), - Q => storage_data2(15), - R => '0' - ); -\storage_data2_reg[16]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(16), - Q => storage_data2(16), - R => '0' - ); -\storage_data2_reg[17]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(17), - Q => storage_data2(17), - R => '0' - ); -\storage_data2_reg[18]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(18), - Q => storage_data2(18), - R => '0' - ); -\storage_data2_reg[19]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(19), - Q => storage_data2(19), - R => '0' - ); -\storage_data2_reg[1]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(1), - Q => storage_data2(1), - R => '0' - ); -\storage_data2_reg[20]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(20), - Q => storage_data2(20), - R => '0' - ); -\storage_data2_reg[21]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(21), - Q => storage_data2(21), - R => '0' - ); -\storage_data2_reg[22]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(22), - Q => storage_data2(22), - R => '0' - ); -\storage_data2_reg[23]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(23), - Q => storage_data2(23), - R => '0' - ); -\storage_data2_reg[24]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(24), - Q => storage_data2(24), - R => '0' - ); -\storage_data2_reg[25]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(25), - Q => storage_data2(25), - R => '0' - ); -\storage_data2_reg[26]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(26), - Q => storage_data2(26), - R => '0' - ); -\storage_data2_reg[27]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(27), - Q => storage_data2(27), - R => '0' - ); -\storage_data2_reg[28]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(28), - Q => storage_data2(28), - R => '0' - ); -\storage_data2_reg[29]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(29), - Q => storage_data2(29), - R => '0' - ); -\storage_data2_reg[2]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(2), - Q => storage_data2(2), - R => '0' - ); -\storage_data2_reg[30]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(30), - Q => storage_data2(30), - R => '0' - ); -\storage_data2_reg[31]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(31), - Q => storage_data2(31), - R => '0' - ); -\storage_data2_reg[3]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(3), - Q => storage_data2(3), - R => '0' - ); -\storage_data2_reg[4]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(4), - Q => storage_data2(4), - R => '0' - ); -\storage_data2_reg[5]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(5), - Q => storage_data2(5), - R => '0' - ); -\storage_data2_reg[6]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(6), - Q => storage_data2(6), - R => '0' - ); -\storage_data2_reg[7]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(7), - Q => storage_data2(7), - R => '0' - ); -\storage_data2_reg[8]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(8), - Q => storage_data2(8), - R => '0' - ); -\storage_data2_reg[9]\: unisim.vcomponents.FDRE - port map ( - C => aclk, - CE => storage_data2_0, - D => s_axis_tdata(9), - Q => storage_data2(9), - R => '0' - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice is - port ( - aclk : in STD_LOGIC; - aclk2x : in STD_LOGIC; - aresetn : in STD_LOGIC; - aclken : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 ); - s_axis_tlast : in STD_LOGIC; - s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 ); - s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 ); - m_axis_tlast : out STD_LOGIC; - m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 ); - m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ) - ); - attribute C_AXIS_SIGNAL_SET : integer; - attribute C_AXIS_SIGNAL_SET of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 3; - attribute C_AXIS_TDATA_WIDTH : integer; - attribute C_AXIS_TDATA_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 32; - attribute C_AXIS_TDEST_WIDTH : integer; - attribute C_AXIS_TDEST_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute C_AXIS_TID_WIDTH : integer; - attribute C_AXIS_TID_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute C_AXIS_TUSER_WIDTH : integer; - attribute C_AXIS_TUSER_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute C_FAMILY : string; - attribute C_FAMILY of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is "zynquplus"; - attribute C_NUM_SLR_CROSSINGS : integer; - attribute C_NUM_SLR_CROSSINGS of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_PIPELINES_MASTER : integer; - attribute C_PIPELINES_MASTER of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_PIPELINES_MIDDLE : integer; - attribute C_PIPELINES_MIDDLE of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_PIPELINES_SLAVE : integer; - attribute C_PIPELINES_SLAVE of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute C_REG_CONFIG : integer; - attribute C_REG_CONFIG of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 8; - attribute DowngradeIPIdentifiedWarnings : string; - attribute DowngradeIPIdentifiedWarnings of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is "yes"; - attribute G_INDX_SS_TDATA : integer; - attribute G_INDX_SS_TDATA of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute G_INDX_SS_TDEST : integer; - attribute G_INDX_SS_TDEST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 6; - attribute G_INDX_SS_TID : integer; - attribute G_INDX_SS_TID of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 5; - attribute G_INDX_SS_TKEEP : integer; - attribute G_INDX_SS_TKEEP of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 3; - attribute G_INDX_SS_TLAST : integer; - attribute G_INDX_SS_TLAST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 4; - attribute G_INDX_SS_TREADY : integer; - attribute G_INDX_SS_TREADY of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute G_INDX_SS_TSTRB : integer; - attribute G_INDX_SS_TSTRB of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 2; - attribute G_INDX_SS_TUSER : integer; - attribute G_INDX_SS_TUSER of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 7; - attribute G_MASK_SS_TDATA : integer; - attribute G_MASK_SS_TDATA of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 2; - attribute G_MASK_SS_TDEST : integer; - attribute G_MASK_SS_TDEST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 64; - attribute G_MASK_SS_TID : integer; - attribute G_MASK_SS_TID of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 32; - attribute G_MASK_SS_TKEEP : integer; - attribute G_MASK_SS_TKEEP of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 8; - attribute G_MASK_SS_TLAST : integer; - attribute G_MASK_SS_TLAST of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 16; - attribute G_MASK_SS_TREADY : integer; - attribute G_MASK_SS_TREADY of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute G_MASK_SS_TSTRB : integer; - attribute G_MASK_SS_TSTRB of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 4; - attribute G_MASK_SS_TUSER : integer; - attribute G_MASK_SS_TUSER of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 128; - attribute G_TASK_SEVERITY_ERR : integer; - attribute G_TASK_SEVERITY_ERR of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 2; - attribute G_TASK_SEVERITY_INFO : integer; - attribute G_TASK_SEVERITY_INFO of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 0; - attribute G_TASK_SEVERITY_WARNING : integer; - attribute G_TASK_SEVERITY_WARNING of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 1; - attribute P_TPAYLOAD_WIDTH : integer; - attribute P_TPAYLOAD_WIDTH of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice : entity is 32; -end axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice; - -architecture STRUCTURE of axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice is - signal \\ : STD_LOGIC; - signal areset_r : STD_LOGIC; - signal areset_r_i_1_n_0 : STD_LOGIC; -begin - m_axis_tdest(0) <= \\; - m_axis_tid(0) <= \\; - m_axis_tkeep(3) <= \\; - m_axis_tkeep(2) <= \\; - m_axis_tkeep(1) <= \\; - m_axis_tkeep(0) <= \\; - m_axis_tlast <= \\; - m_axis_tstrb(3) <= \\; - m_axis_tstrb(2) <= \\; - m_axis_tstrb(1) <= \\; - m_axis_tstrb(0) <= \\; - m_axis_tuser(0) <= \\; -GND: unisim.vcomponents.GND - port map ( - G => \\ - ); -areset_r_i_1: unisim.vcomponents.LUT1 - generic map( - INIT => X"1" - ) - port map ( - I0 => aresetn, - O => areset_r_i_1_n_0 - ); -areset_r_reg: unisim.vcomponents.FDRE - generic map( - INIT => '0' - ) - port map ( - C => aclk, - CE => '1', - D => areset_r_i_1_n_0, - Q => areset_r, - R => '0' - ); -axisc_register_slice_0: entity work.axis_register_slice_32_axis_register_slice_v1_1_29_axisc_register_slice - port map ( - Q(0) => m_axis_tvalid, - aclk => aclk, - areset_r => areset_r, - m_axis_tdata(31 downto 0) => m_axis_tdata(31 downto 0), - m_axis_tready => m_axis_tready, - s_axis_tdata(31 downto 0) => s_axis_tdata(31 downto 0), - s_axis_tready => s_axis_tready, - s_axis_tvalid => s_axis_tvalid - ); -end STRUCTURE; -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity axis_register_slice_32 is - port ( - aclk : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - attribute NotValidForBitStream : boolean; - attribute NotValidForBitStream of axis_register_slice_32 : entity is true; - attribute CHECK_LICENSE_TYPE : string; - attribute CHECK_LICENSE_TYPE of axis_register_slice_32 : entity is "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}"; - attribute DowngradeIPIdentifiedWarnings : string; - attribute DowngradeIPIdentifiedWarnings of axis_register_slice_32 : entity is "yes"; - attribute X_CORE_INFO : string; - attribute X_CORE_INFO of axis_register_slice_32 : entity is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2"; -end axis_register_slice_32; - -architecture STRUCTURE of axis_register_slice_32 is - signal NLW_inst_m_axis_tlast_UNCONNECTED : STD_LOGIC; - signal NLW_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - signal NLW_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); - signal NLW_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); - attribute C_AXIS_SIGNAL_SET : integer; - attribute C_AXIS_SIGNAL_SET of inst : label is 3; - attribute C_AXIS_TDATA_WIDTH : integer; - attribute C_AXIS_TDATA_WIDTH of inst : label is 32; - attribute C_AXIS_TDEST_WIDTH : integer; - attribute C_AXIS_TDEST_WIDTH of inst : label is 1; - attribute C_AXIS_TID_WIDTH : integer; - attribute C_AXIS_TID_WIDTH of inst : label is 1; - attribute C_AXIS_TUSER_WIDTH : integer; - attribute C_AXIS_TUSER_WIDTH of inst : label is 1; - attribute C_FAMILY : string; - attribute C_FAMILY of inst : label is "zynquplus"; - attribute C_NUM_SLR_CROSSINGS : integer; - attribute C_NUM_SLR_CROSSINGS of inst : label is 0; - attribute C_PIPELINES_MASTER : integer; - attribute C_PIPELINES_MASTER of inst : label is 0; - attribute C_PIPELINES_MIDDLE : integer; - attribute C_PIPELINES_MIDDLE of inst : label is 0; - attribute C_PIPELINES_SLAVE : integer; - attribute C_PIPELINES_SLAVE of inst : label is 0; - attribute C_REG_CONFIG : integer; - attribute C_REG_CONFIG of inst : label is 8; - attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; - attribute G_INDX_SS_TDATA : integer; - attribute G_INDX_SS_TDATA of inst : label is 1; - attribute G_INDX_SS_TDEST : integer; - attribute G_INDX_SS_TDEST of inst : label is 6; - attribute G_INDX_SS_TID : integer; - attribute G_INDX_SS_TID of inst : label is 5; - attribute G_INDX_SS_TKEEP : integer; - attribute G_INDX_SS_TKEEP of inst : label is 3; - attribute G_INDX_SS_TLAST : integer; - attribute G_INDX_SS_TLAST of inst : label is 4; - attribute G_INDX_SS_TREADY : integer; - attribute G_INDX_SS_TREADY of inst : label is 0; - attribute G_INDX_SS_TSTRB : integer; - attribute G_INDX_SS_TSTRB of inst : label is 2; - attribute G_INDX_SS_TUSER : integer; - attribute G_INDX_SS_TUSER of inst : label is 7; - attribute G_MASK_SS_TDATA : integer; - attribute G_MASK_SS_TDATA of inst : label is 2; - attribute G_MASK_SS_TDEST : integer; - attribute G_MASK_SS_TDEST of inst : label is 64; - attribute G_MASK_SS_TID : integer; - attribute G_MASK_SS_TID of inst : label is 32; - attribute G_MASK_SS_TKEEP : integer; - attribute G_MASK_SS_TKEEP of inst : label is 8; - attribute G_MASK_SS_TLAST : integer; - attribute G_MASK_SS_TLAST of inst : label is 16; - attribute G_MASK_SS_TREADY : integer; - attribute G_MASK_SS_TREADY of inst : label is 1; - attribute G_MASK_SS_TSTRB : integer; - attribute G_MASK_SS_TSTRB of inst : label is 4; - attribute G_MASK_SS_TUSER : integer; - attribute G_MASK_SS_TUSER of inst : label is 128; - attribute G_TASK_SEVERITY_ERR : integer; - attribute G_TASK_SEVERITY_ERR of inst : label is 2; - attribute G_TASK_SEVERITY_INFO : integer; - attribute G_TASK_SEVERITY_INFO of inst : label is 0; - attribute G_TASK_SEVERITY_WARNING : integer; - attribute G_TASK_SEVERITY_WARNING of inst : label is 1; - attribute P_TPAYLOAD_WIDTH : integer; - attribute P_TPAYLOAD_WIDTH of inst : label is 32; - attribute X_INTERFACE_INFO : string; - attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK"; - attribute X_INTERFACE_PARAMETER : string; - attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST"; - attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY"; - attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID"; - attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY"; - attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID"; - attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA"; - attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; - attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA"; - attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0"; -begin -inst: entity work.axis_register_slice_32_axis_register_slice_v1_1_29_axis_register_slice - port map ( - aclk => aclk, - aclk2x => '0', - aclken => '1', - aresetn => aresetn, - m_axis_tdata(31 downto 0) => m_axis_tdata(31 downto 0), - m_axis_tdest(0) => NLW_inst_m_axis_tdest_UNCONNECTED(0), - m_axis_tid(0) => NLW_inst_m_axis_tid_UNCONNECTED(0), - m_axis_tkeep(3 downto 0) => NLW_inst_m_axis_tkeep_UNCONNECTED(3 downto 0), - m_axis_tlast => NLW_inst_m_axis_tlast_UNCONNECTED, - m_axis_tready => m_axis_tready, - m_axis_tstrb(3 downto 0) => NLW_inst_m_axis_tstrb_UNCONNECTED(3 downto 0), - m_axis_tuser(0) => NLW_inst_m_axis_tuser_UNCONNECTED(0), - m_axis_tvalid => m_axis_tvalid, - s_axis_tdata(31 downto 0) => s_axis_tdata(31 downto 0), - s_axis_tdest(0) => '0', - s_axis_tid(0) => '0', - s_axis_tkeep(3 downto 0) => B"1111", - s_axis_tlast => '1', - s_axis_tready => s_axis_tready, - s_axis_tstrb(3 downto 0) => B"1111", - s_axis_tuser(0) => '0', - s_axis_tvalid => s_axis_tvalid - ); -end STRUCTURE; diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v deleted file mode 100644 index a8ddc84..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -// Date : Thu Apr 23 10:08:03 2026 -// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS -// Command : write_verilog -force -mode synth_stub -rename_top axis_register_slice_32 -prefix -// axis_register_slice_32_ axis_register_slice_32_stub.v -// Design : axis_register_slice_32 -// Purpose : Stub declaration of top-level module interface -// Device : xczu19eg-ffvc1760-2-i -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *) -module axis_register_slice_32(aclk, aresetn, s_axis_tvalid, s_axis_tready, - s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata) -/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]" */ -/* synthesis syn_force_seq_prim="aclk" */; - input aclk /* synthesis syn_isclock = 1 */; - input aresetn; - input s_axis_tvalid; - output s_axis_tready; - input [31:0]s_axis_tdata; - output m_axis_tvalid; - input m_axis_tready; - output [31:0]m_axis_tdata; -endmodule diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl deleted file mode 100644 index cf52608..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl +++ /dev/null @@ -1,38 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 --- Date : Thu Apr 23 10:08:04 2026 --- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS --- Command : write_vhdl -force -mode synth_stub -rename_top axis_register_slice_32 -prefix --- axis_register_slice_32_ axis_register_slice_32_stub.vhdl --- Design : axis_register_slice_32 --- Purpose : Stub declaration of top-level module interface --- Device : xczu19eg-ffvc1760-2-i --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity axis_register_slice_32 is - Port ( - aclk : in STD_LOGIC; - aresetn : in STD_LOGIC; - s_axis_tvalid : in STD_LOGIC; - s_axis_tready : out STD_LOGIC; - s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); - m_axis_tvalid : out STD_LOGIC; - m_axis_tready : in STD_LOGIC; - m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) - ); - -end axis_register_slice_32; - -architecture stub of axis_register_slice_32 is -attribute syn_black_box : boolean; -attribute black_box_pad_pin : string; -attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]"; -attribute X_CORE_INFO : string; -attribute X_CORE_INFO of stub : architecture is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2"; -begin -end; diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh deleted file mode 100755 index 9be387b..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh +++ /dev/null @@ -1,336 +0,0 @@ -// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// Global Parameters: -// -// Functions: -// f_clogb2 -// f_gcd -// f_lcm -// f_get_tdata_indx -// f_get_tstrb_indx -// f_get_tkeep_indx -// f_get_tlast_indx -// f_get_tid_indx -// f_get_tdest_indx -// f_get_tuser_indx -// f_payload_width -// Tasks: -// t_display_tdata_error -//-------------------------------------------------------------------------- -/////////////////////////////////////////////////////////////////////////////// -// BEGIN Global Parameters -/////////////////////////////////////////////////////////////////////////////// -// Define Signal Set indices -localparam G_INDX_SS_TREADY = 0; -localparam G_INDX_SS_TDATA = 1; -localparam G_INDX_SS_TSTRB = 2; -localparam G_INDX_SS_TKEEP = 3; -localparam G_INDX_SS_TLAST = 4; -localparam G_INDX_SS_TID = 5; -localparam G_INDX_SS_TDEST = 6; -localparam G_INDX_SS_TUSER = 7; -localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY; -localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA; -localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB; -localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP; -localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST; -localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ; -localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST; -localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER; - -// Task DRC error levels -localparam G_TASK_SEVERITY_ERR = 2; -localparam G_TASK_SEVERITY_WARNING = 1; -localparam G_TASK_SEVERITY_INFO = 0; - -/////////////////////////////////////////////////////////////////////////////// -// BEGIN Functions -/////////////////////////////////////////////////////////////////////////////// -// ceiling logb2 - function integer f_clogb2 (input integer size); - integer s; - begin - s = size; - s = s - 1; - for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) - s = s >> 1; - end - endfunction // clogb2 - - // Calculates the Greatest Common Divisor between two integers using the - // euclidean algorithm. - function automatic integer f_gcd ( - input integer a, - input integer b - ); - begin : main - if (a == 0) begin - f_gcd = b; - end else if (b == 0) begin - f_gcd = a; - end else if (a > b) begin - f_gcd = f_gcd(a % b, b); - end else begin - f_gcd = f_gcd(a, b % a); - end - end - endfunction - - // Calculates the Lowest Common Denominator between two integers - function integer f_lcm ( - input integer a, - input integer b - ); - begin : main - f_lcm = ( a / f_gcd(a, b)) * b; - end - endfunction - - // Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tdata_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - f_get_tdata_indx = 0; - end - endfunction - - // Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tstrb_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST); - // If TDATA exists, then add its width to its base to get the tstrb index - f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx; - end - endfunction - - // Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tkeep_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST); - f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx; - end - endfunction - - // Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tlast_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST); - f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx; - end - endfunction - - // Returns back the index to the tid portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tid_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST); - f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx; - end - endfunction - - // Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tdest_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST); - f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx; - end - endfunction - - // Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the - // signal is not enabled. - function integer f_get_tuser_indx ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST); - f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx; - end - endfunction - - // Payload is the sum of all the AXIS signals present except for - // TREADY/TVALID - function integer f_payload_width ( - input integer DAW, // TDATA Width - input integer IDW, // TID Width - input integer DEW, // TDEST Width - input integer USW, // TUSER Width - input [31:0] SST // Signal Set - ); - begin : main - integer cur_indx; - cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST); - f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx; - // Ensure that the return value is never less than 1 - f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width; - end - endfunction - - task t_check_tdata_width( - input integer data_width, - input [8*80-1:0] var_name, - input [8*80-1:0] inst_name, - input integer severity_lvl, - output integer ret_val - ); - // Severity levels: - // 0 = INFO - // 1 = WARNING - // 2 = ERROR - begin : t_check_tdata_width - if (data_width%8 != 0) begin - // 000 1 2 3 4 5 6 7 8 - // 012 0 0 0 0 0 0 0 0 - if (severity_lvl >= 2) begin - $display("ERROR: %m::%s", inst_name); - end else if (severity_lvl == 1) begin - $display("WARNING: %m::%s", inst_name); - end else begin - $display("INFO: %m::%s", inst_name); - end - $display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width); - $display(" AXI4-Stream data width is only defined for byte multiples. See the "); - $display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more"); - $display(" information."); - ret_val = 1; - end else begin - ret_val = 0; - end - end - endtask - - task t_check_tuser_width( - input integer tuser_width, - input [8*80-1:0] tuser_name, - input integer tdata_width, - input [8*80-1:0] tdata_name, - input [8*80-1:0] inst_name, - input integer severity_lvl, - output integer ret_val - ); - // Severity levels: - // 0 = INFO - // 1 = WARNING - // 2 = ERROR - begin : t_check_tuser_width - integer tdata_bytes; - tdata_bytes = tdata_width/8; - if ((tuser_width%tdata_bytes) != 0) begin - // 000 1 2 3 4 5 6 7 8 - // 012 0 0 0 0 0 0 0 0 - if (severity_lvl >= 2) begin - $display("ERROR: %m::%s", inst_name); - end else if (severity_lvl == 1) begin - $display("WARNING: %m::%s", inst_name); - end else begin - $display("INFO: %m::%s", inst_name); - end - $display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width); - $display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width); - $display(" TUSER width in this module is only defined when the TUSER is the"); - $display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0"); - $display(" Section 2.1, 2.3.3 and 2.8 for more information. "); - ret_val = 1; - end else begin - ret_val = 0; - end - end - endtask - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v deleted file mode 100755 index 33ddf3c..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v +++ /dev/null @@ -1,1318 +0,0 @@ -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -//----------------------------------------------------------------------------- -// -// Description: -// Optimized Mux using MUXF7/8. -// Any mux ratio. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// mux_enc -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V -`define AXIS_INFRASTRUCTURE_V1_0_MUX_ENC_V -`timescale 1ps/1ps - - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_mux_enc # - ( - parameter C_FAMILY = "rtl", - // FPGA Family. Current version: virtex6 or spartan6. - parameter integer C_RATIO = 4, - // Mux select ratio. Can be any binary value (>= 1) - parameter integer C_SEL_WIDTH = 2, - // Log2-ceiling of C_RATIO (>= 1) - parameter integer C_DATA_WIDTH = 1 - // Data width for comparator (>= 1) - ) - ( - input wire [C_SEL_WIDTH-1:0] S, - input wire [C_RATIO*C_DATA_WIDTH-1:0] A, - output wire [C_DATA_WIDTH-1:0] O, - input wire OE - ); - - wire [C_DATA_WIDTH-1:0] o_i; - genvar bit_cnt; - - function [C_DATA_WIDTH-1:0] f_mux - ( - input [C_SEL_WIDTH-1:0] s, - input [C_RATIO*C_DATA_WIDTH-1:0] a - ); - integer i; - reg [C_RATIO*C_DATA_WIDTH-1:0] carry; - begin - carry[C_DATA_WIDTH-1:0] = {C_DATA_WIDTH{(s==0)?1'b1:1'b0}} & a[C_DATA_WIDTH-1:0]; - for (i=1;i 17, use RTL - assign o_i = f_mux(S, A); - endcase - end // gen_fpga - endgenerate -endmodule - -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_infrastructure_v1_1_1_util_aclken_converter -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V -`define AXIS_INFRASTRUCTURE_V1_0_UTIL_ACLKEN_CONVERTER_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_aclken_converter # ( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_PAYLOAD_WIDTH = 32, - parameter integer C_S_ACLKEN_CAN_TOGGLE = 1, - parameter integer C_M_ACLKEN_CAN_TOGGLE = 1 - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // Slave side - input wire ACLK, - input wire ARESETN, - - input wire S_ACLKEN, - input wire [C_PAYLOAD_WIDTH-1:0] S_PAYLOAD, - input wire S_VALID, - output wire S_READY, - - // Master side - input wire M_ACLKEN, - output wire [C_PAYLOAD_WIDTH-1:0] M_PAYLOAD, - output wire M_VALID, - input wire M_READY -); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - -// State machine states -localparam SM_NOT_READY = 3'b000; -localparam SM_EMPTY = 3'b001; -localparam SM_R0_NOT_READY = 3'b010; -localparam SM_R0 = 3'b011; -localparam SM_R1 = 3'b100; -localparam SM_FULL = 3'b110; - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -wire s_aclken_i; -wire m_aclken_i; -reg areset; - -reg [2:0] state = SM_NOT_READY; - -// r0 is the output register -reg [C_PAYLOAD_WIDTH-1:0] r0; -wire load_r0; -wire load_r0_from_r1; - -// r1 is the overflow register -reg [C_PAYLOAD_WIDTH-1:0] r1; -wire load_r1; -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - -assign s_aclken_i = C_S_ACLKEN_CAN_TOGGLE ? S_ACLKEN : 1'b1; -assign m_aclken_i = C_M_ACLKEN_CAN_TOGGLE ? M_ACLKEN : 1'b1; - -always @(posedge ACLK) begin - areset <= ~ARESETN; -end - -// Valid/Ready outputs encoded into state machine. -assign S_READY = (state == SM_NOT_READY ) ? 1'b0 : state[0] ; -assign M_VALID = (state == SM_NOT_READY ) ? 1'b0 : state[1]; - -// State machine: Controls outputs and hold register state info -always @(posedge ACLK) begin - if (areset) begin - state <= SM_NOT_READY; - end - else begin - case (state) - // De-assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied - SM_NOT_READY: begin - if (s_aclken_i) begin - state <= SM_EMPTY; - end - else begin - state <= state; - end - end - - // Assert s_ready, de-assert m_valid, R0 unoccupied, R1 unoccupied - SM_EMPTY: begin - if (s_aclken_i & S_VALID & m_aclken_i) begin - state <= SM_R0; - end - else if (s_aclken_i & S_VALID & ~m_aclken_i) begin - state <= SM_R1; - end - else begin - state <= state; - end - end - - // Assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied - SM_R0: begin - if ((m_aclken_i & M_READY) & ~(s_aclken_i & S_VALID)) begin - state <= SM_EMPTY; - end - else if (~(m_aclken_i & M_READY) & (s_aclken_i & S_VALID)) begin - state <= SM_FULL; - end - else begin - state <= state; - end - end - - // De-assert s_ready, Assert m_valid, R0 occupied, R1 unoccupied - SM_R0_NOT_READY: begin - if (s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_EMPTY; - end - else if (~s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_NOT_READY; - end - else if (s_aclken_i) begin - state <= SM_R0; - end - else begin - state <= state; - end - end - - // De-assert s_ready, De-assert m_valid, R0 unoccupied, R1 occupied - SM_R1: begin - if (~s_aclken_i & m_aclken_i) begin - state <= SM_R0_NOT_READY; - end - else if (s_aclken_i & m_aclken_i) begin - state <= SM_R0; - end - else begin - state <= state; - end - end - - // De-assert s_ready, De-assert m_valid, R0 occupied, R1 occupied - SM_FULL: begin - if (~s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_R0_NOT_READY; - end - else if (s_aclken_i & m_aclken_i & M_READY) begin - state <= SM_R0; - end - else begin - state <= state; - end - end - - default: begin - state <= SM_NOT_READY; - end - endcase - end -end - -assign M_PAYLOAD = r0; - -always @(posedge ACLK) begin - if (m_aclken_i) begin - r0 <= ~load_r0 ? r0 : - load_r0_from_r1 ? r1 : - S_PAYLOAD ; - end -end - -assign load_r0 = (state == SM_EMPTY) - | (state == SM_R1) - | ((state == SM_R0) & M_READY) - | ((state == SM_FULL) & M_READY); - -assign load_r0_from_r1 = (state == SM_R1) | (state == SM_FULL); - -always @(posedge ACLK) begin - r1 <= ~load_r1 ? r1 : S_PAYLOAD; -end - -assign load_r1 = (state == SM_EMPTY) | (state == SM_R0); - - -endmodule // axis_infrastructure_v1_1_1_util_aclken_converter - -`default_nettype wire -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Verilog-standard: Verilog 2001 -//////////////////////////////////////////////////////////// -// -// Structure: -// axis_infrastructure_v1_1_1_util_aclken_converter_wrapper -// axis_infrastructure_v1_1_1_util_axis2_vector -// axis_infrastructure_v1_1_1_util_aclken_converter -// axis_infrastructure_v1_1_1_util_vector2axis -// -//////////////////////////////////////////////////////////// -`ifndef axis_infrastructure_v1_1_1_UTIL_ACLKEN_CONVERTER_WRAPPER_V -`define axis_infrastructure_v1_1_1_UTIL_ACLKEN_CONVERTER_WRAPPER_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_aclken_converter_wrapper # ( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_TDATA_WIDTH = 32, - parameter integer C_TID_WIDTH = 1, - parameter integer C_TDEST_WIDTH = 1, - parameter integer C_TUSER_WIDTH = 1, - parameter [31:0] C_SIGNAL_SET = 32'hFF, - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - parameter integer C_S_ACLKEN_CAN_TOGGLE = 1, - parameter integer C_M_ACLKEN_CAN_TOGGLE = 1 - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // Slave side - input wire ACLK, - input wire ARESETN, - input wire S_ACLKEN, - input wire S_VALID, - output wire S_READY, - input wire [C_TDATA_WIDTH-1:0] S_TDATA, - input wire [C_TDATA_WIDTH/8-1:0] S_TSTRB, - input wire [C_TDATA_WIDTH/8-1:0] S_TKEEP, - input wire S_TLAST, - input wire [C_TID_WIDTH-1:0] S_TID, - input wire [C_TDEST_WIDTH-1:0] S_TDEST, - input wire [C_TUSER_WIDTH-1:0] S_TUSER, - - input wire M_ACLKEN, - output wire M_VALID, - input wire M_READY, - output wire [C_TDATA_WIDTH-1:0] M_TDATA, - output wire [C_TDATA_WIDTH/8-1:0] M_TSTRB, - output wire [C_TDATA_WIDTH/8-1:0] M_TKEEP, - output wire M_TLAST, - output wire [C_TID_WIDTH-1:0] M_TID, - output wire [C_TDEST_WIDTH-1:0] M_TDEST, - output wire [C_TUSER_WIDTH-1:0] M_TUSER -); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - -localparam integer P_TPAYLOAD_WIDTH = f_payload_width(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -wire [P_TPAYLOAD_WIDTH-1:0] s_tpayload; -wire [P_TPAYLOAD_WIDTH-1:0] m_tpayload; - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - -axis_infrastructure_v1_1_1_util_axis2vector #( - .C_TDATA_WIDTH ( C_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_SIGNAL_SET ) -) -util_axis2vector_0 ( - .TDATA ( S_TDATA ) , - .TSTRB ( S_TSTRB ) , - .TKEEP ( S_TKEEP ) , - .TLAST ( S_TLAST ) , - .TID ( S_TID ) , - .TDEST ( S_TDEST ) , - .TUSER ( S_TUSER ) , - .TPAYLOAD ( s_tpayload ) -); - -generate -if (C_S_ACLKEN_CAN_TOGGLE | C_M_ACLKEN_CAN_TOGGLE) begin : gen_aclken_converter - axis_infrastructure_v1_1_1_util_aclken_converter #( - .C_PAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_S_ACLKEN_CAN_TOGGLE ( C_S_ACLKEN_CAN_TOGGLE ) , - .C_M_ACLKEN_CAN_TOGGLE ( C_M_ACLKEN_CAN_TOGGLE ) - ) - s_util_aclken_converter_0 ( - .ACLK ( ACLK ) , - .ARESETN ( ARESETN ) , - .S_ACLKEN ( S_ACLKEN ) , - .S_PAYLOAD ( s_tpayload ) , - .S_VALID ( S_VALID ) , - .S_READY ( S_READY ) , - .M_ACLKEN ( M_ACLKEN ) , - .M_PAYLOAD ( m_tpayload ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); -end -else begin : gen_aclken_passthru - assign m_tpayload = s_tpayload; - assign M_VALID = S_VALID; - assign S_READY = M_READY; -end -endgenerate - -axis_infrastructure_v1_1_1_util_vector2axis #( - .C_TDATA_WIDTH ( C_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_SIGNAL_SET ) -) -util_vector2axis_0 ( - .TPAYLOAD ( m_tpayload ) , - .TDATA ( M_TDATA ) , - .TSTRB ( M_TSTRB ) , - .TKEEP ( M_TKEEP ) , - .TLAST ( M_TLAST ) , - .TID ( M_TID ) , - .TDEST ( M_TDEST ) , - .TUSER ( M_TUSER ) -); - -endmodule // axis_infrastructure_v1_1_1_util_aclken_converter_wrapper - -`default_nettype wire -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// axis to vector -// A generic module to merge all axis 'data' signals into one signal called payload. -// This is strictly wires, so no clk, reset, aclken, valid/ready are required. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_infrastructure_v1_1_1_util_axis2vector -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V -`define AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_axis2vector # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_TDATA_WIDTH = 32, - parameter integer C_TID_WIDTH = 1, - parameter integer C_TDEST_WIDTH = 1, - parameter integer C_TUSER_WIDTH = 1, - parameter integer C_TPAYLOAD_WIDTH = 44, - parameter [31:0] C_SIGNAL_SET = 32'hFF - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // inputs - input wire [C_TDATA_WIDTH-1:0] TDATA, - input wire [C_TDATA_WIDTH/8-1:0] TSTRB, - input wire [C_TDATA_WIDTH/8-1:0] TKEEP, - input wire TLAST, - input wire [C_TID_WIDTH-1:0] TID, - input wire [C_TDEST_WIDTH-1:0] TDEST, - input wire [C_TUSER_WIDTH-1:0] TUSER, - - // outputs - output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD - ); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// -localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// -generate - if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata - assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] = TDATA; - end else begin : no_gen_tdata - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb - assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB; - end else begin : no_gen_tstrb - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep - assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP; - end else begin : no_gen_tkeep - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast - assign TPAYLOAD[P_TLAST_INDX+:1] = TLAST; - end else begin : no_gen_tlast - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid - assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] = TID; - end else begin : no_gen_tid - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest - assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] = TDEST; - end else begin : no_gen_tdest - // Do nothing - end - if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser - assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] = TUSER; - end else begin : no_gen_tuser - // Do nothing - end -endgenerate -endmodule - -`default_nettype wire -`endif - - -// (c) Copyright 2012-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// axis to vector -// A generic module to unmerge all axis 'data' signals from payload. -// This is strictly wires, so no clk, reset, aclken, valid/ready are required. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_infrastructure_v1_1_1_util_vector2axis -// -//-------------------------------------------------------------------------- -`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V -`define AXIS_INFRASTRUCTURE_V1_0_UTIL_VECTOR2AXIS_V - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_util_vector2axis # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_TDATA_WIDTH = 32, - parameter integer C_TID_WIDTH = 1, - parameter integer C_TDEST_WIDTH = 1, - parameter integer C_TUSER_WIDTH = 1, - parameter integer C_TPAYLOAD_WIDTH = 44, - parameter [31:0] C_SIGNAL_SET = 32'hFF - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // outputs - input wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD, - - // inputs - output wire [C_TDATA_WIDTH-1:0] TDATA, - output wire [C_TDATA_WIDTH/8-1:0] TSTRB, - output wire [C_TDATA_WIDTH/8-1:0] TKEEP, - output wire TLAST, - output wire [C_TID_WIDTH-1:0] TID, - output wire [C_TDEST_WIDTH-1:0] TDEST, - output wire [C_TUSER_WIDTH-1:0] TUSER - ); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// -localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH, - C_TDEST_WIDTH, C_TUSER_WIDTH, - C_SIGNAL_SET); -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// -generate - if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata - assign TDATA = TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] ; - end - else begin : no_gen_tdata - assign TDATA = {C_TDATA_WIDTH{1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb - assign TSTRB = TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8]; - end - else begin : no_gen_tstrb - assign TSTRB = {(C_TDATA_WIDTH/8){1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep - assign TKEEP = TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8]; - end - else begin : no_gen_tkeep - assign TKEEP = {(C_TDATA_WIDTH/8){1'b1}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast - assign TLAST = TPAYLOAD[P_TLAST_INDX+:1] ; - end - else begin : no_gen_tlast - assign TLAST = 1'b0; - end - if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid - assign TID = TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] ; - end - else begin : no_gen_tid - assign TID = {C_TID_WIDTH{1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest - assign TDEST = TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] ; - end - else begin : no_gen_tdest - assign TDEST = {C_TDEST_WIDTH{1'b0}}; - end - if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser - assign TUSER = TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] ; - end - else begin : no_gen_tuser - assign TUSER = {C_TUSER_WIDTH{1'b0}}; - end -endgenerate -endmodule - -`default_nettype wire -`endif - - -// (c) Copyright 2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -//***************************************************************************** -// Description -// This module instantiates the clock synchronization logic. It passes the -// incoming signal through two flops to ensure metastability. -// -//***************************************************************************** -`timescale 1ps / 1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_infrastructure_v1_1_1_clock_synchronizer # ( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_NUM_STAGES = 4 -) -( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - input wire clk, - input wire synch_in , - output wire synch_out -); - -//////////////////////////////////////////////////////////////////////////////// -// Local Parameters -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -xpm_cdc_single #( - .DEST_SYNC_FF ( C_NUM_STAGES ) , - .SRC_INPUT_REG ( 0 ) , - .SIM_ASSERT_CHK ( 0 ) -) -inst_xpm_cdc_single ( - .src_clk ( 1'b0 ) , - .src_in ( synch_in ) , - .dest_out ( synch_out ) , - .dest_clk ( clk ) -); - -endmodule - -`default_nettype wire - - -// (c) Copyright 2014, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -/////////////////////////////////////////////////////////////////////////////// -// -// File name: axis_infrastructure_v1_1_1_cdc_handshake -// -/////////////////////////////////////////////////////////////////////////////// -`timescale 1ps/1ps -`default_nettype none - -module axis_infrastructure_v1_1_1_cdc_handshake # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter integer C_WIDTH = 32, - parameter integer C_NUM_SYNCHRONIZER_STAGES = 2 -) -( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - input wire from_clk, - input wire req, - output wire ack, - input wire [C_WIDTH-1:0] data_in, - - input wire to_clk, - output wire data_valid, - output wire [C_WIDTH-1:0] data_out -); - -///////////////////////////////////////////////////////////////////////////// -// Functions -///////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -/////////////////////////////////////////////////////////////////////////////// -xpm_cdc_handshake #( - .WIDTH ( C_WIDTH ) , - .DEST_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) , - .SRC_SYNC_FF ( C_NUM_SYNCHRONIZER_STAGES ) , - .DEST_EXT_HSK ( 0 ) , - .SIM_ASSERT_CHK ( 0 ) -) -inst_xpm_cdc_handshake ( - .src_in ( data_in ) , - .src_send ( req ) , - .src_rcv ( ack ) , - .src_clk ( from_clk ) , - .dest_out ( data_out ) , - .dest_req ( data_valid ) , - .dest_ack ( 1'b0 ) , - .dest_clk ( to_clk ) -); - -endmodule // axis_infrastructure_v1_1_1_cdc_handshake - -`default_nettype wire - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_register_slice_v1_1_vl_rfs.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_register_slice_v1_1_vl_rfs.v deleted file mode 100755 index ebea64a..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_register_slice_v1_1_vl_rfs.v +++ /dev/null @@ -1,2998 +0,0 @@ -// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps -`default_nettype none - -module axis_register_slice_v1_1_29_tdm_sample ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - input wire slow_clk, - input wire fast_clk, - output wire sample_cycle -); - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -reg slow_clk_div2 = 1'b0; -reg posedge_finder_first; -reg posedge_finder_second; -wire first_edge; -wire second_edge; -reg sample_cycle_d; -(* shreg_extract = "no" *) reg sample_cycle_r; - - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - always @(posedge slow_clk) begin - slow_clk_div2 <= ~slow_clk_div2; - end - - // Find matching rising edges by clocking slow_clk_div2 onto faster clock - always @(posedge fast_clk) begin - posedge_finder_first <= slow_clk_div2; - end - always @(posedge fast_clk) begin - posedge_finder_second <= ~slow_clk_div2; - end - - assign first_edge = slow_clk_div2 & ~posedge_finder_first; - assign second_edge = ~slow_clk_div2 & ~posedge_finder_second; - - always @(*) begin - sample_cycle_d = first_edge | second_edge; - end - - always @(posedge fast_clk) begin - sample_cycle_r <= sample_cycle_d; - end - - assign sample_cycle = sample_cycle_r; - -endmodule // tdm_sample - -`default_nettype wire - - -// (c) Copyright 2019, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - -module axis_register_slice_v1_1_29_test_master # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Master side - (* dont_touch="true" *) output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - (* dont_touch="true" *) output wire M_VALID, - input wire M_READY - ); - - //********************************************** - reg [C_DATA_WIDTH-1:0] payld_i = {C_DATA_WIDTH{1'b0}}; - reg tvalid_i = 1'b0; - - assign M_VALID = tvalid_i; - assign M_PAYLOAD_DATA = payld_i; - - always @(posedge ACLK) begin - if (ARESET) begin - tvalid_i <= 1'b0; - payld_i <= {C_DATA_WIDTH{1'b0}}; - end else if (ACLKEN) begin - if (M_READY && tvalid_i) begin - tvalid_i <= 1'b0; - payld_i <= {payld_i[C_DATA_WIDTH-2 : 0], ~payld_i[C_DATA_WIDTH-1]}; - end else begin - tvalid_i <= 1'b1; - end - end - end - -endmodule - -`default_nettype wire - - -// (c) Copyright 2019, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps - -module axis_register_slice_v1_1_29_test_slave # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - (* dont_touch="true" *) output wire S_READY - - ); - - reg valid_d = 1'b0; - reg [C_DATA_WIDTH-1:0] payld_i = {C_DATA_WIDTH{1'b0}}; - reg ready_i = 1'b0; - - assign S_READY = ready_i; - - always @(posedge ACLK) begin - if(ARESET) begin - ready_i <= 1'b0; - payld_i <= {C_DATA_WIDTH{1'b0}}; - end else if (ACLKEN) begin - valid_d <= S_VALID; - if (S_VALID & ready_i) begin - payld_i <= S_PAYLOAD_DATA; - ready_i <= 1'b0; - end else begin - payld_i <= payld_i>>1; - ready_i <= payld_i[0] ? valid_d : S_VALID; - end - end - end - -endmodule - - - -// (c) Copyright 2010-2018, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Register Slice -// Generic single-channel AXI pipeline register on forward and/or reverse signal path -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axic_register_slice_slr -// -//-------------------------------------------------------------------------- - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_multi_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_DATA_WIDTH = 32, - parameter integer C_NUM_SLR_CROSSINGS = 0, - parameter integer C_PIPELINES_MASTER = 0, - parameter integer C_PIPELINES_SLAVE = 0, - parameter integer C_PIPELINES_MIDDLE = 0 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - localparam integer P_MULTI_SLR = 15; - localparam integer P_FWD_MIDDLE_LATENCY = C_PIPELINES_MASTER + 2; - localparam integer P_FWD_MIDDLE2_LATENCY = C_PIPELINES_MASTER + 2 + C_PIPELINES_MIDDLE + 2; - localparam integer P_FWD_DEST_LATENCY = C_PIPELINES_MASTER + 2 + ((C_NUM_SLR_CROSSINGS>1) ? (C_PIPELINES_MIDDLE+2) : 0) + ((C_NUM_SLR_CROSSINGS==3) ? (C_PIPELINES_MIDDLE+2) : 0); - - generate - - if (C_NUM_SLR_CROSSINGS==0) begin : single_slr - - axis_register_slice_v1_1_29_single_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MASTER) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end else if (C_NUM_SLR_CROSSINGS==1) begin : dual_slr - - wire [C_DATA_WIDTH-1:0] src_payload; - wire src_handshake; - wire src_reset; - wire src_ready; - - axis_register_slice_v1_1_29_source_region_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES ( C_PIPELINES_MASTER) , - .C_REG_CONFIG ( P_MULTI_SLR ) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .laguna_m_reset_out ( src_reset ) , - .laguna_m_payload ( src_payload ) , - .laguna_m_handshake ( src_handshake ) , - .laguna_m_ready ( src_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( P_MULTI_SLR ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_SLAVE), - .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY) - ) - slr_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .laguna_s_reset_in ( src_reset ) , - .laguna_s_payload ( src_payload ) , - .laguna_s_handshake ( src_handshake ) , - .laguna_s_ready ( src_ready ) , - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end else if (C_NUM_SLR_CROSSINGS==2) begin : triple_slr - - wire [C_DATA_WIDTH-1:0] src_payload; - wire src_handshake; - wire src_ready; - wire src_reset; - wire [C_DATA_WIDTH-1:0] dest_payload; - wire dest_handshake; - wire dest_ready; - wire dest_reset; - - axis_register_slice_v1_1_29_source_region_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_MASTER) , - .C_REG_CONFIG ( P_MULTI_SLR ) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .laguna_m_reset_out ( src_reset ) , - .laguna_m_payload ( src_payload ) , - .laguna_m_handshake ( src_handshake ) , - .laguna_m_ready ( src_ready ) - ); - - axis_register_slice_v1_1_29_middle_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MIDDLE), - .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY) - ) - slr_middle ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .laguna_s_reset_in ( src_reset ) , - .laguna_s_payload ( src_payload ) , - .laguna_s_handshake ( src_handshake ) , - .laguna_s_ready ( src_ready ) , - .laguna_m_reset_out ( dest_reset ) , - .laguna_m_payload ( dest_payload ) , - .laguna_m_handshake ( dest_handshake ) , - .laguna_m_ready ( dest_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( P_MULTI_SLR ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_SLAVE), - .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY) - ) - slr_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .laguna_s_reset_in ( dest_reset ) , - .laguna_s_payload ( dest_payload ) , - .laguna_s_handshake ( dest_handshake ) , - .laguna_s_ready ( dest_ready ) , - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end else if (C_NUM_SLR_CROSSINGS==3) begin : quad_slr - - wire [C_DATA_WIDTH-1:0] src_payload; - wire src_handshake; - wire src_ready; - wire src_reset; - wire [C_DATA_WIDTH-1:0] mid_payload; - wire mid_handshake; - wire mid_ready; - wire mid_reset; - wire [C_DATA_WIDTH-1:0] dest_payload; - wire dest_handshake; - wire dest_ready; - wire dest_reset; - - axis_register_slice_v1_1_29_source_region_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_MASTER) , - .C_REG_CONFIG ( P_MULTI_SLR ) - ) - slr_master ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - .laguna_m_reset_out ( src_reset ) , - .laguna_m_payload ( src_payload ) , - .laguna_m_handshake ( src_handshake ) , - .laguna_m_ready ( src_ready ) - ); - - axis_register_slice_v1_1_29_middle_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MIDDLE), - .C_SOURCE_LATENCY (P_FWD_MIDDLE_LATENCY) - ) - slr_middle_master ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .laguna_s_reset_in ( src_reset ) , - .laguna_s_payload ( src_payload ) , - .laguna_s_handshake ( src_handshake ) , - .laguna_s_ready ( src_ready ) , - .laguna_m_reset_out ( mid_reset ) , - .laguna_m_payload ( mid_payload ) , - .laguna_m_handshake ( mid_handshake ) , - .laguna_m_ready ( mid_ready ) - ); - - axis_register_slice_v1_1_29_middle_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_PIPELINES (C_PIPELINES_MIDDLE), - .C_SOURCE_LATENCY (P_FWD_MIDDLE2_LATENCY) - ) - slr_middle_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - .laguna_s_reset_in ( mid_reset ) , - .laguna_s_payload ( mid_payload ) , - .laguna_s_handshake ( mid_handshake ) , - .laguna_s_ready ( mid_ready ) , - .laguna_m_reset_out ( dest_reset ) , - .laguna_m_payload ( dest_payload ) , - .laguna_m_handshake ( dest_handshake ) , - .laguna_m_ready ( dest_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( P_MULTI_SLR ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( C_DATA_WIDTH ), - .C_PIPELINES (C_PIPELINES_SLAVE), - .C_SOURCE_LATENCY (P_FWD_DEST_LATENCY) - ) - slr_slave ( - .ACLK ( ACLK ) , - .ACLKEN (ACLKEN) , - .ACLK2X (1'b0), - .ARESET (ARESET), - .laguna_s_reset_in ( dest_reset ) , - .laguna_s_payload ( dest_payload ) , - .laguna_s_handshake ( dest_handshake ) , - .laguna_s_ready ( dest_ready ) , - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .M_VALID (M_VALID), - .M_READY (M_READY) - ); - - end - -endgenerate -endmodule // multi_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_middle_region_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_DATA_WIDTH = 32, - parameter integer C_PIPELINES = 0, - parameter integer C_SOURCE_LATENCY = 1 - // Number of cycles to wait after laguna_s_ready output to enable shifting internal pipeline stages, to stay in sync with pipeline enables in source slr . - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire laguna_s_reset_in, - input wire [C_DATA_WIDTH-1:0] laguna_s_payload, - input wire laguna_s_handshake, - output wire laguna_s_ready, - - // Master side - output wire laguna_m_reset_out, - output wire [C_DATA_WIDTH-1:0] laguna_m_payload, - output wire laguna_m_handshake, - input wire laguna_m_ready - ); - - localparam integer P_PIPE_WIDTH = C_PIPELINES>0 ? C_PIPELINES : 1; - localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES; - - generate - - (* keep="true" *) reg s_reset_dd = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0; - - assign laguna_m_reset_out = laguna_m_reset_out_i; - - always @(posedge ACLK) begin - laguna_s_reset_in_d <= laguna_s_reset_in; - s_reset_dd <= laguna_s_reset_in_d; - laguna_m_reset_out_i <= C_PIPELINES==0 ? laguna_s_reset_in_d : s_reset_dd; - end - - wire ACLEAR; - assign ACLEAR = ARESET; - - if (1) begin : common - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d; - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i; - wire laguna_s_handshake_q; - wire m_handshake_d; - wire laguna_m_handshake_q; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+2)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+2)-1:0] handshake_i; - genvar p; - - assign laguna_m_payload = laguna_m_payload_i; - assign m_handshake_d = handshake_i[C_PIPELINES]; - assign laguna_m_handshake = laguna_m_handshake_q; - assign laguna_s_ready = laguna_s_ready_i; - - always @(posedge ACLK) begin - laguna_m_ready_d <= laguna_m_ready; - laguna_s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; - ready_d <= {ready_d, laguna_m_ready_d}; - end - - for (p=0; p<=(C_PIPELINES+1); p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - wire payload_valid_d; - wire payload_valid_q; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data; - assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q; - assign payload_valid_d = handshake_i[((p>0)?(p-1):0)]; - - always @(posedge ACLK) begin - if (p==0) begin - laguna_s_payload_d <= laguna_s_payload; - end else if (p==C_PIPELINES+1) begin - laguna_m_payload_i <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - FDCE #( - .INIT(1'b0) - ) payload_valid_asyncclear_inst ( - .Q (payload_valid_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (payload_valid_d) - ); - end // loop p - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_m_handshake_asyncclear_inst ( - .Q (laguna_m_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (m_handshake_d) - ); - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_s_handshake_asyncclear_inst ( - .Q (laguna_s_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (laguna_s_handshake) - ); - - end // gen_slr - endgenerate -endmodule // middle_region_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_source_region_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_REG_CONFIG = 12, - parameter integer C_PIPELINES = 0, - parameter integer C_DATA_WIDTH = 32, - parameter integer C_SLR_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLK2X, - input wire ARESET, - input wire ACLKEN, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire laguna_m_reset_out, - output wire [C_SLR_WIDTH-1:0] laguna_m_payload, - output wire laguna_m_handshake, - input wire laguna_m_ready - ); - - generate - - if (C_REG_CONFIG == 13) begin : gen_slr_tdm - localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH; - - (* keep="true" *) reg areset_d = 1'b0; - always @(posedge ACLK) begin - areset_d <= ARESET; - end - - assign laguna_m_reset_out = 1'b0; - - (* shreg_extract = "no" *) reg [P_EVEN_WIDTH-1:0] payload_d1; - (* shreg_extract = "no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d2; - (* USER_SLL_REG="true", shreg_extract = "no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d3; - (* USER_SLL_REG="true", shreg_extract = "no" *) reg laguna_handshake_d1 = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg s_ready_d2 = 1'b0; - wire sample_cycle; - integer i; - - assign laguna_m_payload = laguna_payload_tdm_d3; - assign laguna_m_handshake = laguna_handshake_d1; - assign S_READY = s_ready_d2; - - always @(posedge ACLK) begin - payload_d1 <= S_PAYLOAD_DATA; // ACLK cycle 1 - end - - always @(posedge ACLK2X) begin - for (i=0;i0) ? C_PIPELINES : 1; - - (* keep="true" *) reg areset_r = 1'b0; - (* keep="true" *) reg areset_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_reset_out_i = 1'b0; - reg [15:0] areset_dly = 16'b0; - - assign laguna_m_reset_out = laguna_m_reset_out_i; - - always @(posedge ACLK) begin - areset_r <= ARESET; - areset_dly <= {16{areset_r}} | (areset_dly<<1); - areset_d <= C_REG_CONFIG == 12 ? ARESET : areset_dly[15]; - laguna_m_reset_out_i <= areset_d; // For resp channels, reflect laguna_m_reset_in_d to avoid tie-off laguna routing errors, but it doesn't get used. - end - - wire ACLEAR; - assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET; - - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_m_payload_i; - wire m_handshake_d; - wire laguna_m_handshake_q; - (* USER_SLL_REG="true", keep="true" *) reg laguna_m_ready_d = 1'b0; - (* keep="true" *) reg s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+1)-1:0] handshake_i; - genvar p; - - assign laguna_m_payload = laguna_m_payload_i; - assign m_handshake_d = C_PIPELINES==0 ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[P_PIPE_WIDTH-1]; - assign laguna_m_handshake = laguna_m_handshake_q; - assign S_READY = s_ready_i; - - always @(posedge ACLK) begin - laguna_m_ready_d <= laguna_m_ready; - ready_d <= {ready_d, laguna_m_ready_d}; - if (areset_d) begin - s_ready_i <= 1'b0; - end else begin - s_ready_i <= (C_PIPELINES==0) ? laguna_m_ready_d : ready_d[P_PIPE_WIDTH-1]; - end - end - - for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - wire payload_valid_d; - wire payload_valid_q; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data; - assign handshake_i[p] = payload_valid_q; - assign payload_valid_d = (p==0) ? (S_VALID & ACLKEN & s_ready_i) : handshake_i[((p>0)?(p-1):0)]; - - always @(posedge ACLK) begin - if (p==C_PIPELINES) begin - laguna_m_payload_i <= C_PIPELINES==0 ? S_PAYLOAD_DATA : payload_i[(P_PIPE_WIDTH-1)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end else if (p==0) begin - payload_data <= S_PAYLOAD_DATA; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - FDCE #( - .INIT(1'b0) - ) payload_valid_asyncclear_inst ( - .Q (payload_valid_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (payload_valid_d) - ); - end // loop p - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_m_handshake_asyncclear_inst ( - .Q (laguna_m_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (m_handshake_d) - ); - - end // gen_slr -endgenerate -endmodule // source_region_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_dest_region_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_REG_CONFIG = 12, - parameter integer C_DATA_WIDTH = 32, - parameter integer C_SLR_WIDTH = 32, - parameter integer C_PIPELINES = 0, - parameter integer C_SOURCE_LATENCY = 1 - ) - ( - // System Signals - input wire ACLK, - input wire ACLK2X, - input wire ARESET, - input wire ACLKEN, - - // Slave side - input wire laguna_s_reset_in, - input wire [C_SLR_WIDTH-1:0] laguna_s_payload, - input wire laguna_s_handshake, - output wire laguna_s_ready, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - generate - - if (C_REG_CONFIG == 13) begin : gen_slr_tdm - (* keep="true" *) reg areset_d = 1'b0; - always @(posedge ACLK) begin - areset_d <= ARESET; - end - - localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH; - - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] laguna_payload_tdm_d3; - (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d4; - (* shreg_extract="no" *) reg [C_SLR_WIDTH-1:0] payload_tdm_d5; - (* USER_SLL_REG="true", shreg_extract="no" *) reg laguna_handshake_d2 = 1'b0; - (* shreg_extract="no" *) reg handshake_d3 = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg s_ready_d1 = 1'b0; - reg [P_EVEN_WIDTH-1:0] payload_demux; - wire m_valid_i; - wire push; - wire pop; - integer i; - - assign laguna_s_ready = s_ready_d1; - assign M_VALID = m_valid_i; - assign pop = M_READY & ACLKEN & m_valid_i; - assign push = handshake_d3; - - always @(posedge ACLK) begin - if (areset_d) begin - laguna_handshake_d2 <= 1'b0; - handshake_d3 <= 1'b0; - end else begin - handshake_d3 <= laguna_handshake_d2; - laguna_handshake_d2 <= laguna_s_handshake; - end - end - - always @(posedge ACLK2X) begin - payload_tdm_d5 <= payload_tdm_d4; - payload_tdm_d4 <= laguna_payload_tdm_d3; - laguna_payload_tdm_d3 <= laguna_s_payload; - end - - always @ * begin - for (i=0;i0 ? C_PIPELINES : 1; - localparam integer P_PIPE_LATENCY = ((C_SOURCE_LATENCY>0)?C_SOURCE_LATENCY:1) + C_PIPELINES; - - (* keep="true" *) reg areset_d = 1'b0; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_reset_in_d = 1'b0; - - always @(posedge ACLK) begin - laguna_s_reset_in_d <= laguna_s_reset_in; - areset_d <= C_REG_CONFIG == 12 ? ARESET : laguna_s_reset_in_d; - end - - wire ACLEAR; - assign ACLEAR = C_REG_CONFIG == 12 ? 1'b0 : ARESET; - - (* USER_SLL_REG="true", shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] laguna_s_payload_d; - wire laguna_s_handshake_q; - (* USER_SLL_REG="true", keep="true" *) reg laguna_s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+1)-1:0] handshake_i; - wire m_valid_i; - wire push; - wire pop; - genvar p; - - assign laguna_s_ready = laguna_s_ready_i; - assign pop = M_READY & ACLKEN & m_valid_i; - assign push = handshake_i[C_PIPELINES]; - assign M_VALID = m_valid_i; - - always @(posedge ACLK) begin - laguna_s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; - ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)}; - end - - for (p=0; p<=C_PIPELINES; p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - wire payload_valid_d; - wire payload_valid_q; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = (p==0) ? laguna_s_payload_d : payload_data; - assign handshake_i[p] = (p==0) ? laguna_s_handshake_q : payload_valid_q; - assign payload_valid_d = handshake_i[((p>0)?(p-1):0)]; - - always @(posedge ACLK) begin - if (p==0) begin - laguna_s_payload_d <= laguna_s_payload; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - FDCE #( - .INIT(1'b0) - ) payload_valid_asyncclear_inst ( - .Q (payload_valid_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (payload_valid_d) - ); - end // loop p - - (* USER_SLL_REG="true" *) - FDCE #( - .INIT(1'b0) - ) laguna_s_handshake_asyncclear_inst ( - .Q (laguna_s_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (ACLEAR), - .D (laguna_s_handshake) - ); - - axis_register_slice_v1_1_29_axic_reg_srl_fifo # - ( - .C_FIFO_WIDTH (C_DATA_WIDTH), - .C_FIFO_SIZE ((C_PIPELINES+C_SOURCE_LATENCY>14) ? 6 : (C_PIPELINES+C_SOURCE_LATENCY>6) ? 5 : 4) - ) - srl_fifo_0 - ( - .aclk (ACLK), - .areset (areset_d), - .aclear (ACLEAR), - .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]), - .s_valid (push), - .m_mesg (M_PAYLOAD_DATA), - .m_valid (m_valid_i), - .m_ready (pop) - ); - - end // gen_slr -endgenerate -endmodule // dest_region_slr - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_single_slr # - ( - parameter C_FAMILY = "virtex6", - parameter integer C_DATA_WIDTH = 32, - parameter integer C_PIPELINES = 0 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - generate - - localparam integer P_PIPE_WIDTH = (C_PIPELINES>0) ? C_PIPELINES : 1; - - reg areset_d = 1'b0; - reg [3:0] areset_dly = 4'b0; - always @(posedge ACLK) begin - areset_dly <= {4{ARESET}} | (areset_dly<<1); - areset_d <= areset_dly[3]; - end - - if (1) begin : common - reg s_ready_i = 1'b0; - (* keep="true" *) reg [P_PIPE_WIDTH-1:0] ready_d = {P_PIPE_WIDTH{1'b0}}; - wire [(C_PIPELINES+1)*C_DATA_WIDTH-1:0] payload_i; - wire [(C_PIPELINES+1)-1:0] handshake_i; - wire m_valid_i; - wire push; - wire pop; - genvar p; - - assign pop = M_READY & ACLKEN & m_valid_i; - assign push = handshake_i[C_PIPELINES]; - assign M_VALID = m_valid_i; - assign S_READY = s_ready_i; - - always @(posedge ACLK) begin - ready_d <= {ready_d, ((M_READY & ACLKEN) | ~m_valid_i)}; - if (areset_d) begin - s_ready_i <= 1'b0; - end else begin - s_ready_i <= (C_PIPELINES==0) ? ((M_READY & ACLKEN) | ~m_valid_i) : ready_d[P_PIPE_WIDTH-1]; - end - end - - assign payload_i[0 +: C_DATA_WIDTH] = S_PAYLOAD_DATA; - assign handshake_i[0] = S_VALID & ACLKEN & s_ready_i; - - for (p=1; p<=C_PIPELINES; p=p+1) begin : pipe - (* shreg_extract="no" *) reg [C_DATA_WIDTH-1:0] payload_data; - (* keep="true" *) reg payload_valid = 1'b0; - - assign payload_i[p*C_DATA_WIDTH +: C_DATA_WIDTH] = payload_data; - assign handshake_i[p] = payload_valid; - - always @(posedge ACLK) begin - if (p==1) begin - payload_data <= S_PAYLOAD_DATA; - payload_valid <= S_VALID & ACLKEN & s_ready_i & ~areset_d; - end else begin - payload_data <= payload_i[((p>0)?(p-1):0)*C_DATA_WIDTH +: C_DATA_WIDTH]; - payload_valid <= handshake_i[((p>0)?(p-1):0)]; - end - end - end - - if (C_PIPELINES==0) begin : ff_fifo - - (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out; - (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n1; - (* shreg_extract = "no" *) reg [C_DATA_WIDTH-1:0] fifo_out_n2; - reg [1:0] fifo_cnt = 2'h0; - reg m_valid_r = 1'b0; - - assign M_PAYLOAD_DATA = fifo_out; - assign m_valid_i = m_valid_r; - - always @(posedge ACLK) begin - if (areset_d) begin - fifo_cnt <= 2'h0; - m_valid_r <= 1'b0; - end else begin - if (push & ~pop) begin - fifo_cnt <= fifo_cnt + 2'h1; - m_valid_r <= 1'b1; - end else if (~push & pop) begin - fifo_cnt <= fifo_cnt - 2'h1; - m_valid_r <= fifo_cnt[1]; // fifo_cnt >= 2 - end - end - end - - always @(posedge ACLK) begin - case (fifo_cnt) - 2'h0: begin // EMPTY - fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - - 2'h1: begin - fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - if (pop) begin - fifo_out <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - 2'h2: begin - fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - if (pop) begin - fifo_out <= fifo_out_n1; - fifo_out_n1 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - - default: begin // fifo_cnt == 3 - if (pop) begin - fifo_out <= fifo_out_n1; - fifo_out_n1 <= fifo_out_n2; - fifo_out_n2 <= payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]; - end - end - endcase - end - - end else begin : srl_fifo - - axis_register_slice_v1_1_29_axic_reg_srl_fifo # - ( - .C_FIFO_WIDTH (C_DATA_WIDTH), - .C_FIFO_SIZE ((C_PIPELINES>12) ? 5 : 4) - ) - srl_fifo_0 - ( - .aclk (ACLK), - .areset (areset_d), - .aclear (1'b0), - .s_mesg (payload_i[C_PIPELINES*C_DATA_WIDTH +: C_DATA_WIDTH]), - .s_valid (push), - .m_mesg (M_PAYLOAD_DATA), - .m_valid (m_valid_i), - .m_ready (pop) - ); - - end // gen_fifo - end // gen_slr - endgenerate -endmodule // single_slr - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_axic_reg_srl_fifo # - // FIFO with no s_ready back-pressure; must guarantee parent will never push beyond full - ( - parameter integer C_FIFO_WIDTH = 1, // Width of s_mesg/m_mesg. - parameter integer C_FIFO_SIZE = 5 // Depth of FIFO is 2**C_FIFO_SIZE. - ) - ( - input wire aclk, // Clock - input wire areset, // Reset - input wire aclear, // Async clear - input wire [C_FIFO_WIDTH-1:0] s_mesg, // Input data - input wire s_valid, // Input data valid - output wire [C_FIFO_WIDTH-1:0] m_mesg, // Output data - output wire m_valid, // Output data valid - input wire m_ready // Output data ready - ); - - genvar i; - - generate - - localparam integer P_FIFO_DEPTH = 2**C_FIFO_SIZE; - localparam [C_FIFO_SIZE-1:0] P_EMPTY = {C_FIFO_SIZE{1'b1}}; - localparam [C_FIFO_SIZE-1:0] P_ALMOSTEMPTY = {C_FIFO_SIZE{1'b0}}; - - localparam M_VALID_0 = 1'b0; - localparam M_VALID_1 = 1'b1; - localparam SRL_VALID_0 = 1'b0; - localparam SRL_VALID_1 = 1'b1; - localparam S_VALID_0 = 1'b0; - localparam S_VALID_1 = 1'b1; - localparam M_READY_0 = 1'b0; - localparam M_READY_1 = 1'b1; - - localparam [1:0] K_EMPTY = {SRL_VALID_0, M_VALID_0}; - localparam [1:0] K_HAS1 = {SRL_VALID_0, M_VALID_1}; - localparam [1:0] K_MIN2 = {SRL_VALID_1, M_VALID_1}; - - reg push; // SRL push - reg pop; // SRL pop - wire [C_FIFO_WIDTH-1:0] srl_reg; - reg [C_FIFO_SIZE-1:0] fifoaddr = P_EMPTY; - - wire [1:0] state; // State vector register - reg [1:0] next; // Next state value - wire [1:0] next_qual; // Next state value - - reg load_mesg; // Load output register - reg srl2mesg; // Output reg loads from SRL (else from s_mesg) - reg [C_FIFO_WIDTH-1:0] mesg_reg; // No initial state - reg m_valid_d; - wire m_valid_q; - - assign m_valid = m_valid_q; - assign next_qual = areset ? K_EMPTY : next; - assign m_mesg = mesg_reg; - - FDCE #( - .INIT(1'b0) - ) asyncclear_mvalid_inst ( - .Q (m_valid_q), - .C (aclk), - .CE (1'b1), - .CLR (aclear), - .D (m_valid_d) - ); - - FDCE #( - .INIT(1'b0) - ) asyncclear_state0_inst ( - .Q (state[0]), - .C (aclk), - .CE (1'b1), - .CLR (aclear), - .D (next_qual[0]) - ); - - FDCE #( - .INIT(1'b0) - ) asyncclear_state1_inst ( - .Q (state[1]), - .C (aclk), - .CE (1'b1), - .CLR (aclear), - .D (next_qual[1]) - ); - - always @ * begin - next = state; // Default: hold state unless re-assigned - m_valid_d = m_valid_q & ~areset; - load_mesg = 1'b1; - srl2mesg = 1'b0; - push = 1'b0; - pop = 1'b0; - case (state) - K_EMPTY: begin // FIFO Empty; pre-assert s_ready - load_mesg = s_valid; - srl2mesg = 1'b0; - push = 1'b0; - pop = 1'b0; - if (s_valid & ~areset) begin - next = K_HAS1; - m_valid_d = 1'b0; - end - end // EMPTY - - K_HAS1: begin // FIFO contains 1 item in the output register (SRL empty) - srl2mesg = 1'b0; - pop = 1'b0; - casex ({s_valid,m_ready}) - {S_VALID_1,M_READY_0}: begin // Receive a 2nd item, push into SRL - next = K_MIN2; - load_mesg = 1'b0; - push = 1'b1; - m_valid_d = 1'b1; - end - - {S_VALID_0,M_READY_1}: begin // Pop to empty - next = K_EMPTY; - load_mesg = 1'b1; // Inconsequential - push = 1'b0; - m_valid_d = 1'b0; - end - - {S_VALID_1,M_READY_1}: begin // Push a new item while popping; replace contents of output reg - next = K_HAS1; - load_mesg = 1'b1; - push = 1'b0; - m_valid_d = 1'b1; - end - - default: begin // s_valid=0, m_ready=0: hold state - next = K_HAS1; - load_mesg = 1'b0; - push = 1'b0; - m_valid_d = 1'b1; - end - endcase - end // HAS1 - - K_MIN2: begin // FIFO contains >1 item, some in SRL - srl2mesg = 1'b1; - m_valid_d = 1'b1; - casex ({s_valid,m_ready}) - {S_VALID_1,M_READY_0}: begin // Receive a new item, push into SRL - next = K_MIN2; - load_mesg = 1'b0; - push = 1'b1; - pop = 1'b0; - end - - {S_VALID_0,M_READY_1}: begin // Pop SRL to replace output reg - next = (fifoaddr == P_ALMOSTEMPTY) ? K_HAS1 : K_MIN2; - load_mesg = 1'b1; - push = 1'b0; - pop = 1'b1; - end - - {S_VALID_1,M_READY_1}: begin // Push a new item while popping - next = K_MIN2; - load_mesg = 1'b1; - push = 1'b1; - pop = 1'b1; - end - - default: begin // s_valid=0, m_ready=0: hold state - next = K_MIN2; - load_mesg = 1'b0; - push = 1'b0; - pop = 1'b0; - end - endcase - end // MIN2 - - default: begin // Same as RESET - next = K_EMPTY; - end // default - endcase - end - - always @(posedge aclk) begin // Payload reg needs no reset - if (load_mesg) begin - mesg_reg <= srl2mesg ? srl_reg : s_mesg; - end - end - - // SRL FIFO address pointer - always @(posedge aclk) begin - if (areset) begin - fifoaddr <= P_EMPTY; - end else begin - if (push & ~pop) begin - fifoaddr <= fifoaddr + 1; - end else if (~push & pop) begin - fifoaddr <= fifoaddr - 1; - end - end - end - - //--------------------------------------------------------------------------- - // Instantiate SRLs - //--------------------------------------------------------------------------- - for (i=0;i= 1) - ) - ( - input wire clk, // Clock - input wire [C_A_WIDTH-1:0] a, // Address - input wire ce, // Clock Enable - input wire d, // Input Data - output wire q // Output Data - ); - - localparam integer P_SRLDEPTH = 2**C_A_WIDTH; - - reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}}; - always @(posedge clk) - if (ce) - shift_reg <= {shift_reg[P_SRLDEPTH-2:0], d}; - assign q = shift_reg[a]; - -endmodule // srl_rtl - - -// (c) Copyright 2019, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// - -`timescale 1ps/1ps -(* DowngradeIPIdentifiedWarnings="yes" *) -(* autopipeline_module="yes" *) -module axis_register_slice_v1_1_29_auto_slr # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - // System Signals - input wire ACLK, - input wire ACLKEN, - input wire ARESET, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - wire handshake_pipe; - wire ready_pipe; - wire [C_DATA_WIDTH-1:0] payload_pipe; - (* keep="true" *) reg s_aclear = 1'b0; - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg s_areset_fwd = 1'b0; - (* autopipeline_group="resp" *) reg s_areset_resp = 1'b0; - (* keep="true" *) reg s_areset_resp2 = 1'b0; - (* keep="true" *) reg m_aclear = 1'b0; - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg m_areset_fwd = 1'b0; - (* autopipeline_group="resp" *) reg m_areset_resp = 1'b0; - (* keep="true" *) reg m_areset_resp2 = 1'b0; - - // Global Reset pipelining - - always @(posedge ACLK) begin - s_aclear <= ARESET; - s_areset_fwd <= ARESET; - s_areset_resp <= s_areset_fwd; // Auto-pipeline - s_areset_resp2 <= s_areset_resp; // Auto-pipeline - end - - always @(posedge ACLK) begin - m_aclear <= ARESET; - m_areset_fwd <= ARESET; - m_areset_resp <= m_areset_fwd; // Auto-pipeline - m_areset_resp2 <= m_areset_resp; // Auto-pipeline - end - - // Source-side submodule - - axis_register_slice_v1_1_29_auto_src # - ( - .C_DATA_WIDTH (C_DATA_WIDTH) - ) - slr_auto_src - ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .s_aclear (s_aclear), - .s_areset_resp2 (s_areset_resp2), - .S_VALID (S_VALID), - .S_READY (S_READY), - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .ready_pipe (ready_pipe), - .handshake_pipe (handshake_pipe), - .payload_pipe (payload_pipe) - ); - - // Destination-side submodule - - axis_register_slice_v1_1_29_auto_dest # - ( - .C_DATA_WIDTH (C_DATA_WIDTH) - ) - slr_auto_dest - ( - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .m_aclear (m_aclear), - .m_areset_resp2 (m_areset_resp2), - .M_READY (M_READY), - .M_VALID (M_VALID), - .M_PAYLOAD_DATA (M_PAYLOAD_DATA), - .handshake_pipe (handshake_pipe), - .ready_pipe (ready_pipe), - .payload_pipe (payload_pipe) - ); - -endmodule // auto_slr - -module axis_register_slice_v1_1_29_auto_src # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - input wire ACLK, - input wire ACLKEN, - input wire s_aclear, - input wire s_areset_resp2, - input wire S_VALID, - input wire ready_pipe, - output wire S_READY, - output wire handshake_pipe, - output wire [C_DATA_WIDTH-1:0] payload_pipe, - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA - ); - - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) reg [C_DATA_WIDTH-1:0] payload_pipe_r; - (* keep="true" *) reg [2:0] s_aresetn_resp4 = 3'b000; - wire s_aresetn_resp3; - wire s_aresetn_d; - wire s_aresetn_q; - wire s_handshake_d; - wire s_ready_i; - - assign S_READY = s_ready_i & s_aresetn_q; - assign s_aresetn_d = (~s_aresetn_resp4[2] & s_aresetn_resp4[0]) | s_aresetn_q; - assign s_handshake_d = S_VALID & s_ready_i & ACLKEN & s_aresetn_q; - assign payload_pipe = payload_pipe_r; - - always @(posedge ACLK or posedge s_aclear) begin - if (s_aclear) begin - s_aresetn_resp4 <= 3'b000; - end else begin - s_aresetn_resp4 <= {s_aresetn_resp4[1:0], s_aresetn_resp3}; - end - end - - always @(posedge ACLK) begin - payload_pipe_r <= S_PAYLOAD_DATA; - end - - FDCE #( - .INIT(1'b0) - ) s_aresetn_resp3_inst ( - .Q (s_aresetn_resp3), - .C (ACLK), - .CE (1'b1), - .CLR (1'b0), - .D (~s_areset_resp2) - ); - - // Assert s_aresetn_q asynchronously on leading edge of s_aclear; De-assert synchronously on trailing edge of s_areset_resp2. - FDCE #( - .INIT(1'b0) - ) reset_asyncclear ( - .Q (s_aresetn_q), - .C (ACLK), - .CE (1'b1), - .CLR (s_aclear), - .D (s_aresetn_d) - ); - - (* autopipeline_group="fwd",autopipeline_limit=24,autopipeline_include="resp" *) - FDCE #( - .INIT(1'b0) - ) handshake_asyncclear ( - .Q (handshake_pipe), - .C (ACLK), - .CE (1'b1), - .CLR (s_aclear), - .D (s_handshake_d) - ); - - FDCE #( - .INIT(1'b0) - ) ready_asyncclear ( - .Q (s_ready_i), - .C (ACLK), - .CE (ACLKEN), - .CLR (s_aclear), - .D (ready_pipe) - ); - -endmodule // auto_src - -module axis_register_slice_v1_1_29_auto_dest # - ( - parameter integer C_DATA_WIDTH = 32 - ) - ( - input wire ACLK, - input wire ACLKEN, - input wire m_aclear, - input wire m_areset_resp2, - input wire M_READY, - input wire handshake_pipe, - output wire ready_pipe, - output wire M_VALID, - input wire [C_DATA_WIDTH-1:0] payload_pipe, - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA - ); - - (* keep="true" *) reg [2:0] m_aresetn_resp4 = 3'b000; - wire m_aresetn_resp3; - wire m_aresetn_d; - wire m_aresetn_q; - wire m_valid_i; - wire pop; - wire m_ready_d; - wire m_handshake_q; - reg [C_DATA_WIDTH-1:0] m_payload_q; - - assign M_VALID = m_valid_i; - assign m_aresetn_d = (~m_aresetn_resp4[2] & m_aresetn_resp4[0]) | m_aresetn_q; - assign m_ready_d = (M_READY | ~m_valid_i) & ACLKEN & m_aresetn_q; - assign pop = M_READY & m_valid_i & ACLKEN; - - always @(posedge ACLK or posedge m_aclear) begin - if (m_aclear) begin - m_aresetn_resp4 <= 3'b000; - end else begin - m_aresetn_resp4 <= {m_aresetn_resp4[1:0], m_aresetn_resp3}; - end - end - - always @(posedge ACLK) begin - m_payload_q <= payload_pipe; - end - - FDCE #( - .INIT(1'b0) - ) m_aresetn_resp3_inst ( - .Q (m_aresetn_resp3), - .C (ACLK), - .CE (1'b1), - .CLR (1'b0), - .D (~m_areset_resp2) - ); - - // Assert m_aresetn_q asynchronously on leading edge of m_aclear; De-assert synchronously on trailing edge of m_areset_resp2. - FDCE #( - .INIT(1'b0) - ) reset_asyncclear ( - .Q (m_aresetn_q), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (m_aresetn_d) - ); - - FDCE #( - .INIT(1'b0) - ) handshake_asyncclear ( - .Q (m_handshake_q), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (handshake_pipe) - ); - - (* autopipeline_group="resp" *) - FDCE #( - .INIT(1'b0) - ) ready_asyncclear ( - .Q (ready_pipe), - .C (ACLK), - .CE (1'b1), - .CLR (m_aclear), - .D (m_ready_d) - ); - - axis_register_slice_v1_1_29_axic_reg_srl_fifo # - ( - .C_FIFO_WIDTH (C_DATA_WIDTH), - .C_FIFO_SIZE (5) - ) - srl_fifo - ( - .aclk (ACLK), - .areset (~m_aresetn_q), - .aclear (m_aclear), - .s_mesg (m_payload_q), - .s_valid (m_handshake_q), - .m_mesg (M_PAYLOAD_DATA), - .m_valid (m_valid_i), - .m_ready (pop) - ); - -endmodule // auto_dest - - -// (c) Copyright 2010-2011, 2013-2014, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Register Slice -// Generic single-channel AXI pipeline register on forward and/or reverse signal path -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axic_register_slice -// -//-------------------------------------------------------------------------- - -`timescale 1ps/1ps - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_axisc_register_slice # - ( - parameter C_FAMILY = "virtex6", - parameter C_DATA_WIDTH = 32, - parameter C_REG_CONFIG = 32'h00000001, - // C_REG_CONFIG: - // 0 => BYPASS = The channel is just wired through the module. - // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID - // 2 => FWD = The master VALID and payload signals are registrated. - // 3 => REV = The slave ready signal is registrated - // 4 => RESERVED (all outputs driven to 0). - // 5 => RESERVED (all outputs driven to 0). - // 6 => INPUTS = Slave and Master side inputs are registrated. - // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining - // 8 => FWD_REV = Both FWD and REV (fully-registered) - // 10 => NO_READY = Assume no ready signal - // 12 => SLR Crossing (source->dest flops, full-width payload, single clock) - // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock) - // 15 => Variable SLR Crossings (single clock) - // 16 -> Auto-pipelining - parameter integer C_NUM_SLR_CROSSINGS = 0, - parameter integer C_PIPELINES_MASTER = 0, - parameter integer C_PIPELINES_SLAVE = 0, - parameter integer C_PIPELINES_MIDDLE = 0 - ) - ( - // System Signals - input wire ACLK, - input wire ACLK2X, - input wire ARESET, - input wire ACLKEN, - - // Slave side - input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, - input wire S_VALID, - output wire S_READY, - - // Master side - output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, - output wire M_VALID, - input wire M_READY - ); - - generate - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 0 - // Bypass mode - // - //////////////////////////////////////////////////////////////////// - if (C_REG_CONFIG == 32'h00000000) - begin - assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; - assign M_VALID = S_VALID; - assign S_READY = M_READY; - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 17 - // Preserve SI - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 17) begin : gen_pres_si - - axis_register_slice_v1_1_29_test_slave # ( - .C_DATA_WIDTH ( C_DATA_WIDTH ) - ) - auto ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Slave side - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY) - ); - - // Master side - assign M_PAYLOAD_DATA = 0; - assign M_VALID = 1'b0; - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 18 - // Preserve MI - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 18) begin : gen_pres_mi - - axis_register_slice_v1_1_29_test_master # ( - .C_DATA_WIDTH ( C_DATA_WIDTH ) - ) - auto ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Master side - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - - // Slave side - assign S_READY = 1'b0; - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 16 - // Multi SLR Crossing - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 16) begin : gen_auto_slr - - axis_register_slice_v1_1_29_auto_slr # ( - .C_DATA_WIDTH ( C_DATA_WIDTH ) - ) - auto ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Slave side - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - - // Master side - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 15 - // Multi SLR Crossing - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 15) begin : gen_multi_slr - - axis_register_slice_v1_1_29_multi_slr # ( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) , - .C_PIPELINES_MASTER (C_PIPELINES_MASTER) , - .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) , - .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE) - ) - multi ( - // System Signals - .ACLK (ACLK), - .ACLKEN (ACLKEN) , - .ARESET (ARESET), - - // Slave side - .S_PAYLOAD_DATA (S_PAYLOAD_DATA), - .S_VALID (S_VALID), - .S_READY (S_READY), - - // Master side - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - end - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 12 or 13 - // TDM SLR Crossing - // - //////////////////////////////////////////////////////////////////// - else if ((C_REG_CONFIG == 32'h0000000C) || (C_REG_CONFIG == 32'h0000000D)) - begin : gen_slr_crossing - localparam integer P_EVEN_WIDTH = C_DATA_WIDTH[0] ? (C_DATA_WIDTH+1) : C_DATA_WIDTH; - localparam integer P_TDM_WIDTH = P_EVEN_WIDTH/2; - localparam integer P_SLR_WIDTH = (C_REG_CONFIG == 13) ? P_TDM_WIDTH : C_DATA_WIDTH; - - wire [P_SLR_WIDTH-1:0] slr_payload; - wire slr_handshake; - wire slr_ready; - - axis_register_slice_v1_1_29_source_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( C_REG_CONFIG ) , - .C_PIPELINES (0), - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( P_SLR_WIDTH ) - ) - slr_source_0 ( - .ACLK ( ACLK ) , - .ACLK2X ( ACLK2X ) , - .ARESET (ARESET), - .ACLKEN ( ACLKEN ) , - .laguna_m_reset_out ( ) , - .S_PAYLOAD_DATA ( S_PAYLOAD_DATA ) , - .S_VALID ( S_VALID ) , - .S_READY ( S_READY ) , - .laguna_m_payload ( slr_payload ) , - .laguna_m_handshake ( slr_handshake ) , - .laguna_m_ready ( slr_ready ) - ); - - axis_register_slice_v1_1_29_dest_region_slr #( - .C_FAMILY ( C_FAMILY ) , - .C_REG_CONFIG ( C_REG_CONFIG ) , - .C_PIPELINES (0), - .C_DATA_WIDTH ( C_DATA_WIDTH ) , - .C_SLR_WIDTH ( P_SLR_WIDTH ) - ) - slr_dest_0 ( - .ACLK ( ACLK ) , - .ACLK2X ( ACLK2X ) , - .ARESET (ARESET), - .ACLKEN ( ACLKEN ) , - .laguna_s_reset_in ( 1'b0 ) , - .laguna_s_payload ( slr_payload ) , - .laguna_s_handshake ( slr_handshake ) , - .laguna_s_ready ( slr_ready ) , - .M_PAYLOAD_DATA ( M_PAYLOAD_DATA ) , - .M_VALID ( M_VALID ) , - .M_READY ( M_READY ) - ); - - end // if (C_REG_CONFIG == 12 or 13 ) - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 10 - // No ready, single stage register - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h0000000A) - begin : NO_READY - - reg [C_DATA_WIDTH-1:0] storage_data1; - reg m_valid_r = 1'b0; //local signal of output - - // assign local signal to its output signal - assign S_READY = 1'b1; - assign M_VALID = m_valid_r; - - // Load storage1 with slave side data - always @(posedge ACLK) - begin - if (ACLKEN) begin - storage_data1 <= S_PAYLOAD_DATA; - m_valid_r <= S_VALID; - end - end - - assign M_PAYLOAD_DATA = storage_data1; - - - end // if (C_REG_CONFIG == 10 ) - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 1 - // Minimized fanout on input signals M_READY and S_TVALID - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000001) begin : gen_AB_reg_slice - // /----------S_READY - // |/---------M_VALID - localparam SM_RESET = 2'b00; - localparam SM_IDLE = 2'b10; - localparam SM_ONE = 2'b11; - localparam SM_FULL = 2'b01; - - (* fsm_encoding = "none" *) reg [1:0] state = SM_RESET; - reg [C_DATA_WIDTH-1:0] payload_a; - reg [C_DATA_WIDTH-1:0] payload_b; - reg sel_rd = 1'b0; - reg sel_wr = 1'b0; - wire sel; - wire load_a; - wire load_b; - - assign M_VALID = state[0]; - assign S_READY = state[1]; - - always @(posedge ACLK) begin - if (ARESET) begin - state <= SM_RESET; - end - else if (ACLKEN) begin - case (state) - SM_IDLE: - if (S_VALID) - state <= SM_ONE; - SM_ONE: - if (S_VALID & ~M_READY) - state <= SM_FULL; - else if (~S_VALID & M_READY) - state <= SM_IDLE; - SM_FULL: - if (M_READY) - state <= SM_ONE; - // SM_RESET: - default: - state <= SM_IDLE; - endcase - end - end - - assign sel = sel_rd; - - always @(posedge ACLK) begin - if (ARESET) begin - sel_rd <= 1'b0; - end - else if (ACLKEN) begin - sel_rd <= (M_READY & M_VALID) ? ~sel_rd : sel_rd; - end - end - - assign load_a = ~sel_wr & (state != SM_FULL); - assign load_b = sel_wr & (state != SM_FULL); - always @(posedge ACLK) begin - if (ARESET) begin - sel_wr <= 1'b0; - end - else if (ACLKEN) begin - sel_wr <= (S_READY & S_VALID) ? ~sel_wr : sel_wr; - end - end - - always @(posedge ACLK) begin - if (ACLKEN) begin - payload_a <= load_a ? S_PAYLOAD_DATA : payload_a; - end - end - - always @(posedge ACLK) begin - if (ACLKEN) begin - payload_b <= load_b ? S_PAYLOAD_DATA : payload_b; - end - end - - assign M_PAYLOAD_DATA = sel ? payload_b : payload_a; - - end // if (C_REG_CONFIG == 1 ) - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 8 - // Both FWD and REV mode - // - //////////////////////////////////////////////////////////////////// - else if ((C_REG_CONFIG == 32'h00000008)) - begin - localparam [1:0] - ZERO = 2'b10, - ONE = 2'b11, - TWO = 2'b01; - (* fsm_encoding = "none" *) reg [1:0] state = ZERO; - - reg [C_DATA_WIDTH-1:0] storage_data1; - reg [C_DATA_WIDTH-1:0] storage_data2; - reg load_s1; - wire load_s2; - wire load_s1_from_s2; - reg s_ready_i = 1'b0; //local signal of output - wire m_valid_i; //local signal of output - - // assign local signal to its output signal - assign S_READY = s_ready_i; - assign M_VALID = m_valid_i; - - (* equivalent_register_removal = "no" *) reg [1:0] aresetn_d = 2'b00; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - aresetn_d <= {aresetn_d[0], ~ARESET}; - end - end - - // Load storage1 with either slave side data or from storage2 - always @(posedge ACLK) - begin - if (ACLKEN) begin - storage_data1 <= ~load_s1 ? storage_data1 : - load_s1_from_s2 ? storage_data2 : - S_PAYLOAD_DATA; - end - end - - // Load storage2 with slave side data - always @(posedge ACLK) - begin - if (ACLKEN) begin - storage_data2 <= load_s2 ? S_PAYLOAD_DATA : storage_data2; - end - end - - assign M_PAYLOAD_DATA = storage_data1; - - // Always load s2 on a valid transaction even if it's unnecessary - assign load_s2 = S_VALID & s_ready_i; - - // Loading s1 - always @ * - begin - if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction - // Load when ONE if we both have read and write at the same time - ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || - // Load when TWO and we have a transaction on Master side - ((state == TWO) && (M_READY == 1))) - load_s1 = 1'b1; - else - load_s1 = 1'b0; - end // always @ * - - assign load_s1_from_s2 = (state == TWO); - - // State Machine for handling output signals - always @(posedge ACLK) begin - if (ARESET) begin - s_ready_i <= 1'b0; - state <= ZERO; - end else if (ACLKEN && aresetn_d == 2'b01) begin - s_ready_i <= 1'b1; - state <= ZERO; - end else if (ACLKEN && aresetn_d[0]) begin - case (state) - // No transaction stored locally - ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE - - // One transaction stored locally - ONE: begin - if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO - if (~M_READY & S_VALID) begin - state <= TWO; // Got another one so move to TWO - s_ready_i <= 1'b0; - end - end - - // TWO transaction stored locally - TWO: if (M_READY) begin - state <= ONE; // Read out one so move to ONE - s_ready_i <= 1'b1; - end - - default: - state <= ZERO; - - endcase // case (state) - end - end // always @ (posedge ACLK) - - assign m_valid_i = state[0]; - - end // if (C_REG_CONFIG == 8) - - //////////////////////////////////////////////////////////////////// - // NOT SUPPORTED - // C_REG_CONFIG = 2 - // Only FWD mode - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000002) - begin - reg [C_DATA_WIDTH-1:0] storage_data; - wire s_ready_i; //local signal of output - reg m_valid_i = 1'b0; //local signal of output - - // assign local signal to its output signal - assign S_READY = s_ready_i; - assign M_VALID = m_valid_i; - - (* equivalent_register_removal = "no" *) reg [1:0] areset_d; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - areset_d <= {areset_d[0], ARESET}; - end - end - - // Save payload data whenever we have a transaction on the slave side - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data; - end - - assign M_PAYLOAD_DATA = storage_data; - - // M_Valid set to high when we have a completed transfer on slave side - // Is removed on a M_READY except if we have a new transfer on the slave side - always @(posedge ACLK) begin - if (areset_d) begin - m_valid_i <= 1'b0; - end - else if (ACLKEN) begin - m_valid_i <= S_VALID ? 1'b1 : // Always set m_valid_i when slave side is valid - M_READY ? 1'b0 : // Clear (or keep) when no slave side is valid but master side is ready - m_valid_i; - end - end // always @ (posedge ACLK) - - // Slave Ready is either when Master side drives M_Ready or we have space in our storage data - assign s_ready_i = (M_READY | ~m_valid_i) & ~|areset_d; - - end // if (C_REG_CONFIG == 2) - //////////////////////////////////////////////////////////////////// - // - // NOT SUPPORTED - // C_REG_CONFIG = 3 - // Only REV mode - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000003) - begin - reg [C_DATA_WIDTH-1:0] storage_data; - reg s_ready_i = 1'b0; //local signal of output - reg has_valid_storage_i; - reg has_valid_storage; - - (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - areset_d <= ARESET; - end - end - - // Save payload data whenever we have a transaction on the slave side - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data <= (S_VALID & s_ready_i) ? S_PAYLOAD_DATA : storage_data; - end - - assign M_PAYLOAD_DATA = has_valid_storage ? storage_data : S_PAYLOAD_DATA; - - // Need to determine when we need to save a payload - // Need a combinatorial signals since it will also effect S_READY - always @ * - begin - // Set the value if we have a slave transaction but master side is not ready - if (S_VALID & s_ready_i & ~M_READY) - has_valid_storage_i = 1'b1; - - // Clear the value if it's set and Master side completes the transaction but we don't have a new slave side - // transaction - else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0))) - has_valid_storage_i = 1'b0; - else - has_valid_storage_i = has_valid_storage; - end // always @ * - - always @(posedge ACLK) - begin - if (ARESET) begin - has_valid_storage <= 1'b0; - end - else if (ACLKEN) begin - has_valid_storage <= has_valid_storage_i; - end - end - - // S_READY is either clocked M_READY or that we have room in local storage - always @(posedge ACLK) begin - if (ARESET) begin - s_ready_i <= 1'b0; - end - else if (ACLKEN) begin - s_ready_i <= M_READY | ~has_valid_storage_i; - end - end - - // assign local signal to its output signal - assign S_READY = s_ready_i; - - // M_READY is either combinatorial S_READY or that we have valid data in local storage - assign M_VALID = (S_VALID | has_valid_storage) & ~areset_d; - - end // if (C_REG_CONFIG == 3) - - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED - // - //////////////////////////////////////////////////////////////////// - else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005)) - begin -// synthesis translate_off - initial begin - $display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED."); - end -// synthesis translate_on - assign M_PAYLOAD_DATA = 0; - assign M_VALID = 1'b0; - assign S_READY = 1'b0; - end - - //////////////////////////////////////////////////////////////////// - // - // NOT SUPPORTED - // C_REG_CONFIG = 6 - // INPUTS mode - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000006) - begin - localparam [1:0] - ZERO = 2'b00, - ONE = 2'b01, - TWO = 2'b11; - reg [1:0] state = ZERO; - reg [1:0] next_state; - - reg [C_DATA_WIDTH-1:0] storage_data1; - reg [C_DATA_WIDTH-1:0] storage_data2; - reg s_valid_d = 1'b0; - reg s_ready_d = 1'b0; - reg m_ready_d = 1'b0; - reg m_valid_d = 1'b0; - reg load_s2; - reg sel_s2; - wire new_access; - wire access_done; - wire s_ready_i; //local signal of output - reg s_ready_ii; - reg m_valid_i; //local signal of output - - (* equivalent_register_removal = "no" *) reg areset_d; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - areset_d <= ARESET; - end - end - - // assign local signal to its output signal - assign S_READY = (state == ZERO) ? 1'b0 : s_ready_i; - assign M_VALID = (state == ZERO) ? 1'b0 : m_valid_i; - assign s_ready_i = s_ready_ii & ~areset_d; - - // Registrate input control signals - always @(posedge ACLK) - begin - if (ARESET) begin - s_valid_d <= 1'b0; - s_ready_d <= 1'b0; - m_ready_d <= 1'b0; - end else if (ACLKEN) begin - s_valid_d <= S_VALID; - s_ready_d <= s_ready_i; - m_ready_d <= M_READY; - end - end // always @ (posedge ACLK) - - // Load storage1 with slave side payload data when slave side ready is high - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data1 <= (s_ready_i) ? S_PAYLOAD_DATA : storage_data1; - end - - // Load storage2 with storage data - always @(posedge ACLK) - begin - if (ACLKEN) - storage_data2 <= load_s2 ? storage_data1 : storage_data2; - end - - always @(posedge ACLK) - begin - if (ARESET) - m_valid_d <= 1'b0; - else if (ACLKEN) - m_valid_d <= m_valid_i; - end - - // Local help signals - assign new_access = s_ready_d & s_valid_d; - assign access_done = m_ready_d & m_valid_d; - - - // State Machine for handling output signals - always @* - begin - next_state = state; // Stay in the same state unless we need to move to another state - load_s2 = 0; - sel_s2 = 0; - m_valid_i = 0; - s_ready_ii = 0; - case (state) - // No transaction stored locally - ZERO: begin - load_s2 = 0; - sel_s2 = 0; - m_valid_i = 0; - s_ready_ii = 1; - if (new_access) begin - next_state = ONE; // Got one so move to ONE - load_s2 = 1; - m_valid_i = 0; - end - else begin - next_state = next_state; - load_s2 = load_s2; - m_valid_i = m_valid_i; - end - - end // case: ZERO - - // One transaction stored locally - ONE: begin - load_s2 = 0; - sel_s2 = 1; - m_valid_i = 1; - s_ready_ii = 1; - if (~new_access & access_done) begin - next_state = ZERO; // Read out one so move to ZERO - m_valid_i = 0; - end - else if (new_access & ~access_done) begin - next_state = TWO; // Got another one so move to TWO - s_ready_ii = 0; - end - else if (new_access & access_done) begin - load_s2 = 1; - sel_s2 = 0; - end - else begin - load_s2 = load_s2; - sel_s2 = sel_s2; - end - - - end // case: ONE - - // TWO transaction stored locally - TWO: begin - load_s2 = 0; - sel_s2 = 1; - m_valid_i = 1; - s_ready_ii = 0; - if (access_done) begin - next_state = ONE; // Read out one so move to ONE - s_ready_ii = 1; - load_s2 = 1; - sel_s2 = 0; - end - else begin - next_state = next_state; - s_ready_ii = s_ready_ii; - load_s2 = load_s2; - sel_s2 = sel_s2; - end - end // case: TWO - endcase // case (state) - end // always @ * - - - // State Machine for handling output signals - always @(posedge ACLK) - begin - if (ARESET) - state <= ZERO; - else if (ACLKEN) - state <= next_state; // Stay in the same state unless we need to move to another state - end - - // Master Payload mux - assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1; - - end // if (C_REG_CONFIG == 6) - //////////////////////////////////////////////////////////////////// - // - // C_REG_CONFIG = 7 - // Light-weight mode. - // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining - // Operates same as 1-deep FIFO - // - //////////////////////////////////////////////////////////////////// - else if (C_REG_CONFIG == 32'h00000007) - begin - reg [C_DATA_WIDTH-1:0] storage_data1; - reg s_ready_i = 1'b0; //local signal of output - reg m_valid_i = 1'b0; //local signal of output - - // assign local signal to its output signal - assign S_READY = s_ready_i; - assign M_VALID = m_valid_i; - - (* equivalent_register_removal = "no" *) reg [1:0] aresetn_d = 2'b00; // Reset delay register - always @(posedge ACLK) begin - if (ACLKEN) begin - aresetn_d <= {aresetn_d[0], ~ARESET}; - end - end - - // Load storage1 with slave side data - always @(posedge ACLK) - begin - if (ARESET) begin - s_ready_i <= 1'b0; - m_valid_i <= 1'b0; - end else if (ACLKEN) begin - if (aresetn_d == 2'b01) begin - s_ready_i <= 1'b1; - end else if (aresetn_d[0]) begin - if (m_valid_i & M_READY) begin - s_ready_i <= 1'b1; - m_valid_i <= 1'b0; - end else if (S_VALID & s_ready_i) begin - s_ready_i <= 1'b0; - m_valid_i <= 1'b1; - end - end - if (~m_valid_i) begin - storage_data1 <= S_PAYLOAD_DATA; - end - end - end - assign M_PAYLOAD_DATA = storage_data1; - end // if (C_REG_CONFIG == 7) - - else begin : default_case - // Passthrough - assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; - assign M_VALID = S_VALID; - assign S_READY = M_READY; - end - - endgenerate -endmodule // axisc_register_slice - - - -// (c) Copyright 2011-2014, 2023 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -//////////////////////////////////////////////////////////// -// -// Register Slice -// Generic single-channel AXIS pipeline register on forward and/or reverse signal path. -// -// Verilog-standard: Verilog 2001 -//-------------------------------------------------------------------------- -// -// Structure: -// axis_register_slice -// util_axis2vector -// axisc_register_slice -// util_vector2axis -// -//-------------------------------------------------------------------------- - -`timescale 1ps/1ps -`default_nettype none - -(* DowngradeIPIdentifiedWarnings="yes" *) -module axis_register_slice_v1_1_29_axis_register_slice # -( -/////////////////////////////////////////////////////////////////////////////// -// Parameter Definitions -/////////////////////////////////////////////////////////////////////////////// - parameter C_FAMILY = "virtex6", - parameter integer C_AXIS_TDATA_WIDTH = 8, - parameter integer C_AXIS_TID_WIDTH = 1, - parameter integer C_AXIS_TDEST_WIDTH = 1, - parameter integer C_AXIS_TUSER_WIDTH = 1, - parameter [31:0] C_AXIS_SIGNAL_SET = 32'h3, - // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present - // [0] => TREADY present - // [1] => TDATA present - // [2] => TSTRB present, TDATA must be present - // [3] => TKEEP present, TDATA must be present - // [4] => TLAST present - // [5] => TID present - // [6] => TDEST present - // [7] => TUSER present - parameter integer C_REG_CONFIG = 1, - // C_REG_CONFIG: - // 0 => BYPASS = The channel is just wired through the module. - // 1 => DEFAULT = Minimized fanout on input signals M_READY and S_TVALID - // 2 => FWD = The master VALID and payload signals are registrated. - // 3 => REV = The slave ready signal is registrated - // 4 => RESERVED (all outputs driven to 0). - // 5 => RESERVED (all outputs driven to 0). - // 6 => INPUTS = Slave and Master side inputs are registrated. - // 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining - // 8 => FWD_REV = Both FWD and REV (fully-registered) - // 10 => NO_READY = Assume no ready signal - // 12 => SLR Crossing (source->dest flops, full-width payload, single clock) - // 13 => TDM SLR Crossing (source->dest flops, half-width payload, dual clock) - // 15 => Variable SLR Crossings (single clock) - // 16 -> Auto-pipelining - parameter integer C_NUM_SLR_CROSSINGS = 0, - parameter integer C_PIPELINES_MASTER = 0, - parameter integer C_PIPELINES_SLAVE = 0, - parameter integer C_PIPELINES_MIDDLE = 0 - ) - ( -/////////////////////////////////////////////////////////////////////////////// -// Port Declarations -/////////////////////////////////////////////////////////////////////////////// - // System Signals - input wire aclk, - input wire aclk2x, - input wire aresetn, - input wire aclken, - - // Slave side - input wire s_axis_tvalid, - output wire s_axis_tready, - input wire [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, - input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tstrb, - input wire [C_AXIS_TDATA_WIDTH/8-1:0] s_axis_tkeep, - input wire s_axis_tlast, - input wire [C_AXIS_TID_WIDTH-1:0] s_axis_tid, - input wire [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, - input wire [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, - - // Master side - output wire m_axis_tvalid, - input wire m_axis_tready, - output wire [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, - output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tstrb, - output wire [C_AXIS_TDATA_WIDTH/8-1:0] m_axis_tkeep, - output wire m_axis_tlast, - output wire [C_AXIS_TID_WIDTH-1:0] m_axis_tid, - output wire [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, - output wire [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser - ); - -//////////////////////////////////////////////////////////////////////////////// -// Functions -//////////////////////////////////////////////////////////////////////////////// -`include "axis_infrastructure_v1_1_1.vh" - -//////////////////////////////////////////////////////////////////////////////// -// Local parameters -//////////////////////////////////////////////////////////////////////////////// - localparam P_TPAYLOAD_WIDTH = f_payload_width(C_AXIS_TDATA_WIDTH, C_AXIS_TID_WIDTH, - C_AXIS_TDEST_WIDTH, C_AXIS_TUSER_WIDTH, - C_AXIS_SIGNAL_SET); - -//////////////////////////////////////////////////////////////////////////////// -// Wires/Reg declarations -//////////////////////////////////////////////////////////////////////////////// -wire [P_TPAYLOAD_WIDTH-1:0] s_axis_tpayload; -wire [P_TPAYLOAD_WIDTH-1:0] m_axis_tpayload; - -reg areset_r = 1'b0; -always @(posedge aclk) begin - areset_r <= ~aresetn; -end - -//////////////////////////////////////////////////////////////////////////////// -// BEGIN RTL -//////////////////////////////////////////////////////////////////////////////// - axis_infrastructure_v1_1_1_util_axis2vector #( - .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET ) - ) - util_axis2vector_0 ( - .TDATA ( s_axis_tdata ) , - .TSTRB ( s_axis_tstrb ) , - .TKEEP ( s_axis_tkeep ) , - .TLAST ( s_axis_tlast ) , - .TID ( s_axis_tid ) , - .TDEST ( s_axis_tdest ) , - .TUSER ( s_axis_tuser ) , - .TPAYLOAD ( s_axis_tpayload ) - ); - - axis_register_slice_v1_1_29_axisc_register_slice #( - .C_FAMILY ( C_FAMILY ) , - .C_DATA_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_REG_CONFIG ( (C_AXIS_SIGNAL_SET[0] == 0) ? 32'hA : C_REG_CONFIG), - .C_NUM_SLR_CROSSINGS (C_NUM_SLR_CROSSINGS) , - .C_PIPELINES_MASTER (C_PIPELINES_MASTER) , - .C_PIPELINES_SLAVE (C_PIPELINES_SLAVE) , - .C_PIPELINES_MIDDLE (C_PIPELINES_MIDDLE) - ) - axisc_register_slice_0 ( - .ACLK ( aclk ) , - .ACLK2X ( aclk2x ) , - .ARESET ( areset_r ) , - .ACLKEN ( aclken ) , - .S_VALID ( s_axis_tvalid ) , - .S_READY ( s_axis_tready ) , - .S_PAYLOAD_DATA ( s_axis_tpayload ) , - - .M_VALID ( m_axis_tvalid ) , - .M_READY ( (C_AXIS_SIGNAL_SET[0] == 0) ? 1'b1 : m_axis_tready ) , - .M_PAYLOAD_DATA ( m_axis_tpayload ) - ); - - axis_infrastructure_v1_1_1_util_vector2axis #( - .C_TDATA_WIDTH ( C_AXIS_TDATA_WIDTH ) , - .C_TID_WIDTH ( C_AXIS_TID_WIDTH ) , - .C_TDEST_WIDTH ( C_AXIS_TDEST_WIDTH ) , - .C_TUSER_WIDTH ( C_AXIS_TUSER_WIDTH ) , - .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH ) , - .C_SIGNAL_SET ( C_AXIS_SIGNAL_SET ) - ) - util_vector2axis_0 ( - .TPAYLOAD ( m_axis_tpayload ) , - .TDATA ( m_axis_tdata ) , - .TSTRB ( m_axis_tstrb ) , - .TKEEP ( m_axis_tkeep ) , - .TLAST ( m_axis_tlast ) , - .TID ( m_axis_tid ) , - .TDEST ( m_axis_tdest ) , - .TUSER ( m_axis_tuser ) - ); - - -endmodule // axis_register_slice - -`default_nettype wire - - - diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v deleted file mode 100644 index 4388ff0..0000000 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v +++ /dev/null @@ -1,125 +0,0 @@ -// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of AMD and is protected under U.S. and international copyright -// and other intellectual property laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// AMD, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) AMD shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or AMD had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// AMD products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of AMD products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:axis_register_slice:1.1 -// IP Revision: 29 - -(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *) -(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *) -(* CORE_GENERATION_INFO = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_register_slice,x_ipVersion=1.1,x_ipCoreRevision=29,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011,C_REG_CONFIG=8,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER=0,C_PIPELINES_SLAVE=0,C_PIPELINES_MIDDLE=0}" *) -(* DowngradeIPIdentifiedWarnings = "yes" *) -module axis_register_slice_32 ( - aclk, - aresetn, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata -); - -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) -input wire aclk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) -input wire aresetn; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) -input wire s_axis_tvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) -output wire s_axis_tready; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) -input wire [31 : 0] s_axis_tdata; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) -output wire m_axis_tvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) -input wire m_axis_tready; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) -output wire [31 : 0] m_axis_tdata; - - axis_register_slice_v1_1_29_axis_register_slice #( - .C_FAMILY("zynquplus"), - .C_AXIS_TDATA_WIDTH(32), - .C_AXIS_TID_WIDTH(1), - .C_AXIS_TDEST_WIDTH(1), - .C_AXIS_TUSER_WIDTH(1), - .C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011), - .C_REG_CONFIG(8), - .C_NUM_SLR_CROSSINGS(0), - .C_PIPELINES_MASTER(0), - .C_PIPELINES_SLAVE(0), - .C_PIPELINES_MIDDLE(0) - ) inst ( - .aclk(aclk), - .aclk2x(1'H0), - .aresetn(aresetn), - .aclken(1'H1), - .s_axis_tvalid(s_axis_tvalid), - .s_axis_tready(s_axis_tready), - .s_axis_tdata(s_axis_tdata), - .s_axis_tstrb(4'HF), - .s_axis_tkeep(4'HF), - .s_axis_tlast(1'H1), - .s_axis_tid(1'H0), - .s_axis_tdest(1'H0), - .s_axis_tuser(1'H0), - .m_axis_tvalid(m_axis_tvalid), - .m_axis_tready(m_axis_tready), - .m_axis_tdata(m_axis_tdata), - .m_axis_tstrb(), - .m_axis_tkeep(), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser() - ); -endmodule diff --git a/sim/dds_wrapper_tb.vhd b/sim/dds_wrapper_tb.vhd deleted file mode 100644 index ae98135..0000000 --- a/sim/dds_wrapper_tb.vhd +++ /dev/null @@ -1,321 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:53:22 03/24/2017 --- Design Name: --- Module Name: --- Project Name: xem7350 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: dac_interface --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE IEEE.STD_LOGIC_arith.ALL; -USE IEEE.STD_LOGIC_unsigned.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -Library xpm; -use xpm.vcomponents.all; - ---library UNISIM; ---use UNISIM.VComponents.all; - -entity dds_wrapper_tb is -end dds_wrapper_tb; - -architecture behavior of dds_wrapper_tb is - - -- Clock period definitions - constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz - constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz - constant CLK_100_PERIOD : time := 10 ns; -- 100 MHz - constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz - constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz - constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - - signal clk_100 : std_logic := '0'; - signal clk_100_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_250 : std_logic := '0'; - signal clk_250_aresetn : std_logic_vector(0 to 63) := x"0000_FFFF_0000_0000";--(others => '0'); - - signal m_axis_tready_r : std_logic := '0'; - signal m_axis_tdata : std_logic_vector(127 downto 0); - signal m_axis_tvalid : std_logic; - signal m_axis_tready : std_logic; - - signal util_mxfe_upack_s_axis_tdata_pipe : std_logic_vector(127 downto 0); - signal util_mxfe_upack_s_axis_tvalid_pipe : std_logic; - - signal m_axis_tdata_1 : std_logic_vector(127 downto 0); - signal m_axis_tvalid_1 : std_logic; - signal m_axis_tready_1 : std_logic; - - signal cmd_send_i : std_logic_vector(0 to 3) := (others => '0'); - signal dac_holdoff_r : std_logic := '1'; - - signal chan1_i : std_logic_vector(15 downto 0); - signal chan1_q : std_logic_vector(15 downto 0); - signal chan2_i : std_logic_vector(15 downto 0); - signal chan2_q : std_logic_vector(15 downto 0); - signal chan3_i : std_logic_vector(15 downto 0); - signal chan3_q : std_logic_vector(15 downto 0); - signal chan4_i : std_logic_vector(15 downto 0); - signal chan4_q : std_logic_vector(15 downto 0); - - signal cmd_send_0_r : std_logic_vector(0 to 2) := (others => '0'); - signal cmd_send_1_r : std_logic_vector(0 to 2) := (others => '0'); - signal cmd_send_2_r : std_logic_vector(0 to 2) := (others => '0'); - signal cmd_send_3_r : std_logic_vector(0 to 2) := (others => '0'); - signal cnt_reset : std_logic := '0'; - -begin - - clk_100 <= not clk_100 after CLK_100_PERIOD/2; - clk_250 <= not clk_250 after CLK_250_PERIOD/2; - - --- - process(clk_100) - begin - if (rising_edge(clk_100)) then - clk_100_aresetn <= clk_100_aresetn(1 to 15) & '1'; - end if; - end process; - --- - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_aresetn <= clk_250_aresetn(1 to 63) & '1'; - end if; - end process; - - - process (clk_100) - begin - if rising_edge(clk_100) then - if (cmd_send_i(0) = '1') then - cmd_send_0_r <= "111"; - else - cmd_send_0_r <= cmd_send_0_r(1 to 2) & '0'; - end if; - - if (cmd_send_i(1) = '1') then - cmd_send_1_r <= "111"; - else - cmd_send_1_r <= cmd_send_1_r(1 to 2) & '0'; - end if; - - if (cmd_send_i(2) = '1') then - cmd_send_2_r <= "111"; - else - cmd_send_2_r <= cmd_send_2_r(1 to 2) & '0'; - end if; - - if (cmd_send_i(3) = '1') then - cmd_send_3_r <= "111"; - else - cmd_send_3_r <= cmd_send_3_r(1 to 2) & '0'; - end if; - end if; - end process; - - - i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4 - port map ( - s_axi_aclk_in => clk_100, - s_axi_aresetn_in => clk_100_aresetn(0), - - cmd_idx_in => "000", - dac_holdoff_in => dac_holdoff_r, - - cmd_send_0_in => cmd_send_0_r(0), - scale_0_in => x"8000", - dds_phase_inc_dwell_time_0_in => x"00000000", - dds_phase_inc_step_size_0_in => x"0000D6BF", - idle_samples_0_in => x"00000000", - dds_samples_0_in => x"000004E2", - phase_inc_0_in => x"010624DD", - phase_off_0_in => x"00000000", - swap_sf_0_in => x"00008000", - - cmd_send_1_in => cmd_send_1_r(0), - scale_1_in => x"8000", - dds_phase_inc_dwell_time_1_in => x"00000000", - dds_phase_inc_step_size_1_in => x"0000D6BF", - idle_samples_1_in => x"00000000", - dds_samples_1_in => x"000004E2", --x"000004E2", - phase_inc_1_in => x"010624DD", - phase_off_1_in => x"00000000", - swap_sf_1_in => x"00008000", - - cmd_send_2_in => cmd_send_2_r(0), - scale_2_in => x"8000", - dds_phase_inc_dwell_time_2_in => x"00000000", - dds_phase_inc_step_size_2_in => x"0000D6BF", - idle_samples_2_in => x"00000000", - dds_samples_2_in => x"000004E2", - phase_inc_2_in => x"010624DD", - phase_off_2_in => x"00000000", - swap_sf_2_in => x"00008000", - - cmd_send_3_in => cmd_send_3_r(0), - scale_3_in => x"8000", - dds_phase_inc_dwell_time_3_in => x"00000000", - dds_phase_inc_step_size_3_in => x"0000D6BF", - idle_samples_3_in => x"00000000", - dds_samples_3_in => x"000004E2", - phase_inc_3_in => x"010624DD", - phase_off_3_in => x"00000000", - swap_sf_3_in => x"00008000", - - m_axis_aclk_in => clk_250, - m_axis_aresetn_in => clk_250_aresetn(0), - m0_axis_tdata_out => m_axis_tdata, - m0_axis_tvalid_out => m_axis_tvalid, - m0_axis_tready_in => m_axis_tready, - - m1_axis_tdata_out => open, - m1_axis_tvalid_out => open, - m1_axis_tready_in => '1', - - cnt_reset_in => cnt_reset, - m0_axis_tvalid_cnt_out => open, - m0_dds_pulse_data_cnt_out => open, - m1_axis_tvalid_cnt_out => open, - m1_dds_pulse_data_cnt_out => open - ); - - - -- big FIFO before JESD TX PORT - i_dac_data_fifo_32kx128 : entity work.axis_data_fifo_32kx128 - port map ( - s_axis_aclk => clk_250, -- in - s_axis_aresetn => clk_250_aresetn(0), -- in - s_axis_tdata => m_axis_tdata, -- in - s_axis_tvalid => m_axis_tvalid, -- in - s_axis_tready => m_axis_tready, -- out - - m_axis_tdata => m_axis_tdata_1, -- out - m_axis_tvalid => m_axis_tvalid_1, -- out - m_axis_tready => m_axis_tready_1 -- in - ); - - -- big FIFO before JESD TX PORT - i_dac_data_fifo_32kx128_1 : entity work.axis_data_fifo_32kx128 - port map ( - s_axis_aclk => clk_250, -- in - s_axis_aresetn => clk_250_aresetn(0), -- in - s_axis_tdata => m_axis_tdata_1, -- in - s_axis_tvalid => m_axis_tvalid_1, -- in - s_axis_tready => m_axis_tready_1, -- out - - m_axis_tdata => util_mxfe_upack_s_axis_tdata_pipe, -- out - m_axis_tvalid => util_mxfe_upack_s_axis_tvalid_pipe, -- out - m_axis_tready => m_axis_tready_r -- in - ); - - - chan1_i <= util_mxfe_upack_s_axis_tdata_pipe(15 downto 0); - chan1_q <= util_mxfe_upack_s_axis_tdata_pipe(31 downto 16); - - chan2_i <= util_mxfe_upack_s_axis_tdata_pipe(47 downto 32); - chan2_q <= util_mxfe_upack_s_axis_tdata_pipe(63 downto 48); - - chan3_i <= util_mxfe_upack_s_axis_tdata_pipe(79 downto 64); - chan3_q <= util_mxfe_upack_s_axis_tdata_pipe(95 downto 80); - - chan4_i <= util_mxfe_upack_s_axis_tdata_pipe(111 downto 96); - chan4_q <= util_mxfe_upack_s_axis_tdata_pipe(127 downto 112); - - -- Stimulus process - stim_proc: process - begin - - wait until clk_100_aresetn(0) = '1'; - - -- wait for 24 us; - - wait until rising_edge(clk_250); - m_axis_tready_r <= '1'; - wait for 1 us; - - wait until rising_edge(clk_100); - cmd_send_i(0) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(0) <= '0'; - wait for 1 us; - wait until rising_edge(clk_100); - cmd_send_i(1) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(1) <= '0'; - - wait for 1 us; - wait until rising_edge(clk_100); - cmd_send_i(2) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(2) <= '0'; - - wait for 1 us; - wait until rising_edge(clk_100); - cmd_send_i(3) <= '1'; - wait for 200 ns; - wait until rising_edge(clk_100); - cmd_send_i(3) <= '0'; - - wait for 1 us; - wait until rising_edge(clk_100); - dac_holdoff_r <= '0'; - - - wait for 8 us; - cnt_reset <= '1'; - wait until rising_edge(clk_100); - cnt_reset <= '0'; - - -- m_axis_tready_r <= '0'; - -- wait until rising_edge(clk_250); - - - -- m_axis_tready_r <= '1'; - -- wait until rising_edge(clk_250); - - - -- m_axis_tready_r <= '0'; - -- wait until rising_edge(clk_250); - - - -- m_axis_tready_r <= '1'; - - wait until rising_edge(clk_100); - - wait; -- wait here forever - end process; - - - -end; diff --git a/sim/tb_cap_plybk.vhd b/sim/tb_cap_plybk.vhd deleted file mode 100644 index 3d7d0b6..0000000 --- a/sim/tb_cap_plybk.vhd +++ /dev/null @@ -1,286 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:53:22 03/24/2017 --- Design Name: --- Module Name: --- Project Name: xem7350 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: dac_interface --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE IEEE.STD_LOGIC_arith.ALL; -USE IEEE.STD_LOGIC_unsigned.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -entity tb_cap_plybk is -end tb_cap_plybk; - -architecture behavior of tb_cap_plybk is - - constant C_M_AXI_DATA_WIDTH : integer := 32; - constant C_M_AXI_ADDR_WIDTH : integer := 32; - - -- Clock period definitions - constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz - constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz - constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz - constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz - constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - - signal clk_125 : std_logic := '0'; - signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_125_reset : std_logic; - - signal clk_250 : std_logic := '0'; - signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_250_areset : std_logic; - - signal tx_device_clk_1 : std_logic := '0'; - signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal tx_device_clk_aresetn : std_logic; - - signal rx_device_clk_1 : std_logic := '0'; - signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal rx_device_clk_aresetn : std_logic; - signal rx_device_clk_areset : std_logic; - - signal qsfp4_playback_aclk : std_logic := '0'; - signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp4_playback_aresetn : std_logic; - - signal qsfp1_capture_aclk : std_logic; - signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp1_capture_aresetn : std_logic; - - --- - signal tick_1ms : std_logic; - - signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - - signal adc_rx_tdata_128b : std_logic_vector(127 downto 0) := (others => '0'); - signal adc_rx_tvalid_128b : std_logic := '0'; - signal adc_rx_tready_128b : std_logic; - signal adc_rx_tvalid_128b_cnt : std_logic_vector(31 downto 0); - - - - signal qsfp4_playback_tdata_240b : std_logic_vector(239 downto 0); - signal qsfp4_playback_tvalid_240b : std_logic; - signal qsfp4_playback_tready_240b : std_logic := '1'; - - - signal qsfp1_capture_tdata_240b : std_logic_vector(239 downto 0); - signal qsfp1_capture_tvalid_240b : std_logic; - - - signal tx_tdata_128b : std_logic_vector(127 downto 0); - signal tx_tvalid_128b : std_logic; - signal tx_tready_128b : std_logic := '1'; - - signal qsfp1_capture_rx_data_ready : std_logic; - - signal playback_data_path_enable_n : std_logic := '1'; - - signal adc_rx_tvalid_128b_ena : std_logic; - -begin - - clk_125 <= not clk_125 after CLK_125_PERIOD/2; - clk_250 <= not clk_250 after CLK_250_PERIOD/2; - tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2; - rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2; - - qsfp4_playback_aclk <= not qsfp4_playback_aclk after QSFP4_AXIS_ACLK_PERIOD/2; --- qsfp1_capture_aclk <= not qsfp1_capture_aclk after QSFP1_AXIS_ACLK_PERIOD/2; - --- - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_125_reset <= not clk_125_aresetn(0); --- - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_250_areset <= not clk_250_aresetn(0); --- - process(tx_device_clk_1) - begin - if (rising_edge(tx_device_clk_1)) then - tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1'; - end if; - end process; - - tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0); - --- - process(rx_device_clk_1) - begin - if (rising_edge(rx_device_clk_1)) then - rx_device_clk_aresetn_r <= rx_device_clk_aresetn_r(1 to 15) & '1'; - end if; - end process; - - rx_device_clk_aresetn <= rx_device_clk_aresetn_r(0); - --- - process(qsfp4_playback_aclk) - begin - if (rising_edge(qsfp4_playback_aclk)) then - qsfp4_axis_aresetn_r <= qsfp4_axis_aresetn_r(1 to 15) & '1'; - end if; - end process; - - qsfp4_playback_aresetn <= qsfp4_axis_aresetn_r(0); - - --- - process(rx_device_clk_1) - begin - if (rising_edge(rx_device_clk_1)) then - adc_rx_tdata_128b <= adc_rx_tdata_128b + x"0003_0002_0001_0004_0005_0006_0007_0008"; - end if; - end process; - --- - process(qsfp1_capture_aclk) - begin - if (rising_edge(qsfp1_capture_aclk)) then - qsfp1_axis_aresetn_r <= qsfp1_axis_aresetn_r(1 to 15) & '1'; - end if; - end process; - - qsfp1_capture_aresetn <= qsfp1_axis_aresetn_r(0); - - adc_rx_tvalid_128b_ena <= adc_rx_tvalid_128b and qsfp1_capture_rx_data_ready; - - i_qsfp4_playback_intfc : entity work.qsfp4_playback_intfc - port map ( - rx_device_clk_in => rx_device_clk_1, - rx_device_clk_aresetn_in => rx_device_clk_aresetn, - rx_tdata_128b_in => adc_rx_tdata_128b, - rx_tvalid_128b_in => adc_rx_tvalid_128b_ena, - rx_tready_128b_out => adc_rx_tready_128b, - rx_tvalid_128b_cnt_out => adc_rx_tvalid_128b_cnt, - rx_tvalid_128b_en_cnt_out => open, - playback_data_path_enable_n_in => playback_data_path_enable_n, - - qsfp4_playback_aclk_in => qsfp4_playback_aclk, - qsfp4_playback_aresetn_in => qsfp4_playback_aresetn, - qsfp4_playback_tdata_240b_out => qsfp4_playback_tdata_240b, - qsfp4_playback_tvalid_240b_out => qsfp4_playback_tvalid_240b, - qsfp4_playback_tready_240b_in => qsfp4_playback_tready_240b, - qsfp4_playback_tvalid_240b_cnt_out => open, - - cnt_reset_in => '0' - ); - ---/////////////////////////////// - - qsfp1_capture_aclk <= qsfp4_playback_aclk; -- - qsfp1_capture_tdata_240b <= qsfp4_playback_tdata_240b; -- - qsfp1_capture_tvalid_240b <= qsfp4_playback_tvalid_240b; -- - - ---/////////////////////////////// ---// ****>>>> FROM QSFP1 CAPTURE INTERFACE - i_qsfp1_capture_intfc : entity work.qsfp1_capture_intfc - port map ( - qsfp1_capture_aclk_in => qsfp1_capture_aclk, - qsfp1_capture_aresetn_in => qsfp1_capture_aresetn, - qsfp1_capture_tdata_240b_in => qsfp1_capture_tdata_240b, - qsfp1_capture_tvalid_240b_in => qsfp1_capture_tvalid_240b, - qsfp1_capture_tvalid_240b_cnt_out => open, - qsfp1_capture_fifo_aempty_512b_cnt_out => open, - qsfp1_capture_iq_240b_to_512b_overflow_cnt_out => open, - - qsfp1_capture_rx_data_ready_out => qsfp1_capture_rx_data_ready, - qsfp1_capture_rx_data_ready_cnt_out => open, - - tx_device_clk_in => tx_device_clk_1, - tx_device_clk_aresetn_in => tx_device_clk_aresetn, - tx_tdata_128b_out => tx_tdata_128b, -- out - tx_tvalid_128b_out => tx_tvalid_128b, -- out - tx_tready_128b_in => tx_tready_128b, -- in - tx_tvalid_128b_cnt_out => open, - - cnt_reset_in => '0' - ); - - - - -- Stimulus process - stim_proc: process - begin - - wait until rx_device_clk_aresetn = '1'; - - wait for 200 ns; - - - wait until rising_edge(rx_device_clk_1); - adc_rx_tvalid_128b <= '1'; - - wait for 500 ns; - wait until rising_edge(rx_device_clk_1); - playback_data_path_enable_n <= '0'; - - wait for 5 us; - wait until rising_edge(qsfp4_playback_aclk); - playback_data_path_enable_n <='0'; - - wait for 5 us; - wait until rising_edge(qsfp4_playback_aclk); - qsfp4_playback_tready_240b <='1'; - - wait; -- wait here forever - end process; - - -end; diff --git a/sim/tb_cap_plybk_behav.wcfg b/sim/tb_cap_plybk_behav.wcfg deleted file mode 100644 index 1f35420..0000000 --- a/sim/tb_cap_plybk_behav.wcfg +++ /dev/null @@ -1,141 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - rx_device_clk_1 - rx_device_clk_1 - - - rx_device_clk_aresetn_r[0:15] - rx_device_clk_aresetn_r[0:15] - - - rx_device_clk_aresetn - rx_device_clk_aresetn - - - qsfp4_playback_aclk - qsfp4_playback_aclk - - - qsfp4_axis_aresetn_r[0:15] - qsfp4_axis_aresetn_r[0:15] - - - qsfp4_playback_aresetn - qsfp4_playback_aresetn - - - adc_rx_tdata_128b[127:0] - adc_rx_tdata_128b[127:0] - - - adc_rx_tvalid_128b - adc_rx_tvalid_128b - - - adc_rx_tready_128b - adc_rx_tready_128b - - - adc_rx_tdata_128b_overflow - adc_rx_tdata_128b_overflow - - - rx_tvalid_128b_cnt_out[31:0] - rx_tvalid_128b_cnt_out[31:0] - - - rx_tvalid_128b_en_cnt_out[31:0] - rx_tvalid_128b_en_cnt_out[31:0] - - - qsfp4_playback_tdata_240b[239:0] - qsfp4_playback_tdata_240b[239:0] - - - qsfp4_playback_tvalid_240b - qsfp4_playback_tvalid_240b - - - qsfp4_playback_tready_240b - qsfp4_playback_tready_240b - - - qsfp4_playback_tvalid_240b_cnt_out[31:0] - qsfp4_playback_tvalid_240b_cnt_out[31:0] - - - playback_data_path_enable_n - playback_data_path_enable_n - - - qsfp1_capture_tdata_240b[239:0] - qsfp1_capture_tdata_240b[239:0] - - - qsfp1_capture_tvalid_240b - qsfp1_capture_tvalid_240b - - - qsfp1_capture_rx_data_ready - qsfp1_capture_rx_data_ready - - - qsfp1_capture_rx_data_ready_cnt_out[31:0] - qsfp1_capture_rx_data_ready_cnt_out[31:0] - - - qsfp1_capture_fifo_aempty_512b_cnt_out[31:0] - qsfp1_capture_fifo_aempty_512b_cnt_out[31:0] - - - qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0] - qsfp1_capture_iq_240b_to_512b_overflow_cnt_out[31:0] - - - tx_tdata_128b[127:0] - tx_tdata_128b[127:0] - - - tx_tvalid_128b - tx_tvalid_128b - - - tx_tready_128b - tx_tready_128b - - - qsfp1_tready_512b - qsfp1_tready_512b - - - qsfp1_tready_512b_pipe - qsfp1_tready_512b_pipe - - - qsfp1_tready_128b - qsfp1_tready_128b - - diff --git a/sim/test_bench.vhd b/sim/test_bench.vhd deleted file mode 100644 index 5fbe485..0000000 --- a/sim/test_bench.vhd +++ /dev/null @@ -1,188 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 16:53:22 03/24/2017 --- Design Name: --- Module Name: --- Project Name: xem7350 --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: dac_interface --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE IEEE.STD_LOGIC_arith.ALL; -USE IEEE.STD_LOGIC_unsigned.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - -entity test_bench is -end test_bench; - -architecture behavior of test_bench is - - constant C_M_AXI_DATA_WIDTH : integer := 32; - constant C_M_AXI_ADDR_WIDTH : integer := 32; - - -- Clock period definitions - constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz - constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz - constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz - constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz - constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; - - signal clk_125 : std_logic := '0'; - signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_125_reset : std_logic; - - signal clk_250 : std_logic := '0'; - signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0'); - signal clk_250_areset : std_logic; - - signal tx_device_clk_1 : std_logic := '0'; - signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal tx_device_clk_aresetn : std_logic; - - signal rx_device_clk_1 : std_logic := '0'; - signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal rx_device_clk_aresetn : std_logic; - signal rx_device_clk_areset : std_logic; - - signal qsfp4_axis_aclk : std_logic := '0'; - signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp4_axis_aresetn : std_logic; - - signal qsfp1_axis_aclk : std_logic := '0'; - signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); - signal qsfp1_axis_aresetn : std_logic; - - --- - signal tick_1ms : std_logic; - - signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - - -begin - - clk_125 <= not clk_125 after CLK_125_PERIOD/2; - clk_250 <= not clk_250 after CLK_250_PERIOD/2; - tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2; - rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2; - - qsfp4_axis_aclk <= not qsfp4_axis_aclk after QSFP4_AXIS_ACLK_PERIOD/2; - qsfp1_axis_aclk <= not qsfp1_axis_aclk after QSFP1_AXIS_ACLK_PERIOD/2; - --- - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_125_reset <= not clk_125_aresetn(0); --- - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1'; - end if; - end process; - - clk_250_areset <= not clk_250_aresetn(0); --- - process(tx_device_clk_1) - begin - if (rising_edge(tx_device_clk_1)) then - tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1'; - end if; - end process; - - tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0); - - ------------------------------------------------- - i_tick_gen : entity work.tick_gen - generic map ( - CLOCK_SPEED_MHZ => 125 - ) - port map ( - clk_in => clk_125, - - tick_1us_out => open, - tick_1ms_out => tick_1ms, - tick_500ms_out => open, - tick_750ms_out => open, - tick_1s_out => open, - - prog_us_tick_rate_in => x"0000_0000", - prog_us_tick_out => open, - - reset_in => clk_125_reset - ); - - - process(clk_125) - begin - if (rising_edge(clk_125)) then - clk_125_tick_1ms_r <= clk_125_tick_1ms_r(1 to 2) & tick_1ms; - if (clk_125_tick_1ms_r(0 to 1) = "01") then - clk_125_freq_r <= clk_125_cnt_r; - clk_125_cnt_r <= (others => '0'); - else - clk_125_cnt_r <= clk_125_cnt_r + 1; - end if; - end if; - end process; - - process(clk_250) - begin - if (rising_edge(clk_250)) then - clk_250_tick_1ms_r <= clk_250_tick_1ms_r(1 to 2) & tick_1ms; - if (clk_250_tick_1ms_r(0 to 1) = "01") then - clk_250_freq_r <= clk_250_cnt_r; - clk_250_cnt_r <= (others => '0'); - else - clk_250_cnt_r <= clk_250_cnt_r + 1; - end if; - end if; - end process; - - - - -end;