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nsantana
2026-07-18 14:19:50 -04:00
parent 9fc4cf25a4
commit 494ada36f0
16 changed files with 0 additions and 10021 deletions
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.dcp
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_clocks.xdc
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###############################################################################################################
# Core-Level Timing Constraints for axi_register_slice Component "axis_register_slice_32"
###############################################################################################################
#
# This component is not configured in a multi-SLR crossing or auto-pipelining mode.
# No timing core-level constraints are needed.
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_ooc.xdc
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# (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of AMD and is protected under U.S. and international copyright
# and other intellectual property laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# AMD, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) AMD shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or AMD had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# AMD products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of AMD products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# DO NOT MODIFY THIS FILE.
# #########################################################
#
# This XDC is used only in OOC mode for synthesis, implementation
#
# #########################################################
create_clock -period 100 -name aclk [get_ports aclk]
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.v
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_sim_netlist.vhdl
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.v
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// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
// Date : Thu Apr 23 10:08:03 2026
// Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
// Command : write_verilog -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
// axis_register_slice_32_ axis_register_slice_32_stub.v
// Design : axis_register_slice_32
// Purpose : Stub declaration of top-level module interface
// Device : xczu19eg-ffvc1760-2-i
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
module axis_register_slice_32(aclk, aresetn, s_axis_tvalid, s_axis_tready,
s_axis_tdata, m_axis_tvalid, m_axis_tready, m_axis_tdata)
/* synthesis syn_black_box black_box_pad_pin="aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]" */
/* synthesis syn_force_seq_prim="aclk" */;
input aclk /* synthesis syn_isclock = 1 */;
input aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [31:0]s_axis_tdata;
output m_axis_tvalid;
input m_axis_tready;
output [31:0]m_axis_tdata;
endmodule
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32_stub.vhdl
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-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
-- Date : Thu Apr 23 10:08:04 2026
-- Host : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top axis_register_slice_32 -prefix
-- axis_register_slice_32_ axis_register_slice_32_stub.vhdl
-- Design : axis_register_slice_32
-- Purpose : Stub declaration of top-level module interface
-- Device : xczu19eg-ffvc1760-2-i
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity axis_register_slice_32 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end axis_register_slice_32;
architecture stub of axis_register_slice_32 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[31:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2";
begin
end;
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_1.vh
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// (c) Copyright 2011-2013, 2023 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
// Generic Functions used by AXIS-Interconnect and Infrastrucutre Modules
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Global Parameters:
//
// Functions:
// f_clogb2
// f_gcd
// f_lcm
// f_get_tdata_indx
// f_get_tstrb_indx
// f_get_tkeep_indx
// f_get_tlast_indx
// f_get_tid_indx
// f_get_tdest_indx
// f_get_tuser_indx
// f_payload_width
// Tasks:
// t_display_tdata_error
//--------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// BEGIN Global Parameters
///////////////////////////////////////////////////////////////////////////////
// Define Signal Set indices
localparam G_INDX_SS_TREADY = 0;
localparam G_INDX_SS_TDATA = 1;
localparam G_INDX_SS_TSTRB = 2;
localparam G_INDX_SS_TKEEP = 3;
localparam G_INDX_SS_TLAST = 4;
localparam G_INDX_SS_TID = 5;
localparam G_INDX_SS_TDEST = 6;
localparam G_INDX_SS_TUSER = 7;
localparam G_MASK_SS_TREADY = 32'h1 << G_INDX_SS_TREADY;
localparam G_MASK_SS_TDATA = 32'h1 << G_INDX_SS_TDATA;
localparam G_MASK_SS_TSTRB = 32'h1 << G_INDX_SS_TSTRB;
localparam G_MASK_SS_TKEEP = 32'h1 << G_INDX_SS_TKEEP;
localparam G_MASK_SS_TLAST = 32'h1 << G_INDX_SS_TLAST;
localparam G_MASK_SS_TID = 32'h1 << G_INDX_SS_TID ;
localparam G_MASK_SS_TDEST = 32'h1 << G_INDX_SS_TDEST;
localparam G_MASK_SS_TUSER = 32'h1 << G_INDX_SS_TUSER;
// Task DRC error levels
localparam G_TASK_SEVERITY_ERR = 2;
localparam G_TASK_SEVERITY_WARNING = 1;
localparam G_TASK_SEVERITY_INFO = 0;
///////////////////////////////////////////////////////////////////////////////
// BEGIN Functions
///////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
// Calculates the Greatest Common Divisor between two integers using the
// euclidean algorithm.
function automatic integer f_gcd (
input integer a,
input integer b
);
begin : main
if (a == 0) begin
f_gcd = b;
end else if (b == 0) begin
f_gcd = a;
end else if (a > b) begin
f_gcd = f_gcd(a % b, b);
end else begin
f_gcd = f_gcd(a, b % a);
end
end
endfunction
// Calculates the Lowest Common Denominator between two integers
function integer f_lcm (
input integer a,
input integer b
);
begin : main
f_lcm = ( a / f_gcd(a, b)) * b;
end
endfunction
// Returns back the index to the TDATA portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tdata_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
f_get_tdata_indx = 0;
end
endfunction
// Returns back the index to the tstrb portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tstrb_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tdata_indx(DAW, IDW, DEW, USW, SST);
// If TDATA exists, then add its width to its base to get the tstrb index
f_get_tstrb_indx = SST[G_INDX_SS_TDATA] ? cur_indx + DAW : cur_indx;
end
endfunction
// Returns back the index to the tkeep portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tkeep_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tstrb_indx(DAW, IDW, DEW, USW, SST);
f_get_tkeep_indx = SST[G_INDX_SS_TSTRB] ? cur_indx + DAW/8 : cur_indx;
end
endfunction
// Returns back the index to the tlast portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tlast_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tkeep_indx(DAW, IDW, DEW, USW, SST);
f_get_tlast_indx = SST[G_INDX_SS_TKEEP] ? cur_indx + DAW/8 : cur_indx;
end
endfunction
// Returns back the index to the tid portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tid_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tlast_indx(DAW, IDW, DEW, USW, SST);
f_get_tid_indx = SST[G_INDX_SS_TLAST] ? cur_indx + 1 : cur_indx;
end
endfunction
// Returns back the index to the tdest portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tdest_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tid_indx(DAW, IDW, DEW, USW, SST);
f_get_tdest_indx = SST[G_INDX_SS_TID] ? cur_indx + IDW : cur_indx;
end
endfunction
// Returns back the index to the tuser portion of TPAYLOAD, returns 0 if the
// signal is not enabled.
function integer f_get_tuser_indx (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tdest_indx(DAW, IDW, DEW, USW, SST);
f_get_tuser_indx = SST[G_INDX_SS_TDEST] ? cur_indx + DEW : cur_indx;
end
endfunction
// Payload is the sum of all the AXIS signals present except for
// TREADY/TVALID
function integer f_payload_width (
input integer DAW, // TDATA Width
input integer IDW, // TID Width
input integer DEW, // TDEST Width
input integer USW, // TUSER Width
input [31:0] SST // Signal Set
);
begin : main
integer cur_indx;
cur_indx = f_get_tuser_indx(DAW, IDW, DEW, USW, SST);
f_payload_width = SST[G_INDX_SS_TUSER] ? cur_indx + USW : cur_indx;
// Ensure that the return value is never less than 1
f_payload_width = (f_payload_width < 1) ? 1 : f_payload_width;
end
endfunction
task t_check_tdata_width(
input integer data_width,
input [8*80-1:0] var_name,
input [8*80-1:0] inst_name,
input integer severity_lvl,
output integer ret_val
);
// Severity levels:
// 0 = INFO
// 1 = WARNING
// 2 = ERROR
begin : t_check_tdata_width
if (data_width%8 != 0) begin
// 000 1 2 3 4 5 6 7 8
// 012 0 0 0 0 0 0 0 0
if (severity_lvl >= 2) begin
$display("ERROR: %m::%s", inst_name);
end else if (severity_lvl == 1) begin
$display("WARNING: %m::%s", inst_name);
end else begin
$display("INFO: %m::%s", inst_name);
end
$display(" Parameter %s (%2d) must be a multiple of 8.", var_name, data_width);
$display(" AXI4-Stream data width is only defined for byte multiples. See the ");
$display(" AMBA4 AXI4-Stream Protocol Specification v1.0 Section 2.1 for more");
$display(" information.");
ret_val = 1;
end else begin
ret_val = 0;
end
end
endtask
task t_check_tuser_width(
input integer tuser_width,
input [8*80-1:0] tuser_name,
input integer tdata_width,
input [8*80-1:0] tdata_name,
input [8*80-1:0] inst_name,
input integer severity_lvl,
output integer ret_val
);
// Severity levels:
// 0 = INFO
// 1 = WARNING
// 2 = ERROR
begin : t_check_tuser_width
integer tdata_bytes;
tdata_bytes = tdata_width/8;
if ((tuser_width%tdata_bytes) != 0) begin
// 000 1 2 3 4 5 6 7 8
// 012 0 0 0 0 0 0 0 0
if (severity_lvl >= 2) begin
$display("ERROR: %m::%s", inst_name);
end else if (severity_lvl == 1) begin
$display("WARNING: %m::%s", inst_name);
end else begin
$display("INFO: %m::%s", inst_name);
end
$display(" Parameter %s == %2d is not the recommended value of 'an integer ", tuser_name, tuser_width);
$display(" multiple of the width of the interface (%s == %2d) in bytes.' AXI4-Stream", tdata_name, tdata_width);
$display(" TUSER width in this module is only defined when the TUSER is the");
$display(" recommended value. See the AMBA4 AXI4-Stream Protocol Specification v1.0");
$display(" Section 2.1, 2.3.3 and 2.8 for more information. ");
ret_val = 1;
end else begin
ret_val = 0;
end
end
endtask
ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/hdl/axis_infrastructure_v1_1_vl_rfs.v
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ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/synth/axis_register_slice_32.v
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of AMD and is protected under U.S. and international copyright
// and other intellectual property laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// AMD, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) AMD shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or AMD had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// AMD products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of AMD products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_register_slice:1.1
// IP Revision: 29
(* X_CORE_INFO = "axis_register_slice_v1_1_29_axis_register_slice,Vivado 2023.2" *)
(* CHECK_LICENSE_TYPE = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{}" *)
(* CORE_GENERATION_INFO = "axis_register_slice_32,axis_register_slice_v1_1_29_axis_register_slice,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_register_slice,x_ipVersion=1.1,x_ipCoreRevision=29,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynquplus,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000000011,C_REG_CONFIG=8,C_NUM_SLR_CROSSINGS=0,C_PIPELINES_MASTER=0,C_PIPELINES_SLAVE=0,C_PIPELINES_MIDDLE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module axis_register_slice_32 (
aclk,
aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 10000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
axis_register_slice_v1_1_29_axis_register_slice #(
.C_FAMILY("zynquplus"),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET(32'B00000000000000000000000000000011),
.C_REG_CONFIG(8),
.C_NUM_SLR_CROSSINGS(0),
.C_PIPELINES_MASTER(0),
.C_PIPELINES_SLAVE(0),
.C_PIPELINES_MIDDLE(0)
) inst (
.aclk(aclk),
.aclk2x(1'H0),
.aresetn(aresetn),
.aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(4'HF),
.s_axis_tkeep(4'HF),
.s_axis_tlast(1'H1),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser()
);
endmodule