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added CMAC interface out of QSFP3

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This commit is contained in:
nsantana
2026-07-17 15:55:55 -04:00
parent 69be245f2a
commit 3f25b73be7
20 changed files with 2869 additions and 524 deletions
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source/system_top.v
+320 -128
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@@ -37,8 +37,8 @@
module system_top #(
parameter FPGA_REVISION_DATE = 32'h05282026,
parameter MINOR_REV = 8'h04,
parameter FPGA_REVISION_DATE = 32'h07162026,
parameter MINOR_REV = 8'h01,
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
@@ -69,6 +69,35 @@ module system_top #(
output QSFP1_TX3_P,
output QSFP1_TX4_N,
output QSFP1_TX4_P,
//
input QSFP2_INTL_LS,
input QSFP2_MODPRSL_LS,
output QSFP2_RESETL_LS,
input QSFP2_SI570_CLOCK_N,//CLK3_N
input QSFP2_SI570_CLOCK_P,
//
input QSFP3_INTL_LS,
input QSFP3_MODPRSL_LS,
output QSFP3_RESETL_LS,
input QSFP3_RX1_N,
input QSFP3_RX1_P,
input QSFP3_RX2_N,
input QSFP3_RX2_P,
input QSFP3_RX3_N,
input QSFP3_RX3_P,
input QSFP3_RX4_N,
input QSFP3_RX4_P,
input QSFP3_SI570_CLOCK_N,//CLK1_N
input QSFP3_SI570_CLOCK_P,
output QSFP3_TX1_N,
output QSFP3_TX1_P,
output QSFP3_TX2_N,
output QSFP3_TX2_P,
output QSFP3_TX3_N,
output QSFP3_TX3_P,
output QSFP3_TX4_N,
output QSFP3_TX4_P,
//
input QSFP4_INTL_LS,
input QSFP4_MODPRSL_LS,
output QSFP4_RESETL_LS,
@@ -90,14 +119,7 @@ module system_top #(
output QSFP4_TX3_P,
output QSFP4_TX4_N,
output QSFP4_TX4_P,
input QSFP2_SI570_CLOCK_N,//CLK3_N
input QSFP2_SI570_CLOCK_P,
input QSFP3_SI570_CLOCK_N,//CLK1_N
input QSFP3_SI570_CLOCK_P,
//
inout pll_scl,
inout pll_sda,
@@ -220,13 +242,13 @@ module system_top #(
wire qsfp1_capture_tvalid_240b;
wire [31:0] qsfp1_capture_tvalid_240b_cnt;
wire [31:0] qsfp1_tx_fifo_128_aempty_cnt;
wire [31:0] qsfp1_fifo_128_aempty_cnt;
wire [127:0] tx_tdata_128b;
wire tx_tvalid_128b;
wire tx_tready_128b;
wire [127:0] qsfp1_tdata_128b;
wire qsfp1_tvalid_128b;
wire qsfp1_tready_128b;
wire [31:0] qsfp1_tx_fifo_tvalid_128b_cnt;
wire [31:0] qsfp1_fifo_tvalid_128b_cnt;
wire qsfp1_capture_rx_data_ready;
wire [31:0] qsfp1_capture_rx_data_ready_cnt;
@@ -253,38 +275,7 @@ module system_top #(
wire [31:0] slv_reg9;
wire [31:0] slv_reg10;
wire [31:0] slv_reg21;
wire [31:0] slv_reg22;
wire [31:0] slv_reg23;
wire [31:0] slv_reg24;
wire [31:0] slv_reg25;
wire [31:0] slv_reg26;
wire [31:0] slv_reg27;
wire [31:0] slv_reg28;
wire [31:0] slv_reg29;
wire [31:0] slv_reg30;
wire [31:0] slv_reg31;
wire [31:0] slv_reg32;
wire [31:0] slv_reg33;
wire [31:0] slv_reg34;
wire [31:0] slv_reg35;
wire [31:0] slv_reg36;
wire [31:0] slv_reg37;
wire [31:0] slv_reg38;
wire [31:0] slv_reg39;
wire [31:0] slv_reg40;
wire [31:0] slv_reg41;
wire [31:0] slv_reg42;
wire [31:0] slv_reg43;
wire [31:0] slv_reg44;
wire [31:0] slv_reg45;
wire [31:0] slv_reg46;
wire [31:0] slv_reg47;
wire [31:0] slv_reg48;
wire [1:0] dac_src_data_sel;
wire [2:0] dac_src_data_sel;
wire chan1to4_mode_sel;
wire qsfp4_playback_path_data_enable_n;
@@ -292,9 +283,6 @@ module system_top #(
wire qsfp2_clk;
wire qsfp2_clk_bufg;
wire qsfp3_clk;
wire qsfp3_clk_bufg;
wire clk_100;
wire clk_100_aresetn;
wire [31:0] M11_AXI_0_araddr;
@@ -337,6 +325,26 @@ module system_top #(
wire [3:0] M12_AXI_0_wstrb;
wire M12_AXI_0_wvalid;
wire [31:0] M13_AXI_0_araddr;
wire [2:0] M13_AXI_0_arprot;
wire M13_AXI_0_arready;
wire M13_AXI_0_arvalid;
wire [31:0] M13_AXI_0_awaddr;
wire [2:0] M13_AXI_0_awprot;
wire M13_AXI_0_awready;
wire M13_AXI_0_awvalid;
wire M13_AXI_0_bready;
wire [1:0] M13_AXI_0_bresp;
wire M13_AXI_0_bvalid;
wire [31:0] M13_AXI_0_rdata;
wire M13_AXI_0_rready;
wire [1:0] M13_AXI_0_rresp;
wire M13_AXI_0_rvalid;
wire [31:0] M13_AXI_0_wdata;
wire M13_AXI_0_wready;
wire [3:0] M13_AXI_0_wstrb;
wire M13_AXI_0_wvalid;
wire sda_i;
wire sda_o;
wire sda_t;
@@ -357,6 +365,10 @@ module system_top #(
wire m1_dds_pulse_tvalid_128b;
wire m1_dds_pulse_tready_128b;
wire [127:0] m1_dds_pulse_fifo_tdata_128b;
wire m1_dds_pulse_fifo_tvalid_128b;
wire m1_dds_pulse_fifo_tready_128b;
wire [127:0] fiber_tx_tdata_128b;
wire fiber_tx_tvalid_128b;
wire fiber_tx_tready_128b;
@@ -369,6 +381,47 @@ module system_top #(
wire qsfp1_capture_en_n;
wire qsfp1_capture_rst;
wire [3:0] cmac_gt_0_grx_n;
wire [3:0] cmac_gt_0_grx_p;
wire [3:0] cmac_gt_0_gtx_n;
wire [3:0] cmac_gt_0_gtx_p;
wire cmac_refclk_0_clk_n;
wire cmac_refclk_0_clk_p;
wire cmac_tx_intfc_en;
wire cmac_rx_intfc_en;
////
wire [511:0] cmac_0_tx_tdata_512b;
wire cmac_0_tx_tvalid_512b;
wire cmac_0_tx_tvalid_512b_en;
wire cmac_0_tx_tready_512b;
wire cmac_0_tx_tready_512b_en;
reg [31:0] cmac_0_tx_tvalid_512b_cnt_r = 32'h0;
wire [511:0] cmac_0_rx_tdata_512b;
wire cmac_0_rx_tvalid_512b;
wire cmac_0_rx_tvalid_512b_en;
wire cmac_0_rx_tready_512b;
wire cmac_0_rx_tready_512b_en;
reg [31:0] cmac_0_rx_tvalid_512b_cnt_r = 32'h0;
wire [127:0] cmac_0_rx_tdata_128b;
wire cmac_0_rx_tvalid_128b;
wire cmac_0_rx_tready_128b;
wire [127:0] dds2cmac_fifo_tdata_128b;
wire dds2cmac_fifo_tvalid_128b;
wire dds2cmac_fifo_tready_128b;
wire dds_out_dest_sel;
wire cmac_tx_src_data_sel;
wire [511:0] adc_tdata_512b;
wire adc_tvalid_512b;
wire adc_tready_512b;
////////////////////////////////////////////////////////////////
// instantiations
@@ -472,27 +525,6 @@ module system_top #(
.DIV (3'b000),
.O (qsfp2_clk_bufg)
);
//////////
IBUFDS_GTE4 i_ibufds_qsfp3 (
.I (QSFP3_SI570_CLOCK_P),
.IB (QSFP3_SI570_CLOCK_N),
.CEB (1'b0),
.O (),
.ODIV2 (qsfp3_clk)
);
BUFG_GT i_bufgt_qsfp3 (
.I (qsfp3_clk),
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'b000),
.O (qsfp3_clk_bufg)
);
// assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
@@ -736,6 +768,26 @@ module system_top #(
.M12_AXI_0_wstrb (M12_AXI_0_wstrb),
.M12_AXI_0_wvalid (M12_AXI_0_wvalid),
.M13_AXI_0_araddr (M13_AXI_0_araddr),
.M13_AXI_0_arprot (M13_AXI_0_arprot),
.M13_AXI_0_arready (M13_AXI_0_arready),
.M13_AXI_0_arvalid (M13_AXI_0_arvalid),
.M13_AXI_0_awaddr (M13_AXI_0_awaddr),
.M13_AXI_0_awprot (M13_AXI_0_awprot),
.M13_AXI_0_awready (M13_AXI_0_awready),
.M13_AXI_0_awvalid (M13_AXI_0_awvalid),
.M13_AXI_0_bready (M13_AXI_0_bready),
.M13_AXI_0_bresp (M13_AXI_0_bresp),
.M13_AXI_0_bvalid (M13_AXI_0_bvalid),
.M13_AXI_0_rdata (M13_AXI_0_rdata),
.M13_AXI_0_rready (M13_AXI_0_rready),
.M13_AXI_0_rresp (M13_AXI_0_rresp),
.M13_AXI_0_rvalid (M13_AXI_0_rvalid),
.M13_AXI_0_wdata (M13_AXI_0_wdata),
.M13_AXI_0_wready (M13_AXI_0_wready),
.M13_AXI_0_wstrb (M13_AXI_0_wstrb),
.M13_AXI_0_wvalid (M13_AXI_0_wvalid),
.Res_0 (), //mxfe_rx_data_offload_s_axis_tready from Rx DMA engine
.pl_clk3_0 (pl_clk3_0),
@@ -781,7 +833,6 @@ module system_top #(
// .sysref_in (sysref),
.ref_clk_div2_in (ref_clk_div2_bufg),
.qsfp2_clk_in (qsfp2_clk_bufg),
.qsfp3_clk_in (qsfp3_clk_bufg),
.pl_clk3_0 (pl_clk3_0),
.QSFP1_INTL_LS (QSFP1_INTL_LS),
@@ -805,6 +856,15 @@ module system_top #(
.QSFP1_TX3_P (QSFP1_TX3_P),
.QSFP1_TX4_N (QSFP1_TX4_N),
.QSFP1_TX4_P (QSFP1_TX4_P),
///////////
.QSFP2_RESETL_LS (QSFP2_RESETL_LS),
.QSFP2_MODPRSL_LS (QSFP2_MODPRSL_LS),
.QSFP2_INTL_LS (QSFP2_INTL_LS),
///////////
.QSFP3_RESETL_LS (QSFP3_RESETL_LS),
.QSFP3_MODPRSL_LS (QSFP3_MODPRSL_LS),
.QSFP3_INTL_LS (QSFP3_INTL_LS),
///////////
.QSFP4_INTL_LS (QSFP4_INTL_LS),
.QSFP4_MODPRSL_LS (QSFP4_MODPRSL_LS),
.QSFP4_RESETL_LS (QSFP4_RESETL_LS),
@@ -842,9 +902,9 @@ module system_top #(
.qsfp1_capture_tvalid_240b_cnt_in (qsfp1_capture_tvalid_240b_cnt),
.qsfp1_capture_overflow_240b_cnt_in (qsfp1_capture_overflow_240b_cnt),
.qsfp1_capture_tvalid_512b_cnt_in (qsfp1_capture_tvalid_512b_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_tx_fifo_128_aempty_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_fifo_128_aempty_cnt),
.qsfp1_capture_rx_data_ready_cnt_in (qsfp1_capture_rx_data_ready_cnt),
.qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_tx_fifo_tvalid_128b_cnt),
.qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_fifo_tvalid_128b_cnt),
.mem_xfer_tx_upload_tvalid_128b_cnt_in (mem_xfer_tx_upload_tvalid_128b_cnt_r),
.dac_tx_tvalid_128b_cnt_in (dac_tx_tvalid_128b_cnt_r),
@@ -853,44 +913,17 @@ module system_top #(
.qsfp4_playback_tvalid_128b_cnt_in (qsfp4_playback_tvalid_128b_cnt),
.qsfp4_playback_tvalid_240b_cnt_in (qsfp4_playback_tvalid_240b_cnt),
.fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r),
.fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r),
.cmac_0_tx_tvalid_512b_cnt_in (cmac_0_tx_tvalid_512b_cnt_r),
.cmac_0_rx_tvalid_512b_cnt_in (cmac_0_rx_tvalid_512b_cnt_r),
.cnt_reset_out (cnt_reset),
.slv_reg9_out (slv_reg9),
.slv_reg10_out (slv_reg10),
.slv_reg21_out (slv_reg21),
.slv_reg22_out (slv_reg22),
.slv_reg23_out (slv_reg23),
.slv_reg24_out (slv_reg24),
.slv_reg25_out (slv_reg25),
.slv_reg26_out (slv_reg26),
.slv_reg27_out (slv_reg27),
.slv_reg28_out (slv_reg28),
.slv_reg29_out (slv_reg29),
.slv_reg30_out (slv_reg30),
.slv_reg31_out (slv_reg31),
.slv_reg32_out (slv_reg32),
.slv_reg33_out (slv_reg33),
.slv_reg34_out (slv_reg34),
.slv_reg35_out (slv_reg35),
.slv_reg36_out (slv_reg36),
.slv_reg37_out (slv_reg37),
.slv_reg38_out (slv_reg38),
.slv_reg39_out (slv_reg39),
.slv_reg40_out (slv_reg40),
.slv_reg41_out (slv_reg41),
.slv_reg42_out (slv_reg42),
.slv_reg43_out (slv_reg43),
.slv_reg44_out (slv_reg44),
.slv_reg45_out (slv_reg45),
.slv_reg46_out (slv_reg46),
.slv_reg47_out (slv_reg47),
.slv_reg48_out (slv_reg48),
.sys_cpu_clk_in (clk_100),
.s00_axi_aresetn (clk_100_aresetn),
.s00_axi_awaddr (M11_AXI_0_awaddr[7:0]),
@@ -918,12 +951,19 @@ module system_top #(
//assign = slv_reg10[3:1];
assign qsfp1_capture_rst = slv_reg10[4];
//assign = slv_reg10[7:5];
assign dac_src_data_sel = slv_reg10[9:8];
//assign = slv_reg10[11:10];
assign dac_src_data_sel = slv_reg10[10:8];
//assign = slv_reg10[11];
assign chan1to4_mode_sel = slv_reg10[12];
//assign = slv_reg10[14:13];
assign qsfp1_capture_en_n = slv_reg10[15];
//assign = slv_reg10[30:16];
//assign = slv_reg10[18:16];
assign cmac_tx_src_data_sel = slv_reg10[19];
//assign = slv_reg10[23:20];
assign dds_out_dest_sel = slv_reg10[24];
//assign = slv_reg10[27:25];
assign cmac_tx_intfc_en = slv_reg10[28];
assign cmac_rx_intfc_en = slv_reg10[29];
//assign = slv_reg10[30];
assign qsfp4_playback_path_data_enable_n = slv_reg10[31];
///////////////////////////////
@@ -942,11 +982,11 @@ module system_top #(
.tx_device_clk_in (tx_device_clk_1),
.tx_device_clk_aresetn_in (tx_device_clk_aresetn),
.tx_fifo_tdata_128b_out (tx_tdata_128b), // out
.tx_fifo_tvalid_128b_out (tx_tvalid_128b), // out
.tx_fifo_tready_128b_in (tx_tready_128b), // in
.qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_tx_fifo_tvalid_128b_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_tx_fifo_128_aempty_cnt),
.tx_fifo_tdata_128b_out (qsfp1_tdata_128b), // out
.tx_fifo_tvalid_128b_out (qsfp1_tvalid_128b), // out
.tx_fifo_tready_128b_in (qsfp1_tready_128b), // in
.qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_fifo_tvalid_128b_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_fifo_128_aempty_cnt),
.qsfp1_capture_en_n_in (qsfp1_capture_en_n),
.qsfp1_capture_rst_in (qsfp1_capture_rst),
@@ -957,17 +997,15 @@ module system_top #(
//// to DAC - data source from DMA Tx axis data, QSFP1 and ADC_INTFC
/////////////////////////////////////////////
axis_mux_128b i_dac_axis_mux_128b (
.aclk (tx_device_clk_1), // input
.aresetn (tx_device_clk_aresetn), // input
.aselect (dac_src_data_sel), // input
.s0_axis_tdata (mem_xfer_tx_upload_tdata_128b), // input
.s0_axis_tvalid (mem_xfer_tx_upload_tvalid_128b), // input
.s0_axis_tready (mem_xfer_tx_upload_tready_128b), // output
.s1_axis_tdata (tx_tdata_128b), // input
.s1_axis_tvalid (tx_tvalid_128b), // input
.s1_axis_tready (tx_tready_128b), // output
.s1_axis_tdata (qsfp1_tdata_128b), // input
.s1_axis_tvalid (qsfp1_tvalid_128b), // input
.s1_axis_tready (qsfp1_tready_128b), // output
.s2_axis_tdata (adc_loopback_tdata_128b_mux), // input
.s2_axis_tvalid (adc_loopback_tvalid_128b), // input
@@ -977,6 +1015,10 @@ module system_top #(
.s3_axis_tvalid (m0_dds_pulse_tvalid_128b), // input
.s3_axis_tready (m0_dds_pulse_tready_128b), // output
.s4_axis_tdata (cmac_0_rx_tdata_128b), // input
.s4_axis_tvalid (cmac_0_rx_tvalid_128b), // input
.s4_axis_tready (cmac_0_rx_tready_128b), // output
.m_axis_tdata (dac_tx_tdata_128b), // output
.m_axis_tvalid (dac_tx_tvalid_128b), // output
.m_axis_tready (dac_tx_tready_128b) // input
@@ -1004,14 +1046,28 @@ module system_top #(
.s_axis_tready (m1_dds_pulse_tready_128b), // out
.m_axis_aclk (rx_device_clk_1), // in
.m_axis_tdata (dds2fiber_fifo_tdata_128b), // out
.m_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out
.m_axis_tready (dds2fiber_fifo_tready_128b) // in
.m_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // out
.m_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // out
.m_axis_tready (m1_dds_pulse_fifo_tready_128b) // in
);
axis_demux_128b i_axis_demux_128b (
.aselect (dds_out_dest_sel), // in
.s_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // in
.s_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // in
.s_axis_tready (m1_dds_pulse_fifo_tready_128b), // out
.m0_axis_tdata (dds2fiber_fifo_tdata_128b), // out
.m0_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out
.m0_axis_tready (dds2fiber_fifo_tready_128b), // in
.m1_axis_tdata (dds2cmac_fifo_tdata_128b), // out
.m1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // out
.m1_axis_tready (dds2cmac_fifo_tready_128b) // in
);
axis_mux_s2_128b i_axis_mux_s2_128b (
.aclk (rx_device_clk_1), // input
.aresetn (rx_device_clk_aresetn), // input
.aselect (fiber_tx_src_data_sel), // input
.s0_axis_tdata (adc_rx_tdata_128b), // input
@@ -1151,6 +1207,145 @@ module system_top #(
.s00_axi_rready (M12_AXI_0_rready)
);
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
assign cmac_refclk_0_clk_p = QSFP3_SI570_CLOCK_P;
assign cmac_refclk_0_clk_n = QSFP3_SI570_CLOCK_N;
assign cmac_gt_0_grx_p[0] = QSFP3_RX1_P;
assign cmac_gt_0_grx_n[0] = QSFP3_RX1_N;
assign cmac_gt_0_grx_p[1] = QSFP3_RX2_P;
assign cmac_gt_0_grx_n[1] = QSFP3_RX2_N;
assign cmac_gt_0_grx_p[2] = QSFP3_RX3_P;
assign cmac_gt_0_grx_n[2] = QSFP3_RX3_N;
assign cmac_gt_0_grx_p[3] = QSFP3_RX4_P;
assign cmac_gt_0_grx_n[3] = QSFP3_RX4_N;
assign QSFP3_TX1_P = cmac_gt_0_gtx_p[0];
assign QSFP3_TX1_N = cmac_gt_0_gtx_n[0];
assign QSFP3_TX2_P = cmac_gt_0_gtx_p[1];
assign QSFP3_TX2_N = cmac_gt_0_gtx_n[1];
assign QSFP3_TX3_P = cmac_gt_0_gtx_p[2];
assign QSFP3_TX3_N = cmac_gt_0_gtx_n[2];
assign QSFP3_TX4_P = cmac_gt_0_gtx_p[3];
assign QSFP3_TX4_N = cmac_gt_0_gtx_n[3];
raw_eth_wrapper i_raw_eth_cmac_0 (
.clk_100_0 (clk_100),
.clk_100_reset_0 (clk_100_areset),
.cmac_gt_0_grx_n (cmac_gt_0_grx_n), //in
.cmac_gt_0_grx_p (cmac_gt_0_grx_p), //in
.cmac_gt_0_gtx_n (cmac_gt_0_gtx_n), //out
.cmac_gt_0_gtx_p (cmac_gt_0_gtx_p), //out
.cmac_refclk_0_clk_n (cmac_refclk_0_clk_n),
.cmac_refclk_0_clk_p (cmac_refclk_0_clk_p),
.m_axis_aclk (tx_device_clk_1),
.m_axis_aresetn (tx_device_clk_aresetn),
.m_axis_tdata (cmac_0_rx_tdata_512b), // out
.m_axis_tvalid (cmac_0_rx_tvalid_512b), // out
.m_axis_tready (cmac_0_rx_tready_512b_en), // in
.axil_clk_0 (clk_100),
.axil_resetn_0 (clk_100_aresetn),
.s_axil_0_awaddr (M13_AXI_0_awaddr),
.s_axil_0_awprot (M13_AXI_0_awprot),
.s_axil_0_awvalid (M13_AXI_0_awvalid),
.s_axil_0_awready (M13_AXI_0_awready),
.s_axil_0_wdata (M13_AXI_0_wdata),
.s_axil_0_wstrb (M13_AXI_0_wstrb),
.s_axil_0_wvalid (M13_AXI_0_wvalid),
.s_axil_0_wready (M13_AXI_0_wready),
.s_axil_0_bresp (M13_AXI_0_bresp),
.s_axil_0_bvalid (M13_AXI_0_bvalid),
.s_axil_0_bready (M13_AXI_0_bready),
.s_axil_0_araddr (M13_AXI_0_araddr),
.s_axil_0_arprot (M13_AXI_0_arprot),
.s_axil_0_arvalid (M13_AXI_0_arvalid),
.s_axil_0_arready (M13_AXI_0_arready),
.s_axil_0_rdata (M13_AXI_0_rdata),
.s_axil_0_rresp (M13_AXI_0_rresp),
.s_axil_0_rvalid (M13_AXI_0_rvalid),
.s_axil_0_rready (M13_AXI_0_rready),
.s_axis_clk (rx_device_clk_1),
.s_axis_aresetn (rx_device_clk_aresetn),
.s_axis_tdata (cmac_0_tx_tdata_512b), // in
.s_axis_tvalid (cmac_0_tx_tvalid_512b_en), // in
.s_axis_tready (cmac_0_tx_tready_512b) // out
);
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b (
.aclk (rx_device_clk_1), // in
.aresetn (rx_device_clk_aresetn), // in
.s_axis_tdata (adc_rx_tdata_128b), // in
.s_axis_tvalid (adc_rx_tvalid_128b), // in
.s_axis_tready ( ), // out
.m_axis_tdata (adc_tdata_512b), // out
.m_axis_tvalid (adc_tvalid_512b), // out
.m_axis_tready (adc_tready_512b) // in
);
axis_mux_512b i_axis_mux_512b (
.aselect (cmac_tx_src_data_sel), // input
.s0_axis_tdata (adc_tdata_512b), // input
.s0_axis_tvalid (adc_tvalid_512b), // input
.s0_axis_tready (adc_tready_512b), // output
.s1_axis_tdata (dds2cmac_fifo_tdata_128b), // input
.s1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // input
.s1_axis_tready (dds2cmac_fifo_tready_128b), // output
.m_axis_tdata (cmac_0_tx_tdata_512b), // output
.m_axis_tvalid (cmac_0_tx_tvalid_512b), // output
.m_axis_tready (cmac_0_tx_tready_512b_en) // input
);
assign cmac_0_tx_tvalid_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tvalid_512b : 1'b0;
assign cmac_0_tx_tready_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tready_512b : 1'b0;
always @(posedge rx_device_clk_1)
begin
if (rx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
cmac_0_tx_tvalid_512b_cnt_r <= 32'h0;
else if (cmac_0_tx_tvalid_512b_en == 1'b1 && cmac_0_tx_tready_512b_en == 1'b1)
cmac_0_tx_tvalid_512b_cnt_r <= cmac_0_tx_tvalid_512b_cnt_r + 1;
end
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
assign cmac_0_rx_tvalid_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tvalid_512b : 1'b0;
assign cmac_0_rx_tready_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tready_512b : 1'b0;
axis_dwidth_converter_512b_to_128b i_axis_dwidth_converter_512b_to_128b_cmac_0 (
.aclk (tx_device_clk_1), // in
.aresetn (tx_device_clk_aresetn), // in
.s_axis_tdata (cmac_0_rx_tdata_512b), // in
.s_axis_tvalid (cmac_0_rx_tvalid_512b_en), // in
.s_axis_tready (cmac_0_rx_tready_512b), // out
.m_axis_tdata (cmac_0_rx_tdata_128b), // out
.m_axis_tvalid (cmac_0_rx_tvalid_128b), // out
.m_axis_tready (cmac_0_rx_tready_128b) // in
);
always @(posedge tx_device_clk_1)
begin
if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
cmac_0_rx_tvalid_512b_cnt_r <= 32'h0;
else if (cmac_0_rx_tvalid_512b_en == 1'b1 && cmac_0_rx_tready_512b_en == 1'b1)
cmac_0_rx_tvalid_512b_cnt_r <= cmac_0_rx_tvalid_512b_cnt_r + 1;
end
//////////////////////////
si5332_wrapper i_si5332_wrapper (
@@ -1163,10 +1358,7 @@ module system_top #(
.scl_in (scl_i),
.scl_out (scl_o),
.scl_t_out (scl_t),
.qsfp2_clk_in (qsfp2_clk_bufg),
.qsfp3_clk_in (qsfp3_clk_bufg)
.scl_t_out (scl_t)
);
IOBUF i_scl_iobuf (