diff --git a/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260616044053.wic.gz b/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260717174139.wic.gz similarity index 90% rename from bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260616044053.wic.gz rename to bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260717174139.wic.gz index 0abf7e4..533d1d2 100644 Binary files a/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260616044053.wic.gz and b/bin/ardsoc-image-core-ardsoc-z19-zynqmp.rootfs-20260717174139.wic.gz differ diff --git a/bin/boot.bin b/bin/boot.bin index 755943c..f71aacb 100644 Binary files a/bin/boot.bin and b/bin/boot.bin differ diff --git a/constraints/qsfp_constr.xdc b/constraints/qsfp_constr.xdc index ae5078c..63fceda 100644 --- a/constraints/qsfp_constr.xdc +++ b/constraints/qsfp_constr.xdc @@ -1,7 +1,6 @@ ##################################### # -# VCU128 Rev1.0 XDC -# Date: 01/24/2018 +# ALINX Z19 BOARD # #################################### ################################### @@ -37,45 +36,54 @@ set_property PACKAGE_PIN R33 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 130 set_property PACKAGE_PIN R32 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 130 - MGTREFCLK0P_130 CLK1_P # set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 130 - MGTREFCLK1N_130 # set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 130 - MGTREFCLK1P_130 -# set_property PACKAGE_PIN U54 [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130 -# set_property PACKAGE_PIN U50 [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130 -# set_property PACKAGE_PIN T52 [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130 -# set_property PACKAGE_PIN R54 [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130 -# set_property PACKAGE_PIN U53 [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130 -# set_property PACKAGE_PIN U49 [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130 -# set_property PACKAGE_PIN T51 [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130 -# set_property PACKAGE_PIN R53 [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130 -# set_property PACKAGE_PIN V47 [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130 -# set_property PACKAGE_PIN U45 [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130 -# set_property PACKAGE_PIN T47 [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130 -# set_property PACKAGE_PIN R45 [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130 -# set_property PACKAGE_PIN V46 [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130 -# set_property PACKAGE_PIN U44 [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130 -# set_property PACKAGE_PIN T46 [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130 -# set_property PACKAGE_PIN R44 [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130 + set_property PACKAGE_PIN L42 [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130 + set_property PACKAGE_PIN L41 [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130 + set_property PACKAGE_PIN K40 [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130 + set_property PACKAGE_PIN K39 [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130 + set_property PACKAGE_PIN J42 [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130 + set_property PACKAGE_PIN J41 [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130 + set_property PACKAGE_PIN H40 [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130 + set_property PACKAGE_PIN H39 [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130 + + set_property PACKAGE_PIN M35 [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130 + set_property PACKAGE_PIN M34 [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130 + set_property PACKAGE_PIN L37 [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130 + set_property PACKAGE_PIN L36 [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130 + set_property PACKAGE_PIN K35 [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130 + set_property PACKAGE_PIN K34 [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130 + set_property PACKAGE_PIN J37 [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130 + set_property PACKAGE_PIN J36 [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130 + +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_INTL_LS"] ;# +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_RESETL_LS"] ;# +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18 } [get_ports "QSFP3_MODPRSL_LS"] ;# ### J77 set_property PACKAGE_PIN W33 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 129 - MGTREFCLK0N_129 CLK3_N set_property PACKAGE_PIN W32 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 129 - MGTREFCLK0P_129 CLK3_P # set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK1N_129 # set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK1P_129 -# set_property PACKAGE_PIN L54 [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129 -# set_property PACKAGE_PIN K52 [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129 -# set_property PACKAGE_PIN J54 [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129 -# set_property PACKAGE_PIN H52 [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129 -# set_property PACKAGE_PIN L53 [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129 -# set_property PACKAGE_PIN K51 [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129 -# set_property PACKAGE_PIN J53 [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129 -# set_property PACKAGE_PIN H51 [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129 -# set_property PACKAGE_PIN L49 [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129 -# set_property PACKAGE_PIN L45 [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129 -# set_property PACKAGE_PIN K47 [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129 -# set_property PACKAGE_PIN J49 [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129 -# set_property PACKAGE_PIN L48 [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129 -# set_property PACKAGE_PIN L44 [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129 -# set_property PACKAGE_PIN K46 [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129 -# set_property PACKAGE_PIN J48 [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129 +# set_property PACKAGE_PIN R42 [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129 +# set_property PACKAGE_PIN R41 [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129 +# set_property PACKAGE_PIN P40 [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129 +# set_property PACKAGE_PIN P39 [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129 +# set_property PACKAGE_PIN N42 [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129 +# set_property PACKAGE_PIN N41 [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129 +# set_property PACKAGE_PIN M40 [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129 +# set_property PACKAGE_PIN M39 [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129 +# set_property PACKAGE_PIN T35 [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129 +# set_property PACKAGE_PIN T34 [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129 +# set_property PACKAGE_PIN R37 [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129 +# set_property PACKAGE_PIN R36 [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129 +# set_property PACKAGE_PIN P35 [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129 +# set_property PACKAGE_PIN P34 [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129 +# set_property PACKAGE_PIN N37 [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129 +# set_property PACKAGE_PIN N36 [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129 + +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_INTL_LS"] ;# +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_RESETL_LS"] ;# +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18 } [get_ports "QSFP2_MODPRSL_LS"] ;# # set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ; # set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ; # set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ; diff --git a/constraints/timing_constr.xdc b/constraints/timing_constr.xdc index 0f60f39..03977f8 100644 --- a/constraints/timing_constr.xdc +++ b/constraints/timing_constr.xdc @@ -13,8 +13,8 @@ create_clock -name clkin8 -period 2.0 [get_ports clkin8_p] ##create_clock -name sysref2 -period 4.0 [get_ports sysref2_p] # not a clock create_clock -period 2.640 -name QSFP1_SI570_CLOCK_P [get_ports QSFP1_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz -create_clock -period 2.640 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P] -create_clock -period 2.640 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P] +create_clock -period 6.400 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P] +create_clock -period 6.400 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P] create_clock -period 2.640 -name QSFP4_SI570_CLOCK_P [get_ports QSFP4_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz diff --git a/create_proj.tcl b/create_proj.tcl index 1564acc..9afeccc 100644 --- a/create_proj.tcl +++ b/create_proj.tcl @@ -3,7 +3,7 @@ # # create_proj.tcl: Tcl script for re-creating project 'alinx_z19_ad9081' # -# Generated by Vivado on Tue Jun 02 12:21:15 EDT 2026 +# Generated by Vivado on Fri Jul 17 15:54:45 EDT 2026 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -27,61 +27,67 @@ # # 3. The following remote source files that were added to the original project:- # -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_register_slice_128/axis_register_slice_128.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_latency10/dds_latency10.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_register_slice_240/axis_register_slice_240.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_register_slice_512/axis_register_slice_512.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/ad_3w_spi.v" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/ad_iobuf.v" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/axis_mux_128b.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/axis_mux_s2_128b.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/global_types.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_gen_cfg.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/clk_gen_cfg_2.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_cmd_gen.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_2x_top.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_gen.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0_S00_AXI.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/tick_gen.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_wrapper.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_intfc_x4.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/i2c.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/i2c_st.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/qsfp1_capture_intfc.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/qsfp4_playback_intfc.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_clk_configurator.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/Si5332/src/si5332_wrapper.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/source/system_top.v" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_32b/axis_dwidth_converter_512b_to_32b.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/ip_repo/ila_3/ila_3.xci" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/constraints/qsfp_constr.xdc" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/constraints/system_constr.xdc" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/constraints/timing_constr.xdc" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/sim/tb_cap_plybk.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/sim/dds_wrapper_tb.vhd" -# "/home/nsantana/proj_alinx_z19_TEST/ALINX_Z19/alinx_z19_ad9081/sim/test_bench.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_rx.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_packer.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_tx.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_unpacker.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_register_slice_128/axis_register_slice_128.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_latency10/dds_latency10.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/ila_3/ila_3.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_register_slice_240/axis_register_slice_240.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_register_slice_512/axis_register_slice_512.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/ad_3w_spi.v" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/ad_iobuf.v" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_demux_128b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_mux_128b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_mux_512b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/axis_mux_s2_128b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/global_types.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_gen_cfg.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/clk_gen_cfg_2.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_cmd_gen.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_2x_top.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_gen.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0_S00_AXI.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/tick_gen.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_wrapper.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/src/dds_pulse_intfc_x4.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/dds_pulse_intfc_x4_1_0/hdl/dds_pulse_intfc_v1_0.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_dig_iq_encoder_0_0/dig_iq_encoder.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_p_intfc.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/src/dig_iq_x2.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/i2c.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/i2c_st.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/qsfp1_capture_intfc.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/qsfp4_playback_intfc.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_init_fsm.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/si5341_clk_configurator.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/Si5332/src/si5332_wrapper.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/system_top.v" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/ip_repo/axis_dwidth_converter_512b_to_32b/axis_dwidth_converter_512b_to_32b.xci" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/constraints/qsfp_constr.xdc" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/constraints/system_constr.xdc" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/constraints/timing_constr.xdc" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/sim/dds_wrapper_tb.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/sim/tb_cap_plybk.vhd" +# "/home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/sim/test_bench.vhd" # #***************************************************************************************** @@ -89,6 +95,12 @@ proc checkRequiredFiles { origin_dir} { set status true set files [list \ + "[file normalize "$origin_dir/source/eth_flowctrl_rx.vhd"]"\ + "[file normalize "$origin_dir/source/eth_frame_packer.vhd"]"\ + "[file normalize "$origin_dir/source/eth_flowctrl_tx.vhd"]"\ + "[file normalize "$origin_dir/source/eth_frame_unpacker.vhd"]"\ + "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"]"\ + "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_register_slice_128/axis_register_slice_128.xci"]"\ "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci"]"\ "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci"]"\ @@ -98,17 +110,19 @@ proc checkRequiredFiles { origin_dir} { "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci"]"\ "[file normalize "$origin_dir/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci"]"\ + "[file normalize "$origin_dir/ip_repo/ila_3/ila_3.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_register_slice_240/axis_register_slice_240.xci"]"\ "[file normalize "$origin_dir/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_register_slice_512/axis_register_slice_512.xci"]"\ - "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"]"\ - "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"]"\ + "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"]"\ "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"]"\ "[file normalize "$origin_dir/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"]"\ "[file normalize "$origin_dir/source/ad_3w_spi.v"]"\ "[file normalize "$origin_dir/source/ad_iobuf.v"]"\ + "[file normalize "$origin_dir/source/axis_demux_128b.vhd"]"\ "[file normalize "$origin_dir/source/axis_mux_128b.vhd"]"\ + "[file normalize "$origin_dir/source/axis_mux_512b.vhd"]"\ "[file normalize "$origin_dir/source/axis_mux_s2_128b.vhd"]"\ "[file normalize "$origin_dir/ip_repo/Si5332/src/global_types.vhd"]"\ "[file normalize "$origin_dir/ip_repo/Si5332/src/si5341_gen_cfg.vhd"]"\ @@ -136,13 +150,11 @@ proc checkRequiredFiles { origin_dir} { "[file normalize "$origin_dir/ip_repo/Si5332/src/si5332_wrapper.vhd"]"\ "[file normalize "$origin_dir/source/system_top.v"]"\ "[file normalize "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_32b/axis_dwidth_converter_512b_to_32b.xci"]"\ - "[file normalize "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"]"\ - "[file normalize "$origin_dir/ip_repo/ila_3/ila_3.xci"]"\ "[file normalize "$origin_dir/constraints/qsfp_constr.xdc"]"\ "[file normalize "$origin_dir/constraints/system_constr.xdc"]"\ "[file normalize "$origin_dir/constraints/timing_constr.xdc"]"\ - "[file normalize "$origin_dir/sim/tb_cap_plybk.vhd"]"\ "[file normalize "$origin_dir/sim/dds_wrapper_tb.vhd"]"\ + "[file normalize "$origin_dir/sim/tb_cap_plybk.vhd"]"\ "[file normalize "$origin_dir/sim/test_bench.vhd"]"\ ] foreach ifile $files { @@ -250,6 +262,18 @@ create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu19eg-ffvc1760-2 set proj_dir [get_property directory [current_project]] # Reconstruct message rules +set_msg_config -id {Vivado 12-1790} -string {{Evaluation} {features} {should} {NOT} {be} {used} {in} {production} {systems.}} -new_severity {WARNING} -ruleid {1} -source 2 +set_msg_config -id {Designutils 20-3303} -string {{HDPYFinalizeIO}} -new_severity {INFO} -ruleid {10} -source 2 +set_msg_config -id {Place 30-73} -string {{axi_spi}} -new_severity {WARNING} -ruleid {11} -source 2 +set_msg_config -string {{PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY}} -new_severity {WARNING} -ruleid {12} -source 2 +set_msg_config -id {BD 41-1343} -new_severity {WARNING} -ruleid {2} -source 2 +set_msg_config -id {BD 41-1306} -new_severity {WARNING} -ruleid {3} -source 2 +set_msg_config -id {BD 41-1276} -severity {CRITICAL WARNING} -new_severity {ERROR} -ruleid {4} -source 2 +set_msg_config -id {[BD 41-1306]} -suppress -ruleid {41} -source 2 +set_msg_config -id {[BD 41-1271]} -suppress -ruleid {42} -source 2 +set_msg_config -id {IP_Flow 19-3656} -new_severity {INFO} -ruleid {5} -source 2 +set_msg_config -id {IP_Flow 19-4623} -new_severity {INFO} -ruleid {6} -source 2 +set_msg_config -id {IP_Flow 19-459} -new_severity {INFO} -ruleid {7} -source 2 set_msg_config -id {[BD 41-1271]} -suppress -ruleid {8} -source 2 set_msg_config -id {[BD 41-1306]} -suppress -ruleid {9} -source 2 @@ -270,14 +294,14 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "sim_compile_state" -value "1" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "97" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "97" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "97" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "97" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "97" -objects $obj -set_property -name "webtalk.xcelium_export_sim" -value "15" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "97" -objects $obj -set_property -name "webtalk.xsim_launch_sim" -value "103" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "108" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "108" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "108" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "108" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "108" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "5" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "108" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "105" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_COMP_DECL XPM_FIFO XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -297,6 +321,12 @@ if { $obj != {} } { # Set 'sources_1' fileset object set obj [get_filesets sources_1] set files [list \ + [file normalize "${origin_dir}/source/eth_flowctrl_rx.vhd"] \ + [file normalize "${origin_dir}/source/eth_frame_packer.vhd"] \ + [file normalize "${origin_dir}/source/eth_flowctrl_tx.vhd"] \ + [file normalize "${origin_dir}/source/eth_frame_unpacker.vhd"] \ + [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"] \ + [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_register_slice_128/axis_register_slice_128.xci"] \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/axis_register_slice_32/axis_register_slice_32.xci"] \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci"] \ @@ -306,17 +336,19 @@ set files [list \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci"] \ [file normalize "${origin_dir}/ip_repo/dds_pulse_intfc_x4_1_0/src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_afifo_64x128/axis_afifo_64x128.xci"] \ + [file normalize "${origin_dir}/ip_repo/ila_3/ila_3.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_register_slice_240/axis_register_slice_240.xci"] \ [file normalize "${origin_dir}/ip_repo/iq_512b_to_240b/src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_register_slice_512/axis_register_slice_512.xci"] \ - [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci"] \ - [file normalize "${origin_dir}/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci"] \ + [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"] \ [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci"] \ [file normalize "${origin_dir}/ip_repo/qsfp_intfc_1_0/src/dig_iq_hs_custom1x_12bit_usp.dcp"] \ [file normalize "${origin_dir}/source/ad_3w_spi.v"] \ [file normalize "${origin_dir}/source/ad_iobuf.v"] \ + [file normalize "${origin_dir}/source/axis_demux_128b.vhd"] \ [file normalize "${origin_dir}/source/axis_mux_128b.vhd"] \ + [file normalize "${origin_dir}/source/axis_mux_512b.vhd"] \ [file normalize "${origin_dir}/source/axis_mux_s2_128b.vhd"] \ [file normalize "${origin_dir}/ip_repo/Si5332/src/global_types.vhd"] \ [file normalize "${origin_dir}/ip_repo/Si5332/src/si5341_gen_cfg.vhd"] \ @@ -348,6 +380,44 @@ set files [list \ add_files -norecurse -fileset $obj $files # Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/source/eth_flowctrl_rx.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/eth_frame_packer.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/eth_flowctrl_tx.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/source/eth_frame_unpacker.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj +} +set_property -name "registered_with_manager" -value "1" -objects $file_obj + +set file "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj +} +set_property -name "registered_with_manager" -value "1" -objects $file_obj + set file "$origin_dir/ip_repo/axis_register_slice_128/axis_register_slice_128.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -429,6 +499,15 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } +set file "$origin_dir/ip_repo/ila_3/ila_3.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + set file "$origin_dir/ip_repo/axis_data_fifo_32x240/axis_data_fifo_32x240.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -465,23 +544,14 @@ if { ![get_property "is_locked" $file_obj] } { } set_property -name "registered_with_manager" -value "1" -objects $file_obj -set file "$origin_dir/ip_repo/axis_dwidth_converter_128b_to_512b/axis_dwidth_converter_128b_to_512b.xci" +set file "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj -} set_property -name "registered_with_manager" -value "1" -objects $file_obj - -set file "$origin_dir/ip_repo/axis_dwidth_converter_512b_to_128b/axis_dwidth_converter_512b_to_128b.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj if { ![get_property "is_locked" $file_obj] } { - set_property -name "generate_synth_checkpoint" -value "0" -objects $file_obj + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } -set_property -name "registered_with_manager" -value "1" -objects $file_obj set file "$origin_dir/ip_repo/axis_data_fifo_32x512/axis_data_fifo_32x512.xci" set file [file normalize $file] @@ -497,11 +567,21 @@ set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "netlist_only" -value "0" -objects $file_obj +set file "$origin_dir/source/axis_demux_128b.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + set file "$origin_dir/source/axis_mux_128b.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "file_type" -value "VHDL" -objects $file_obj +set file "$origin_dir/source/axis_mux_512b.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + set file "$origin_dir/source/axis_mux_s2_128b.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] @@ -648,48 +728,6 @@ set_property -name "top" -value "system_top" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "vhdl_generic" -value "JESD_MODE=8B10B RX_LANE_RATE=10 TX_LANE_RATE=10 RX_JESD_M=8 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 RX_NUM_LINKS=1 RX_TPL_WIDTH TX_JESD_M=8 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 TX_NUM_LINKS=1 TX_TPL_WIDTH TDD_SUPPORT=0 SHARED_DEVCLK=0 TDD_CHANNEL_CNT=2 TDD_SYNC_WIDTH=32 TDD_SYNC_INT=1 TDD_SYNC_EXT=0 TDD_SYNC_EXT_CDC=0" -objects $obj -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [file normalize "${origin_dir}/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip_repo/axis_data_fifo_32kx128/axis_data_fifo_32kx128.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [file normalize "${origin_dir}/ip_repo/ila_3/ila_3.xci"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip_repo/ila_3/ila_3.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - # Create 'constrs_1' fileset (if not found) if {[string equal [get_filesets -quiet constrs_1] ""]} { create_fileset -constrset constrs_1 @@ -734,19 +772,19 @@ if {[string equal [get_filesets -quiet sim_1] ""]} { # Set 'sim_1' fileset object set obj [get_filesets sim_1] set files [list \ - [file normalize "${origin_dir}/sim/tb_cap_plybk.vhd"] \ [file normalize "${origin_dir}/sim/dds_wrapper_tb.vhd"] \ + [file normalize "${origin_dir}/sim/tb_cap_plybk.vhd"] \ [file normalize "${origin_dir}/sim/test_bench.vhd"] \ ] add_files -norecurse -fileset $obj $files # Set 'sim_1' fileset file properties for remote files -set file "$origin_dir/sim/tb_cap_plybk.vhd" +set file "$origin_dir/sim/dds_wrapper_tb.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] set_property -name "file_type" -value "VHDL" -objects $file_obj -set file "$origin_dir/sim/dds_wrapper_tb.vhd" +set file "$origin_dir/sim/tb_cap_plybk.vhd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] set_property -name "file_type" -value "VHDL" -objects $file_obj @@ -762,7 +800,7 @@ set_property -name "file_type" -value "VHDL" -objects $file_obj # Set 'sim_1' fileset properties set obj [get_filesets sim_1] -set_property -name "top" -value "tb_cap_plybk" -objects $obj +set_property -name "top" -value "dds_wrapper_tb" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj set_property -name "xsim.simulate.log_all_signals" -value "1" -objects $obj @@ -776,6 +814,1077 @@ set obj [get_filesets utils_1] # Adding sources referenced in BDs, if not already added +if { [get_files [list eth_flowctrl_rx.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_rx.vhd +} +if { [get_files [list eth_frame_packer.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_packer.vhd +} +if { [get_files [list eth_flowctrl_tx.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_flowctrl_tx.vhd +} +if { [get_files [list eth_frame_unpacker.vhd]] == "" } { + import_files -quiet -fileset sources_1 /home/nsantana/proj_NEW_REPOS/alinx_z19_ad9081/source/eth_frame_unpacker.vhd +} + + +# Proc to create BD raw_eth +proc cr_bd_raw_eth { parentCell } { +# The design that will be created by this Tcl proc contains the following +# module references: +# eth_flowctrl_rx, eth_frame_packer, eth_flowctrl_tx, eth_frame_unpacker + + + + # CHANGE DESIGN NAME HERE + set design_name raw_eth + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:axis_register_slice:1.1\ + xilinx.com:ip:axis_subset_converter:1.1\ + xilinx.com:ip:axis_data_fifo:2.0\ + xilinx.com:ip:cmac_usplus:3.1\ + xilinx.com:ip:system_ila:1.1\ + xilinx.com:ip:util_vector_logic:2.0\ + xilinx.com:ip:c_counter_binary:12.0\ + xilinx.com:ip:smartconnect:1.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + user:user:axi_regs_32:1.0\ + xilinx.com:ip:xlslice:1.0\ + xilinx.com:ip:xlconcat:2.1\ + xilinx.com:ip:xpm_cdc_gen:1.0\ + xilinx.com:ip:xlconstant:1.1\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + ################################################################## + # CHECK Modules + ################################################################## + set bCheckModules 1 + if { $bCheckModules == 1 } { + set list_check_mods "\ + eth_flowctrl_rx\ + eth_frame_packer\ + eth_flowctrl_tx\ + eth_frame_unpacker\ + " + + set list_mods_missing "" + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + + foreach mod_vlnv $list_check_mods { + if { [can_resolve_reference $mod_vlnv] == 0 } { + lappend list_mods_missing $mod_vlnv + } + } + + if { $list_mods_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." + set bCheckIPsPassed 0 + } +} + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + +# Hierarchical cell: ETH_regs +proc create_hier_cell_ETH_regs { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ETH_regs() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + + # Create pins + create_bd_pin -dir O -from 47 -to 0 dest_addr + create_bd_pin -dir O -from 47 -to 0 source_addr + create_bd_pin -dir O -from 15 -to 0 EtherType + create_bd_pin -dir I cmac_clk + create_bd_pin -dir I aclk + create_bd_pin -dir I aresetn + create_bd_pin -dir O -from 0 -to 0 prog_full_manual + create_bd_pin -dir O -from 31 -to 0 prog_full_on + create_bd_pin -dir O -from 31 -to 0 prog_full_off + create_bd_pin -dir I -from 31 -to 0 tx_frame_cnt + create_bd_pin -dir I -from 31 -to 0 tx_frame_underrun_cnt + create_bd_pin -dir I -from 31 -to 0 tx_pause_cnt + create_bd_pin -dir I -from 31 -to 0 rx_frame_cnt + create_bd_pin -dir I -from 31 -to 0 rx_frame_err_cnt + create_bd_pin -dir I -from 31 -to 0 rx_pause_cnt + create_bd_pin -dir I -from 31 -to 0 rx_fifo_overflow_cnt + + # Create instance: axi_regs_32_0, and set properties + set axi_regs_32_0 [ create_bd_cell -type ip -vlnv user:user:axi_regs_32:1.0 axi_regs_32_0 ] + + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + set_property CONFIG.DIN_FROM {15} $xlslice_0 + + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {32} \ + CONFIG.IN1_WIDTH {16} \ + ] $xlconcat_0 + + + # Create instance: xlconcat_1, and set properties + set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] + set_property -dict [list \ + CONFIG.IN0_WIDTH {32} \ + CONFIG.IN1_WIDTH {16} \ + ] $xlconcat_1 + + + # Create instance: xlslice_1, and set properties + set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + set_property CONFIG.DIN_FROM {15} $xlslice_1 + + + # Create instance: xlslice_2, and set properties + set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] + set_property CONFIG.DIN_FROM {15} $xlslice_2 + + + # Create instance: xpm_cdc_gen_0, and set properties + set xpm_cdc_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_0 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {48} \ + ] $xpm_cdc_gen_0 + + + # Create instance: const_1b0, and set properties + set const_1b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1b0 ] + set_property CONFIG.CONST_VAL {0} $const_1b0 + + + # Create instance: xpm_cdc_gen_1, and set properties + set xpm_cdc_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_1 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {48} \ + ] $xpm_cdc_gen_1 + + + # Create instance: xpm_cdc_gen_2, and set properties + set xpm_cdc_gen_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_2 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {16} \ + ] $xpm_cdc_gen_2 + + + # Create instance: const_32b0, and set properties + set const_32b0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_32b0 ] + set_property -dict [list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {32} \ + ] $const_32b0 + + + # Create instance: xlslice_3, and set properties + set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ] + set_property CONFIG.DIN_FROM {0} $xlslice_3 + + + # Create instance: xpm_cdc_gen_3, and set properties + set xpm_cdc_gen_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_3 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {1} \ + ] $xpm_cdc_gen_3 + + + # Create instance: xpm_cdc_gen_4, and set properties + set xpm_cdc_gen_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_4 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_4 + + + # Create instance: xpm_cdc_gen_5, and set properties + set xpm_cdc_gen_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_5 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_5 + + + # Create instance: xpm_cdc_gen_16, and set properties + set xpm_cdc_gen_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_16 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_16 + + + # Create instance: xpm_cdc_gen_17, and set properties + set xpm_cdc_gen_17 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_17 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_17 + + + # Create instance: xpm_cdc_gen_18, and set properties + set xpm_cdc_gen_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_18 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_18 + + + # Create instance: xpm_cdc_gen_19, and set properties + set xpm_cdc_gen_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_19 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_19 + + + # Create instance: xpm_cdc_gen_20, and set properties + set xpm_cdc_gen_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_20 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_20 + + + # Create instance: xpm_cdc_gen_21, and set properties + set xpm_cdc_gen_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_21 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_21 + + + # Create instance: xpm_cdc_gen_22, and set properties + set xpm_cdc_gen_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xpm_cdc_gen:1.0 xpm_cdc_gen_22 ] + set_property -dict [list \ + CONFIG.DEST_SYNC_FF {2} \ + CONFIG.SIM_ASSERT_CHK {false} \ + CONFIG.SRC_INPUT_REG {false} \ + CONFIG.WIDTH {32} \ + ] $xpm_cdc_gen_22 + + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_regs_32_0/S_AXI] + + # Create port connections + connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_regs_32_0/S_AXI_ACLK] [get_bd_pins xpm_cdc_gen_16/dest_clk] [get_bd_pins xpm_cdc_gen_17/dest_clk] [get_bd_pins xpm_cdc_gen_18/dest_clk] [get_bd_pins xpm_cdc_gen_19/dest_clk] [get_bd_pins xpm_cdc_gen_20/dest_clk] [get_bd_pins xpm_cdc_gen_21/dest_clk] [get_bd_pins xpm_cdc_gen_22/dest_clk] + connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins axi_regs_32_0/S_AXI_ARESETN] + connect_bd_net -net axi_regs_32_0_reg0_out [get_bd_pins axi_regs_32_0/reg0_out] [get_bd_pins xlconcat_0/In0] [get_bd_pins axi_regs_32_0/reg0_in] + connect_bd_net -net axi_regs_32_0_reg1_out [get_bd_pins axi_regs_32_0/reg1_out] [get_bd_pins xlslice_0/Din] [get_bd_pins axi_regs_32_0/reg1_in] + connect_bd_net -net axi_regs_32_0_reg2_out [get_bd_pins axi_regs_32_0/reg2_out] [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_regs_32_0/reg2_in] + connect_bd_net -net axi_regs_32_0_reg3_out [get_bd_pins axi_regs_32_0/reg3_out] [get_bd_pins xlslice_1/Din] [get_bd_pins axi_regs_32_0/reg3_in] + connect_bd_net -net axi_regs_32_0_reg4_out [get_bd_pins axi_regs_32_0/reg4_out] [get_bd_pins xlslice_2/Din] [get_bd_pins axi_regs_32_0/reg4_in] + connect_bd_net -net axi_regs_32_0_reg5_out [get_bd_pins axi_regs_32_0/reg5_out] [get_bd_pins xlslice_3/Din] [get_bd_pins axi_regs_32_0/reg5_in] + connect_bd_net -net axi_regs_32_0_reg6_out [get_bd_pins axi_regs_32_0/reg6_out] [get_bd_pins axi_regs_32_0/reg6_in] [get_bd_pins xpm_cdc_gen_4/src_in] + connect_bd_net -net axi_regs_32_0_reg7_out [get_bd_pins axi_regs_32_0/reg7_out] [get_bd_pins axi_regs_32_0/reg7_in] [get_bd_pins xpm_cdc_gen_5/src_in] + connect_bd_net -net cmac_clk_1 [get_bd_pins cmac_clk] [get_bd_pins xpm_cdc_gen_0/dest_clk] [get_bd_pins xpm_cdc_gen_2/dest_clk] [get_bd_pins xpm_cdc_gen_1/dest_clk] [get_bd_pins xpm_cdc_gen_3/dest_clk] [get_bd_pins xpm_cdc_gen_4/dest_clk] [get_bd_pins xpm_cdc_gen_5/dest_clk] + connect_bd_net -net const_1b0_dout [get_bd_pins const_1b0/dout] [get_bd_pins xpm_cdc_gen_0/src_clk] [get_bd_pins xpm_cdc_gen_1/src_clk] [get_bd_pins xpm_cdc_gen_2/src_clk] [get_bd_pins xpm_cdc_gen_3/src_clk] [get_bd_pins xpm_cdc_gen_4/src_clk] [get_bd_pins xpm_cdc_gen_5/src_clk] [get_bd_pins xpm_cdc_gen_16/src_clk] [get_bd_pins xpm_cdc_gen_17/src_clk] [get_bd_pins xpm_cdc_gen_18/src_clk] [get_bd_pins xpm_cdc_gen_19/src_clk] [get_bd_pins xpm_cdc_gen_20/src_clk] [get_bd_pins xpm_cdc_gen_21/src_clk] [get_bd_pins xpm_cdc_gen_22/src_clk] + connect_bd_net -net const_32b0_dout [get_bd_pins const_32b0/dout] [get_bd_pins axi_regs_32_0/reg9_in] [get_bd_pins axi_regs_32_0/reg8_in] [get_bd_pins axi_regs_32_0/reg10_in] [get_bd_pins axi_regs_32_0/reg11_in] [get_bd_pins axi_regs_32_0/reg12_in] [get_bd_pins axi_regs_32_0/reg13_in] [get_bd_pins axi_regs_32_0/reg14_in] [get_bd_pins axi_regs_32_0/reg15_in] [get_bd_pins axi_regs_32_0/reg23_in] [get_bd_pins axi_regs_32_0/reg24_in] [get_bd_pins axi_regs_32_0/reg25_in] [get_bd_pins axi_regs_32_0/reg26_in] [get_bd_pins axi_regs_32_0/reg27_in] [get_bd_pins axi_regs_32_0/reg28_in] [get_bd_pins axi_regs_32_0/reg29_in] [get_bd_pins axi_regs_32_0/reg30_in] [get_bd_pins axi_regs_32_0/reg31_in] + connect_bd_net -net rx_fifo_overflow_cnt_1 [get_bd_pins rx_fifo_overflow_cnt] [get_bd_pins xpm_cdc_gen_22/src_in] + connect_bd_net -net rx_frame_cnt_1 [get_bd_pins rx_frame_cnt] [get_bd_pins xpm_cdc_gen_19/src_in] + connect_bd_net -net rx_frame_err_cnt_1 [get_bd_pins rx_frame_err_cnt] [get_bd_pins xpm_cdc_gen_20/src_in] + connect_bd_net -net rx_pause_cnt_1 [get_bd_pins rx_pause_cnt] [get_bd_pins xpm_cdc_gen_21/src_in] + connect_bd_net -net tx_frame_cnt_1 [get_bd_pins tx_frame_cnt] [get_bd_pins xpm_cdc_gen_16/src_in] + connect_bd_net -net tx_frame_underrun_cnt_1 [get_bd_pins tx_frame_underrun_cnt] [get_bd_pins xpm_cdc_gen_17/src_in] + connect_bd_net -net tx_pause_cnt_1 [get_bd_pins tx_pause_cnt] [get_bd_pins xpm_cdc_gen_18/src_in] + connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xpm_cdc_gen_0/src_in] + connect_bd_net -net xlconcat_1_dout [get_bd_pins xlconcat_1/dout] [get_bd_pins xpm_cdc_gen_1/src_in] + connect_bd_net -net xlslice_0_Dout [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net xlslice_1_Dout [get_bd_pins xlslice_1/Dout] [get_bd_pins xlconcat_1/In1] + connect_bd_net -net xlslice_2_Dout [get_bd_pins xlslice_2/Dout] [get_bd_pins xpm_cdc_gen_2/src_in] + connect_bd_net -net xlslice_3_Dout [get_bd_pins xlslice_3/Dout] [get_bd_pins xpm_cdc_gen_3/src_in] + connect_bd_net -net xpm_cdc_gen_0_dest_out [get_bd_pins xpm_cdc_gen_0/dest_out] [get_bd_pins dest_addr] + connect_bd_net -net xpm_cdc_gen_18_dest_out [get_bd_pins xpm_cdc_gen_18/dest_out] [get_bd_pins axi_regs_32_0/reg18_in] + connect_bd_net -net xpm_cdc_gen_19_dest_out [get_bd_pins xpm_cdc_gen_19/dest_out] [get_bd_pins axi_regs_32_0/reg19_in] + connect_bd_net -net xpm_cdc_gen_1_dest_out [get_bd_pins xpm_cdc_gen_1/dest_out] [get_bd_pins source_addr] + connect_bd_net -net xpm_cdc_gen_20_dest_out [get_bd_pins xpm_cdc_gen_20/dest_out] [get_bd_pins axi_regs_32_0/reg20_in] + connect_bd_net -net xpm_cdc_gen_21_dest_out [get_bd_pins xpm_cdc_gen_21/dest_out] [get_bd_pins axi_regs_32_0/reg21_in] + connect_bd_net -net xpm_cdc_gen_22_dest_out [get_bd_pins xpm_cdc_gen_22/dest_out] [get_bd_pins axi_regs_32_0/reg22_in] + connect_bd_net -net xpm_cdc_gen_2_dest_out [get_bd_pins xpm_cdc_gen_2/dest_out] [get_bd_pins EtherType] + connect_bd_net -net xpm_cdc_gen_3_dest_out [get_bd_pins xpm_cdc_gen_3/dest_out] [get_bd_pins prog_full_manual] + connect_bd_net -net xpm_cdc_gen_4_dest_out [get_bd_pins xpm_cdc_gen_4/dest_out] [get_bd_pins prog_full_on] + connect_bd_net -net xpm_cdc_gen_5_dest_out [get_bd_pins xpm_cdc_gen_5/dest_out] [get_bd_pins prog_full_off] + connect_bd_net -net xpm_cdc_gen_6_dest_out [get_bd_pins xpm_cdc_gen_16/dest_out] [get_bd_pins axi_regs_32_0/reg16_in] + connect_bd_net -net xpm_cdc_gen_7_dest_out [get_bd_pins xpm_cdc_gen_17/dest_out] [get_bd_pins axi_regs_32_0/reg17_in] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: Ethernet +proc create_hier_cell_Ethernet { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_Ethernet() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXIL + + + # Create pins + create_bd_pin -dir O -type clk axis_aclk + create_bd_pin -dir O -from 0 -to 0 axis_aresetn + create_bd_pin -dir I -type clk axil_clk + create_bd_pin -dir I clk_100_reset + create_bd_pin -dir I clk_100 + create_bd_pin -dir I -from 31 -to 0 rx_fifo_wr_data_cnt + create_bd_pin -dir I -type rst axil_resetn + create_bd_pin -dir I -from 0 -to 0 rx_fifo_overflow + + # Create instance: eth_flowctrl_rx_i, and set properties + set block_name eth_flowctrl_rx + set block_cell_name eth_flowctrl_rx_i + if { [catch {set eth_flowctrl_rx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_flowctrl_rx_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: cmac_usplus_i, and set properties + set cmac_usplus_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_i ] + set_property -dict [list \ + CONFIG.CMAC_CAUI4_MODE {1} \ + CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y1} \ + CONFIG.ENABLE_AXI_INTERFACE {1} \ + CONFIG.ENABLE_PIPELINE_REG {1} \ + CONFIG.GT_GROUP_SELECT {X0Y12~X0Y15} \ + CONFIG.GT_REF_CLK_FREQ {156.25} \ + CONFIG.RX_CHECK_ACK {0} \ + CONFIG.RX_FLOW_CONTROL {1} \ + CONFIG.TX_FLOW_CONTROL {1} \ + CONFIG.TX_SA_GPP {0x000000000000} \ + CONFIG.TX_SA_PPP {0x000000000000} \ + CONFIG.USER_INTERFACE {AXIS} \ + ] $cmac_usplus_i + + + # Create instance: eth_frame_packer_i, and set properties + set block_name eth_frame_packer + set block_cell_name eth_frame_packer_i + if { [catch {set eth_frame_packer_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_frame_packer_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: eth_flowctrl_tx_i, and set properties + set block_name eth_flowctrl_tx + set block_cell_name eth_flowctrl_tx_i + if { [catch {set eth_flowctrl_tx_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_flowctrl_tx_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: eth_frame_unpacker_i, and set properties + set block_name eth_frame_unpacker + set block_cell_name eth_frame_unpacker_i + if { [catch {set eth_frame_unpacker_i [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $eth_frame_unpacker_i eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: system_ila_i, and set properties + set system_ila_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_i ] + set_property -dict [list \ + CONFIG.C_MON_TYPE {MIX} \ + CONFIG.C_NUM_MONITOR_SLOTS {6} \ + CONFIG.C_NUM_OF_PROBES {20} \ + CONFIG.C_SLOT {5} \ + CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \ + CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:display_cmac_usplus:statistics_ports:2.0} \ + CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ + ] $system_ila_i + + + # Create instance: ETH_regs + create_hier_cell_ETH_regs $hier_obj ETH_regs + + # Create instance: rst_inv_i, and set properties + set rst_inv_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 rst_inv_i ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $rst_inv_i + + + # Create instance: counter_i, and set properties + set counter_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 counter_i ] + set_property -dict [list \ + CONFIG.CE {true} \ + CONFIG.Fb_Latency_Configuration {Automatic} \ + CONFIG.Latency_Configuration {Automatic} \ + CONFIG.Load {false} \ + CONFIG.Load_Sense {Active_High} \ + CONFIG.Output_Width {32} \ + CONFIG.Restrict_Count {false} \ + CONFIG.SCLR {true} \ + CONFIG.SSET {false} \ + CONFIG.Sync_Threshold_Output {false} \ + ] $counter_i + + + # Create instance: smartcon_i, and set properties + set smartcon_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartcon_i ] + set_property -dict [list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $smartcon_i + + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins smartcon_i/S00_AXI] [get_bd_intf_pins S_AXIL] + connect_bd_intf_net -intf_net S_AXI_1 [get_bd_intf_pins ETH_regs/S_AXI] [get_bd_intf_pins smartcon_i/M01_AXI] + connect_bd_intf_net -intf_net cmac_axis_rx [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins eth_frame_unpacker_i/s_axis] + connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_axis_rx] [get_bd_intf_pins cmac_usplus_i/axis_rx] [get_bd_intf_pins system_ila_i/SLOT_4_AXIS] + connect_bd_intf_net -intf_net cmac_refclk [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins cmac_usplus_i/gt_ref_clk] + connect_bd_intf_net -intf_net cmac_tx_fifo_M_AXIS [get_bd_intf_pins S_AXIS] [get_bd_intf_pins eth_frame_packer_i/s_axis] + connect_bd_intf_net -intf_net [get_bd_intf_nets cmac_tx_fifo_M_AXIS] [get_bd_intf_pins S_AXIS] [get_bd_intf_pins system_ila_i/SLOT_0_AXIS] + connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_pins cmac_gt] [get_bd_intf_pins cmac_usplus_i/gt_serial_port] + connect_bd_intf_net -intf_net cmac_usplus_i_stat_rx [get_bd_intf_pins cmac_usplus_i/stat_rx] [get_bd_intf_pins system_ila_i/SLOT_3_STATISTICS_PORTS] + connect_bd_intf_net -intf_net cmac_usplus_i_stat_tx [get_bd_intf_pins cmac_usplus_i/stat_tx] [get_bd_intf_pins system_ila_i/SLOT_2_STATISTICS_PORTS] + connect_bd_intf_net -intf_net packer_m_axis [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins cmac_usplus_i/axis_tx] + connect_bd_intf_net -intf_net [get_bd_intf_nets packer_m_axis] [get_bd_intf_pins eth_frame_packer_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_1_AXIS] + connect_bd_intf_net -intf_net smartcon_i_M00_AXI [get_bd_intf_pins cmac_usplus_i/s_axi] [get_bd_intf_pins smartcon_i/M00_AXI] + connect_bd_intf_net -intf_net unpacker_m_axis [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins M_AXIS] + connect_bd_intf_net -intf_net [get_bd_intf_nets unpacker_m_axis] [get_bd_intf_pins eth_frame_unpacker_i/m_axis] [get_bd_intf_pins system_ila_i/SLOT_5_AXIS] + + # Create port connections + connect_bd_net -net ETH_regs_prog_full_off [get_bd_pins ETH_regs/prog_full_off] [get_bd_pins system_ila_i/probe12] [get_bd_pins eth_flowctrl_tx_i/prog_full_off] + connect_bd_net -net ETH_regs_prog_full_on [get_bd_pins ETH_regs/prog_full_on] [get_bd_pins system_ila_i/probe11] [get_bd_pins eth_flowctrl_tx_i/prog_full_on] + connect_bd_net -net axil_clk [get_bd_pins axil_clk] [get_bd_pins ETH_regs/aclk] [get_bd_pins cmac_usplus_i/s_axi_aclk] [get_bd_pins smartcon_i/aclk] + connect_bd_net -net axil_resetn [get_bd_pins axil_resetn] [get_bd_pins ETH_regs/aresetn] [get_bd_pins rst_inv_i/Op1] [get_bd_pins smartcon_i/aresetn] + connect_bd_net -net clk_100 [get_bd_pins clk_100] [get_bd_pins cmac_usplus_i/drp_clk] [get_bd_pins cmac_usplus_i/init_clk] + connect_bd_net -net clk_100_reset [get_bd_pins clk_100_reset] [get_bd_pins cmac_usplus_i/sys_reset] + connect_bd_net -net cmac_reset [get_bd_pins cmac_usplus_i/usr_tx_reset] [get_bd_pins proc_sys_reset_0/ext_reset_in] + connect_bd_net -net cmac_resetn [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins axis_aresetn] [get_bd_pins system_ila_i/resetn] [get_bd_pins eth_flowctrl_rx_i/resetn] [get_bd_pins eth_frame_packer_i/resetn] [get_bd_pins eth_flowctrl_tx_i/resetn] [get_bd_pins eth_frame_unpacker_i/resetn] + connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins rx_fifo_wr_data_cnt] [get_bd_pins system_ila_i/probe10] [get_bd_pins eth_flowctrl_tx_i/data_cnt] + connect_bd_net -net cmac_usplus_i_gt_powergoodout [get_bd_pins cmac_usplus_i/gt_powergoodout] [get_bd_pins system_ila_i/probe0] + connect_bd_net -net cmac_usplus_i_gt_txusrclk2 [get_bd_pins cmac_usplus_i/gt_txusrclk2] [get_bd_pins axis_aclk] [get_bd_pins cmac_usplus_i/rx_clk] [get_bd_pins system_ila_i/clk] [get_bd_pins ETH_regs/cmac_clk] [get_bd_pins counter_i/CLK] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins eth_flowctrl_rx_i/clk] [get_bd_pins eth_frame_packer_i/clk] [get_bd_pins eth_flowctrl_tx_i/clk] [get_bd_pins eth_frame_unpacker_i/clk] + connect_bd_net -net cmac_usplus_i_stat_rx_pause [get_bd_pins cmac_usplus_i/stat_rx_pause] [get_bd_pins system_ila_i/probe16] [get_bd_pins eth_flowctrl_rx_i/rx_pause] + connect_bd_net -net cmac_usplus_i_stat_rx_pause_quanta8 [get_bd_pins cmac_usplus_i/stat_rx_pause_quanta8] [get_bd_pins system_ila_i/probe17] [get_bd_pins eth_flowctrl_rx_i/rx_pause_quanta8] + connect_bd_net -net counter_i_Q [get_bd_pins counter_i/Q] [get_bd_pins ETH_regs/rx_fifo_overflow_cnt] + connect_bd_net -net ctl_tx_pause_req [get_bd_pins eth_flowctrl_tx_i/ctl_tx_pause_req] [get_bd_pins cmac_usplus_i/ctl_tx_pause_req] [get_bd_pins system_ila_i/probe9] + connect_bd_net -net ctl_tx_resend_pause [get_bd_pins eth_flowctrl_tx_i/ctl_tx_resend_pause] [get_bd_pins cmac_usplus_i/ctl_tx_resend_pause] [get_bd_pins system_ila_i/probe8] + connect_bd_net -net eth_flowctrl_rx_0_pause [get_bd_pins eth_flowctrl_rx_i/pause] [get_bd_pins system_ila_i/probe15] + connect_bd_net -net eth_flowctrl_rx_0_rx_pause_cnt [get_bd_pins eth_flowctrl_rx_i/rx_pause_cnt] [get_bd_pins ETH_regs/rx_pause_cnt] [get_bd_pins system_ila_i/probe14] + connect_bd_net -net eth_flowctrl_tx_i_tx_pause_cnt [get_bd_pins eth_flowctrl_tx_i/tx_pause_cnt] [get_bd_pins ETH_regs/tx_pause_cnt] [get_bd_pins system_ila_i/probe19] + connect_bd_net -net eth_frame_packer_i_tx_cnt [get_bd_pins eth_frame_packer_i/tx_cnt] [get_bd_pins ETH_regs/tx_frame_cnt] [get_bd_pins system_ila_i/probe13] + connect_bd_net -net eth_frame_unpacker_i_rx_frame_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_cnt] [get_bd_pins ETH_regs/rx_frame_cnt] [get_bd_pins system_ila_i/probe18] + connect_bd_net -net eth_regs_EtherType [get_bd_pins ETH_regs/EtherType] [get_bd_pins system_ila_i/probe6] [get_bd_pins eth_frame_packer_i/cfg_eth_type] + connect_bd_net -net eth_regs_dest_addr [get_bd_pins ETH_regs/dest_addr] [get_bd_pins system_ila_i/probe4] [get_bd_pins eth_frame_packer_i/cfg_dst_mac] + connect_bd_net -net eth_regs_source_addr [get_bd_pins ETH_regs/source_addr] [get_bd_pins system_ila_i/probe5] [get_bd_pins eth_frame_packer_i/cfg_src_mac] + connect_bd_net -net packer_underrun_cnt [get_bd_pins eth_frame_packer_i/underrun_cnt] [get_bd_pins system_ila_i/probe1] [get_bd_pins ETH_regs/tx_frame_underrun_cnt] + connect_bd_net -net probe2_1 [get_bd_pins rx_fifo_overflow] [get_bd_pins system_ila_i/probe2] [get_bd_pins counter_i/CE] + connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins proc_sys_reset_0/peripheral_reset] [get_bd_pins counter_i/SCLR] + connect_bd_net -net prog_full_manual [get_bd_pins ETH_regs/prog_full_manual] [get_bd_pins system_ila_i/probe7] [get_bd_pins eth_flowctrl_tx_i/prog_full_manual] + connect_bd_net -net rst_inv_i_Res [get_bd_pins rst_inv_i/Res] [get_bd_pins cmac_usplus_i/s_axi_sreset] + connect_bd_net -net unpacker_rx_frame_err_cnt [get_bd_pins eth_frame_unpacker_i/rx_frame_err_cnt] [get_bd_pins system_ila_i/probe3] [get_bd_pins ETH_regs/rx_frame_err_cnt] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: srl2 +proc create_hier_cell_srl2 { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_srl2() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis + + + # Create pins + create_bd_pin -dir I -type clk axis_clk + create_bd_pin -dir I -type rst axis_resetn + create_bd_pin -dir I -type clk axil_clk + create_bd_pin -dir I -type rst axil_resetn + create_bd_pin -dir I clk_100 + create_bd_pin -dir I clk_100_reset + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst aresetn_0 + + # Create instance: axis_reg_0_i, and set properties + set axis_reg_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_0_i ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $axis_reg_0_i + + + # Create instance: axis_ss_conv_0_i, and set properties + set axis_ss_conv_0_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_0_i ] + set_property -dict [list \ + CONFIG.DEFAULT_TLAST {16} \ + CONFIG.M_HAS_TKEEP {0} \ + CONFIG.M_HAS_TLAST {1} \ + CONFIG.M_HAS_TREADY {1} \ + CONFIG.M_HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.M_TDEST_WIDTH {0} \ + CONFIG.M_TID_WIDTH {0} \ + CONFIG.M_TUSER_WIDTH {0} \ + CONFIG.S_HAS_TKEEP {0} \ + CONFIG.S_HAS_TLAST {0} \ + CONFIG.S_HAS_TREADY {1} \ + CONFIG.S_HAS_TSTRB {0} \ + CONFIG.S_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDEST_WIDTH {0} \ + CONFIG.S_TID_WIDTH {0} \ + CONFIG.S_TUSER_WIDTH {0} \ + ] $axis_ss_conv_0_i + + + # Create instance: cmac_rx_fifo_i, and set properties + set cmac_rx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_rx_fifo_i ] + set_property -dict [list \ + CONFIG.FIFO_DEPTH {1024} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.HAS_WR_DATA_COUNT {1} \ + CONFIG.IS_ACLK_ASYNC {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $cmac_rx_fifo_i + + + # Create instance: axis_ss_conv_1_i, and set properties + set axis_ss_conv_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_ss_conv_1_i ] + set_property -dict [list \ + CONFIG.M_HAS_TKEEP {0} \ + CONFIG.M_HAS_TLAST {0} \ + CONFIG.M_HAS_TREADY {1} \ + CONFIG.M_HAS_TSTRB {0} \ + CONFIG.M_TDATA_NUM_BYTES {64} \ + CONFIG.M_TDEST_WIDTH {0} \ + CONFIG.M_TID_WIDTH {0} \ + CONFIG.M_TUSER_WIDTH {0} \ + CONFIG.S_HAS_TKEEP {0} \ + CONFIG.S_HAS_TLAST {1} \ + CONFIG.S_HAS_TREADY {0} \ + CONFIG.S_HAS_TSTRB {0} \ + CONFIG.S_TDATA_NUM_BYTES {64} \ + CONFIG.S_TDEST_WIDTH {0} \ + CONFIG.S_TID_WIDTH {0} \ + CONFIG.S_TUSER_WIDTH {1} \ + ] $axis_ss_conv_1_i + + + # Create instance: axis_reg_1_i, and set properties + set axis_reg_1_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_reg_1_i ] + set_property -dict [list \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.REG_CONFIG {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $axis_reg_1_i + + + # Create instance: cmac_tx_fifo_i, and set properties + set cmac_tx_fifo_i [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 cmac_tx_fifo_i ] + set_property -dict [list \ + CONFIG.FIFO_DEPTH {32} \ + CONFIG.FIFO_MODE {2} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.IS_ACLK_ASYNC {1} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $cmac_tx_fifo_i + + + # Create instance: Ethernet + create_hier_cell_Ethernet $hier_obj Ethernet + + # Create interface connections + connect_bd_intf_net -intf_net Ethernet_M_AXIS [get_bd_intf_pins Ethernet/M_AXIS] [get_bd_intf_pins axis_ss_conv_1_i/S_AXIS] + connect_bd_intf_net -intf_net Ethernet_cmac_gt [get_bd_intf_pins cmac_gt] [get_bd_intf_pins Ethernet/cmac_gt] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins cmac_rx_fifo_i/M_AXIS] [get_bd_intf_pins axis_reg_1_i/S_AXIS] + connect_bd_intf_net -intf_net axis_reg_1_i_M_AXIS [get_bd_intf_pins m_axis] [get_bd_intf_pins axis_reg_1_i/M_AXIS] + connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_reg_0_i/M_AXIS] [get_bd_intf_pins axis_ss_conv_0_i/S_AXIS] + connect_bd_intf_net -intf_net axis_ss_conv_0_i_M_AXIS [get_bd_intf_pins axis_ss_conv_0_i/M_AXIS] [get_bd_intf_pins cmac_tx_fifo_i/S_AXIS] + connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS1 [get_bd_intf_pins axis_ss_conv_1_i/M_AXIS] [get_bd_intf_pins cmac_rx_fifo_i/S_AXIS] + connect_bd_intf_net -intf_net cmac_refclk_1 [get_bd_intf_pins cmac_refclk] [get_bd_intf_pins Ethernet/cmac_refclk] + connect_bd_intf_net -intf_net cmac_tx_fifo_i_M_AXIS [get_bd_intf_pins cmac_tx_fifo_i/M_AXIS] [get_bd_intf_pins Ethernet/S_AXIS] + connect_bd_intf_net -intf_net s_axil_1 [get_bd_intf_pins s_axil] [get_bd_intf_pins Ethernet/S_AXIL] + connect_bd_intf_net -intf_net s_axis_1 [get_bd_intf_pins s_axis] [get_bd_intf_pins axis_reg_0_i/S_AXIS] + + # Create port connections + connect_bd_net -net Ethernet_axis_aclk [get_bd_pins Ethernet/axis_aclk] [get_bd_pins axis_ss_conv_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/s_axis_aclk] [get_bd_pins cmac_tx_fifo_i/m_axis_aclk] + connect_bd_net -net Ethernet_axis_aresetn [get_bd_pins Ethernet/axis_aresetn] [get_bd_pins cmac_rx_fifo_i/s_axis_aresetn] [get_bd_pins axis_ss_conv_1_i/aresetn] + connect_bd_net -net Net [get_bd_pins m_axis_aclk] [get_bd_pins axis_reg_1_i/aclk] [get_bd_pins cmac_rx_fifo_i/m_axis_aclk] + connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins axis_reg_1_i/aresetn] + connect_bd_net -net clk_100_1 [get_bd_pins clk_100] [get_bd_pins Ethernet/clk_100] + connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset] [get_bd_pins Ethernet/clk_100_reset] + connect_bd_net -net cmac_rx_fifo_i_axis_wr_data_count [get_bd_pins cmac_rx_fifo_i/axis_wr_data_count] [get_bd_pins Ethernet/rx_fifo_wr_data_cnt] + connect_bd_net -net cmac_rx_overflow [get_bd_pins axis_ss_conv_1_i/transfer_dropped] [get_bd_pins Ethernet/rx_fifo_overflow] + connect_bd_net -net s_axi_sreset_1 [get_bd_pins axil_resetn] [get_bd_pins Ethernet/axil_resetn] + connect_bd_net -net s_axilite_dsp_clk [get_bd_pins axil_clk] [get_bd_pins Ethernet/axil_clk] + connect_bd_net -net s_axis_dsp_clk [get_bd_pins axis_clk] [get_bd_pins axis_reg_0_i/aclk] [get_bd_pins axis_ss_conv_0_i/aclk] [get_bd_pins cmac_tx_fifo_i/s_axis_aclk] + connect_bd_net -net s_axis_dsp_resetn [get_bd_pins axis_resetn] [get_bd_pins axis_reg_0_i/aresetn] [get_bd_pins axis_ss_conv_0_i/aresetn] [get_bd_pins cmac_tx_fifo_i/s_axis_aresetn] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: hier_0 +proc create_hier_cell_hier_0 { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_hier_0() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0 + + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_0 + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0 + + + # Create pins + create_bd_pin -dir I -type clk axis_clk_0 + create_bd_pin -dir I -type rst axis_resetn_0 + create_bd_pin -dir I -type clk axil_clk_0 + create_bd_pin -dir I -type rst axil_resetn_0 + create_bd_pin -dir I clk_100_0 + create_bd_pin -dir I clk_100_reset_0 + create_bd_pin -dir I -type clk m_axis_aclk + create_bd_pin -dir I -type rst aresetn_0 + + # Create instance: srl2 + create_hier_cell_srl2 $hier_obj srl2 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins srl2/cmac_gt] [get_bd_intf_pins cmac_gt_0] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins srl2/m_axis] [get_bd_intf_pins m_axis_0] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins srl2/s_axil] [get_bd_intf_pins s_axil_0] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins srl2/s_axis] [get_bd_intf_pins s_axis_0] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins srl2/cmac_refclk] [get_bd_intf_pins cmac_refclk_0] + + # Create port connections + connect_bd_net -net aresetn_0_1 [get_bd_pins aresetn_0] [get_bd_pins srl2/aresetn_0] + connect_bd_net -net axil_clk_1 [get_bd_pins axil_clk_0] [get_bd_pins srl2/axil_clk] + connect_bd_net -net axil_resetn_1 [get_bd_pins axil_resetn_0] [get_bd_pins srl2/axil_resetn] + connect_bd_net -net axis_clk_1 [get_bd_pins axis_clk_0] [get_bd_pins srl2/axis_clk] + connect_bd_net -net axis_resetn_1 [get_bd_pins axis_resetn_0] [get_bd_pins srl2/axis_resetn] + connect_bd_net -net clk_100_1 [get_bd_pins clk_100_0] [get_bd_pins srl2/clk_100] + connect_bd_net -net clk_100_reset_1 [get_bd_pins clk_100_reset_0] [get_bd_pins srl2/clk_100_reset] + connect_bd_net -net m_axis_aclk_1 [get_bd_pins m_axis_aclk] [get_bd_pins srl2/m_axis_aclk] + + # Restore current instance + current_bd_instance $oldCurInst +} + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set cmac_gt_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 cmac_gt_0 ] + + set m_axis [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {375000000} \ + ] $m_axis + + set s_axil_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {1} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $s_axil_0 + + set s_axis [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {375000000} \ + CONFIG.HAS_TKEEP {0} \ + CONFIG.HAS_TLAST {0} \ + CONFIG.HAS_TREADY {1} \ + CONFIG.HAS_TSTRB {0} \ + CONFIG.LAYERED_METADATA {undef} \ + CONFIG.TDATA_NUM_BYTES {64} \ + CONFIG.TDEST_WIDTH {0} \ + CONFIG.TID_WIDTH {0} \ + CONFIG.TUSER_WIDTH {0} \ + ] $s_axis + + set cmac_refclk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 cmac_refclk_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {156250000} \ + ] $cmac_refclk_0 + + + # Create ports + set s_axis_clk [ create_bd_port -dir I -type clk -freq_hz 375000000 s_axis_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {s_axis} \ + CONFIG.ASSOCIATED_RESET {s_axis_aresetn} \ + ] $s_axis_clk + set s_axis_aresetn [ create_bd_port -dir I -type rst s_axis_aresetn ] + set axil_clk_0 [ create_bd_port -dir I -type clk axil_clk_0 ] + set axil_resetn_0 [ create_bd_port -dir I -type rst axil_resetn_0 ] + set clk_100_0 [ create_bd_port -dir I clk_100_0 ] + set clk_100_reset_0 [ create_bd_port -dir I clk_100_reset_0 ] + set m_axis_aclk [ create_bd_port -dir I -type clk -freq_hz 375000000 m_axis_aclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {m_axis} \ + CONFIG.ASSOCIATED_RESET {m_axis_aresetn} \ + CONFIG.CLK_DOMAIN {raw_eth_axis_clk_0} \ + ] $m_axis_aclk + set m_axis_aresetn [ create_bd_port -dir I -type rst m_axis_aresetn ] + + # Create instance: hier_0 + create_hier_cell_hier_0 [current_bd_instance .] hier_0 + + # Create interface connections + connect_bd_intf_net -intf_net cmac_refclk_0_1 [get_bd_intf_ports cmac_refclk_0] [get_bd_intf_pins hier_0/cmac_refclk_0] + connect_bd_intf_net -intf_net hier_0_cmac_gt_0 [get_bd_intf_ports cmac_gt_0] [get_bd_intf_pins hier_0/cmac_gt_0] + connect_bd_intf_net -intf_net hier_0_m_axis_0 [get_bd_intf_ports m_axis] [get_bd_intf_pins hier_0/m_axis_0] + connect_bd_intf_net -intf_net s_axil_0_1 [get_bd_intf_ports s_axil_0] [get_bd_intf_pins hier_0/s_axil_0] + connect_bd_intf_net -intf_net s_axis_0_1 [get_bd_intf_ports s_axis] [get_bd_intf_pins hier_0/s_axis_0] + + # Create port connections + connect_bd_net -net aresetn_0_1 [get_bd_ports m_axis_aresetn] [get_bd_pins hier_0/aresetn_0] + connect_bd_net -net axil_clk_0_1 [get_bd_ports axil_clk_0] [get_bd_pins hier_0/axil_clk_0] + connect_bd_net -net axil_resetn_0_1 [get_bd_ports axil_resetn_0] [get_bd_pins hier_0/axil_resetn_0] + connect_bd_net -net axis_clk_0_1 [get_bd_ports s_axis_clk] [get_bd_pins hier_0/axis_clk_0] + connect_bd_net -net axis_resetn_0_1 [get_bd_ports s_axis_aresetn] [get_bd_pins hier_0/axis_resetn_0] + connect_bd_net -net clk_100_0_1 [get_bd_ports clk_100_0] [get_bd_pins hier_0/clk_100_0] + connect_bd_net -net clk_100_reset_0_1 [get_bd_ports clk_100_reset_0] [get_bd_pins hier_0/clk_100_reset_0] + connect_bd_net -net m_axis_aclk_1 [get_bd_ports m_axis_aclk] [get_bd_pins hier_0/m_axis_aclk] + + # Create address segments + assign_bd_address -offset 0x84000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/ETH_regs/axi_regs_32_0/S_AXI/reg0] -force + assign_bd_address -offset 0x84010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces s_axil_0] [get_bd_addr_segs hier_0/srl2/Ethernet/cmac_usplus_i/s_axi/Reg] -force + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-456,-97", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port cmac_gt_0 -pg 1 -lvl 2 -x 320 -y 150 -defaultsOSRD +preplace port m_axis -pg 1 -lvl 2 -x 320 -y 170 -defaultsOSRD +preplace port s_axil_0 -pg 1 -lvl 0 -x 0 -y 60 -defaultsOSRD +preplace port s_axis -pg 1 -lvl 0 -x 0 -y 80 -defaultsOSRD +preplace port cmac_refclk_0 -pg 1 -lvl 0 -x 0 -y 100 -defaultsOSRD +preplace port port-id_s_axis_clk -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD +preplace port port-id_s_axis_aresetn -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD +preplace port port-id_axil_clk_0 -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD +preplace port port-id_axil_resetn_0 -pg 1 -lvl 0 -x 0 -y 180 -defaultsOSRD +preplace port port-id_clk_100_0 -pg 1 -lvl 0 -x 0 -y 200 -defaultsOSRD +preplace port port-id_clk_100_reset_0 -pg 1 -lvl 0 -x 0 -y 220 -defaultsOSRD +preplace port port-id_m_axis_aclk -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD +preplace port port-id_m_axis_aresetn -pg 1 -lvl 0 -x 0 -y 260 -defaultsOSRD +preplace inst hier_0 -pg 1 -lvl 1 -x 160 -y 160 -defaultsOSRD +preplace netloc aresetn_0_1 1 0 1 NJ 260 +preplace netloc axil_clk_0_1 1 0 1 NJ 160 +preplace netloc axil_resetn_0_1 1 0 1 NJ 180 +preplace netloc axis_clk_0_1 1 0 1 NJ 120 +preplace netloc axis_resetn_0_1 1 0 1 NJ 140 +preplace netloc clk_100_0_1 1 0 1 NJ 200 +preplace netloc clk_100_reset_0_1 1 0 1 NJ 220 +preplace netloc m_axis_aclk_1 1 0 1 NJ 240 +preplace netloc cmac_refclk_0_1 1 0 1 NJ 100 +preplace netloc hier_0_cmac_gt_0 1 1 1 NJ 150 +preplace netloc hier_0_m_axis_0 1 1 1 NJ 170 +preplace netloc s_axil_0_1 1 0 1 NJ 60 +preplace netloc s_axis_0_1 1 0 1 NJ 80 +levelinfo -pg 1 0 160 320 +pagesize -pg 1 -db -bbox -sgen -170 0 450 310 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_raw_eth() + +cr_bd_raw_eth "" +set_property REGISTERED_WITH_MANAGER "1" [get_files raw_eth.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files raw_eth.bd ] + # Proc to create BD iq_240b_to_512b @@ -2242,6 +3351,13 @@ proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { CONFIG.PROTOCOL {AXI4LITE} \ ] $M12_AXI_0 + set M13_AXI_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M13_AXI_0 ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $M13_AXI_0 + # Create ports set spi0_csn [ create_bd_port -dir O -from 2 -to 0 spi0_csn ] @@ -2312,7 +3428,7 @@ proc create_hier_cell_axi_mxfe_rx_jesd { parentCell nameHier } { set clk_250_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst clk_250_aresetn_out ] set sys_cpu_clk_out [ create_bd_port -dir O -type clk sys_cpu_clk_out ] set_property -dict [ list \ - CONFIG.ASSOCIATED_BUSIF {M11_AXI_0:M12_AXI_0} \ + CONFIG.ASSOCIATED_BUSIF {M11_AXI_0:M12_AXI_0:M13_AXI_0} \ ] $sys_cpu_clk_out set sys_cpu_aresetn_out [ create_bd_port -dir O -from 0 -to 0 -type rst sys_cpu_aresetn_out ] set pl_clk3_0 [ create_bd_port -dir O -type clk pl_clk3_0 ] @@ -3406,7 +4522,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 # Create instance: axi_cpu_interconnect, and set properties set axi_cpu_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_cpu_interconnect ] set_property -dict [list \ - CONFIG.NUM_MI {13} \ + CONFIG.NUM_MI {14} \ CONFIG.NUM_SI {1} \ ] $axi_cpu_interconnect @@ -3660,6 +4776,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 connect_bd_intf_net -intf_net axi_cpu_interconnect_M10_AXI [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins mxfe_tx_data_offload/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_M11_AXI [get_bd_intf_ports M11_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] connect_bd_intf_net -intf_net axi_cpu_interconnect_M12_AXI [get_bd_intf_ports M12_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] + connect_bd_intf_net -intf_net axi_cpu_interconnect_M13_AXI [get_bd_intf_ports M13_AXI_0] [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] connect_bd_intf_net -intf_net axi_hp0_interconnect_M00_AXI [get_bd_intf_pins axi_hp0_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP0_FPD] connect_bd_intf_net -intf_net axi_hp1_interconnect_M00_AXI [get_bd_intf_pins axi_hp1_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP1_FPD] connect_bd_intf_net -intf_net axi_hp2_interconnect_M00_AXI [get_bd_intf_pins axi_hp2_interconnect/M00_AXI] [get_bd_intf_pins sys_ps8/S_AXI_HP2_FPD] @@ -3822,6 +4939,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 # Create address segments assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M11_AXI_0/Reg] -force assign_bd_address -offset 0x83000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M12_AXI_0/Reg] -force + assign_bd_address -offset 0x84000000 -range 0x00020000 -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs M13_AXI_0/Reg] -force assign_bd_address -offset 0x9C420000 -range 0x00001000 -with_name SEG_data_axi_mxfe_rx_dma -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_dma/s_axi/axi_lite] -force assign_bd_address -offset 0x84A90000 -range 0x00004000 -with_name SEG_data_axi_mxfe_rx_jesd -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_jesd/rx_axi/s_axi/axi_lite] -force assign_bd_address -offset 0x84A60000 -range 0x00010000 -with_name SEG_data_axi_mxfe_rx_xcvr -target_address_space [get_bd_addr_spaces sys_ps8/Data] [get_bd_addr_segs axi_mxfe_rx_xcvr/s_axi/axi_lite] -force @@ -3842,6 +4960,297 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000 exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_rx_xcvr/m_axi] [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_HIGH] exclude_bd_addr_seg -offset 0x000800000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces axi_mxfe_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_HIGH] + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.04233", + "Default View_TopLeft":"4252,745", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port util_mxfe_upack_s_axis -pg 1 -lvl 0 -x -10 -y 780 -defaultsOSRD +preplace port mxfe_tx_data_offload_m_axis -pg 1 -lvl 11 -x 4990 -y 2470 -defaultsOSRD +preplace port M11_AXI_0 -pg 1 -lvl 11 -x 4990 -y 2230 -defaultsOSRD +preplace port M12_AXI_0 -pg 1 -lvl 11 -x 4990 -y 2210 -defaultsOSRD +preplace port M13_AXI_0 -pg 1 -lvl 11 -x 4990 -y 1890 -defaultsOSRD +preplace port port-id_spi0_sclk -pg 1 -lvl 11 -x 4990 -y 2700 -defaultsOSRD +preplace port port-id_spi0_mosi -pg 1 -lvl 11 -x 4990 -y 2720 -defaultsOSRD +preplace port port-id_spi0_miso -pg 1 -lvl 0 -x -10 -y 3280 -defaultsOSRD +preplace port port-id_spi1_sclk -pg 1 -lvl 11 -x 4990 -y 3120 -defaultsOSRD +preplace port port-id_spi1_mosi -pg 1 -lvl 11 -x 4990 -y 2900 -defaultsOSRD +preplace port port-id_spi1_miso -pg 1 -lvl 0 -x -10 -y 3300 -defaultsOSRD +preplace port port-id_rx_device_clk -pg 1 -lvl 0 -x -10 -y 2720 -defaultsOSRD +preplace port port-id_tx_device_clk -pg 1 -lvl 0 -x -10 -y 800 -defaultsOSRD +preplace port port-id_ref_clk_q0 -pg 1 -lvl 0 -x -10 -y 1510 -defaultsOSRD +preplace port port-id_ref_clk_q1 -pg 1 -lvl 0 -x -10 -y 20 -defaultsOSRD +preplace port port-id_rx_sysref_0 -pg 1 -lvl 0 -x -10 -y 1490 -defaultsOSRD +preplace port port-id_rx_data_0_p -pg 1 -lvl 0 -x -10 -y 1530 -defaultsOSRD +preplace port port-id_rx_data_0_n -pg 1 -lvl 0 -x -10 -y 1550 -defaultsOSRD +preplace port port-id_rx_data_1_p -pg 1 -lvl 0 -x -10 -y 1570 -defaultsOSRD +preplace port port-id_rx_data_1_n -pg 1 -lvl 0 -x -10 -y 1590 -defaultsOSRD +preplace port port-id_rx_data_2_p -pg 1 -lvl 0 -x -10 -y 2100 -defaultsOSRD +preplace port port-id_rx_data_2_n -pg 1 -lvl 0 -x -10 -y 2080 -defaultsOSRD +preplace port port-id_rx_data_3_p -pg 1 -lvl 0 -x -10 -y 2120 -defaultsOSRD +preplace port port-id_rx_data_3_n -pg 1 -lvl 0 -x -10 -y 2160 -defaultsOSRD +preplace port port-id_tx_sysref_0 -pg 1 -lvl 0 -x -10 -y 2140 -defaultsOSRD +preplace port port-id_tx_data_0_p -pg 1 -lvl 11 -x 4990 -y 1360 -defaultsOSRD +preplace port port-id_tx_data_0_n -pg 1 -lvl 11 -x 4990 -y 1340 -defaultsOSRD +preplace port port-id_tx_data_1_p -pg 1 -lvl 11 -x 4990 -y 1660 -defaultsOSRD +preplace port port-id_tx_data_1_n -pg 1 -lvl 11 -x 4990 -y 1680 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1 1 10 240 1130 NJ 1130 NJ 1130 NJ 1130 NJ 1130 2720J 1160 3390J 50 NJ 50 NJ 50 4960 +preplace netloc util_mxfe_upack_fifo_rd_data_0 1 6 1 N 840 +preplace netloc util_mxfe_upack_fifo_rd_data_1 1 6 1 N 860 +preplace netloc util_mxfe_upack_fifo_rd_data_2 1 6 1 N 880 +preplace netloc util_mxfe_upack_fifo_rd_data_3 1 6 1 N 900 +preplace netloc util_mxfe_upack_fifo_rd_data_4 1 6 1 N 920 +preplace netloc util_mxfe_upack_fifo_rd_data_5 1 6 1 N 940 +preplace netloc util_mxfe_upack_fifo_rd_data_6 1 6 1 N 960 +preplace netloc util_mxfe_upack_fifo_rd_data_7 1 6 1 N 980 +preplace netloc util_mxfe_xcvr_rx_out_clk_0 1 8 2 4000 970 4420 +preplace netloc util_mxfe_xcvr_tx_0_n 1 9 2 4370J 1340 NJ +preplace netloc util_mxfe_xcvr_tx_0_p 1 9 2 4380J 1360 NJ +preplace netloc util_mxfe_xcvr_tx_1_n 1 9 2 4420J 1680 NJ +preplace netloc util_mxfe_xcvr_tx_1_p 1 9 2 4440J 1660 NJ +preplace netloc util_mxfe_xcvr_tx_2_n 1 9 2 NJ 1720 NJ +preplace netloc util_mxfe_xcvr_tx_2_p 1 9 2 NJ 1700 NJ +preplace netloc util_mxfe_xcvr_tx_3_n 1 9 2 NJ 1800 NJ +preplace netloc util_mxfe_xcvr_tx_3_p 1 9 2 NJ 1780 NJ +preplace netloc util_mxfe_xcvr_tx_out_clk_0 1 7 3 3480 1390 3920 930 4360 +preplace netloc axi_cpu_interconnect_M00_AXI 1 6 1 2610 1630n +preplace netloc axi_cpu_interconnect_M01_AXI 1 2 5 660 1060 NJ 1060 NJ 1060 NJ 1060 2580 +preplace netloc axi_cpu_interconnect_M02_AXI 1 6 1 2650 220n +preplace netloc axi_cpu_interconnect_M03_AXI 1 6 4 2850J 1310 NJ 1310 3790J 1090 4410 +preplace netloc axi_cpu_interconnect_M04_AXI 1 2 5 650 1510 NJ 1510 NJ 1510 NJ 1510 2570 +preplace netloc axi_cpu_interconnect_M05_AXI 1 1 6 260 1520 NJ 1520 NJ 1520 NJ 1520 NJ 1520 2590 +preplace netloc axi_cpu_interconnect_M06_AXI 1 6 2 2860J 1630 3300 +preplace netloc axi_cpu_interconnect_M07_AXI 1 6 1 2710 740n +preplace netloc axi_cpu_interconnect_M08_AXI 1 6 2 NJ 1790 3460 +preplace netloc axi_cpu_interconnect_M09_AXI 1 2 5 660 1530 NJ 1530 NJ 1530 NJ 1530 2600 +preplace netloc axi_cpu_interconnect_M10_AXI 1 6 3 2870 1680 NJ 1680 3880J +preplace netloc axi_cpu_interconnect_M11_AXI 1 6 5 2780J 1210 3400J 940 NJ 940 NJ 940 4970J +preplace netloc axi_cpu_interconnect_M12_AXI 1 6 5 NJ 1870 3410J 1960 3840J 2210 NJ 2210 NJ +preplace netloc axi_cpu_interconnect_M13_AXI 1 6 5 NJ 1890 3360J 1970 3820J 2170 4430J 1890 NJ +preplace netloc axi_hp0_interconnect_M00_AXI 1 4 1 1420 2560n +preplace netloc axi_hp1_interconnect_M00_AXI 1 4 1 1390 2740n +preplace netloc axi_hp2_interconnect_M00_AXI 1 4 1 1440 2810n +preplace netloc axi_mxfe_rx_dma_m_dest_axi 1 3 1 1020 2680n +preplace netloc axi_mxfe_rx_xcvr_m_axi 1 3 1 1070 1230n +preplace netloc axi_mxfe_rx_xcvr_up_ch_0 1 3 6 980J 1080 NJ 1080 NJ 1080 2840J 1110 NJ 1110 3980 +preplace netloc axi_mxfe_rx_xcvr_up_ch_1 1 3 6 NJ 1310 NJ 1310 NJ 1310 2730J 1300 NJ 1300 3820 +preplace netloc axi_mxfe_rx_xcvr_up_ch_2 1 3 6 1030J 1090 NJ 1090 NJ 1090 2830J 1120 NJ 1120 3970 +preplace netloc axi_mxfe_rx_xcvr_up_ch_3 1 3 6 1040J 1100 NJ 1100 NJ 1100 2820J 1130 NJ 1130 3960 +preplace netloc axi_mxfe_rx_xcvr_up_es_0 1 3 6 NJ 1250 NJ 1250 2180J 1270 NJ 1270 3450J 1290 3800 +preplace netloc axi_mxfe_rx_xcvr_up_es_1 1 3 6 NJ 1290 NJ 1290 2150J 1320 NJ 1320 NJ 1320 3830 +preplace netloc axi_mxfe_rx_xcvr_up_es_2 1 3 6 NJ 1330 NJ 1330 NJ 1330 NJ 1330 NJ 1330 N +preplace netloc axi_mxfe_rx_xcvr_up_es_3 1 3 6 NJ 1370 NJ 1370 NJ 1370 2730J 1360 NJ 1360 3950 +preplace netloc axi_mxfe_tx_dma_m_src_axi 1 3 1 1000 2440n +preplace netloc axi_mxfe_tx_jesd_tx_phy0 1 8 1 3860 1230n +preplace netloc axi_mxfe_tx_jesd_tx_phy1 1 8 1 3900 1310n +preplace netloc axi_mxfe_tx_jesd_tx_phy2 1 8 1 3930 1390n +preplace netloc axi_mxfe_tx_jesd_tx_phy3 1 8 1 3950 1470n +preplace netloc axi_mxfe_tx_xcvr_up_ch_0 1 8 1 3840 1210n +preplace netloc axi_mxfe_tx_xcvr_up_ch_1 1 8 1 3850 1290n +preplace netloc axi_mxfe_tx_xcvr_up_ch_2 1 8 1 3870 1370n +preplace netloc axi_mxfe_tx_xcvr_up_ch_3 1 8 1 3880 1450n +preplace netloc axi_mxfe_tx_xcvr_up_cm_0 1 8 1 3810 1150n +preplace netloc mxfe_rx_data_offload_m_axis 1 2 1 600 2600n +preplace netloc mxfe_tx_data_offload_m_axis 1 9 2 NJ 2470 NJ +preplace netloc s_axis_1 1 3 6 NJ 2460 NJ 2460 NJ 2460 NJ 2460 NJ 2460 3940 +preplace netloc sys_ps8_M_AXI_HPM0_LPD 1 5 1 2130 1740n +preplace netloc tx_mxfe_tpl_core_link 1 7 1 3410 700n +preplace netloc util_mxfe_upack_s_axis 1 0 6 NJ 780 NJ 780 NJ 780 NJ 780 NJ 780 NJ +preplace netloc util_mxfe_xcvr_rx_0 1 9 1 N 1440 +preplace netloc util_mxfe_xcvr_rx_1 1 9 1 N 1460 +preplace netloc util_mxfe_xcvr_rx_2 1 9 1 N 1480 +preplace netloc util_mxfe_xcvr_rx_3 1 9 1 N 1500 +levelinfo -pg 1 -10 100 440 820 1250 1770 2420 3070 3610 4180 4710 4990 +pagesize -pg 1 -db -bbox -sgen -230 0 5270 3740 +" +} # Restore current instance current_bd_instance $oldCurInst @@ -3856,6 +5265,15 @@ cr_bd_system "" set_property REGISTERED_WITH_MANAGER "1" [get_files system.bd ] set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files system.bd ] +#call make_wrapper to create wrapper files +if { [get_property IS_LOCKED [ get_files -norecurse [list raw_eth.bd]] ] == 1 } { + import_files -fileset sources_1 [file normalize "${origin_dir}/alinx_z19_ad9081/alinx_z19_ad9081.gen/sources_1/bd/raw_eth/hdl/raw_eth_wrapper.v" ] +} else { + set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse [list raw_eth.bd]] -top] + add_files -norecurse -fileset sources_1 $wrapper_path +} + + set idrFlowPropertiesConstraints "" catch { set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints] @@ -4106,7 +5524,6 @@ set_property -name "options.warn_on_violation" -value "1" -objects $obj } set obj [get_runs impl_1] -set_property -name "needs_refresh" -value "1" -objects $obj set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj @@ -4593,6 +6010,7 @@ set_property -name "options.warn_on_violation" -value "1" -objects $obj } set obj [get_runs impl_3] +set_property -name "needs_refresh" -value "1" -objects $obj set_property -name "part" -value "xczu19eg-ffvc1760-2-i" -objects $obj set_property -name "strategy" -value "Performance_Auto_1" -objects $obj set_property -name "steps.opt_design.args.directive" -value "Explore" -objects $obj @@ -5844,7 +7262,7 @@ set_property -name "steps.write_bitstream.args.readback_file" -value "0" -object set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj # set the current impl run -current_run -implementation [get_runs impl_1] +current_run -implementation [get_runs impl_3] catch { if { $idrFlowPropertiesConstraints != {} } { set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints diff --git a/ip_repo/Si5332/src/si5332_wrapper.vhd b/ip_repo/Si5332/src/si5332_wrapper.vhd index 8ed7d03..860a8ba 100644 --- a/ip_repo/Si5332/src/si5332_wrapper.vhd +++ b/ip_repo/Si5332/src/si5332_wrapper.vhd @@ -44,21 +44,6 @@ architecture imp of si5332_wrapper is signal man_clk_gen_en : std_logic := '0'; signal man_clk_gen_cfg_reset : std_logic := '0'; - - signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal qsfp2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal qsfp2_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp2_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - signal qsfp3_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal qsfp3_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp3_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - - - begin @@ -105,63 +90,4 @@ begin reset_in => clk_100_areset_in ); - --- i_vio_3 : entity work.vio_3 --- port map ( --- clk => clk_100_in, --- probe_in0(0) => i2c_mux_access_ok, -- 1 --- probe_in1(0) => si5341_access_ok, -- 1 --- probe_in2(0) => si5341_config_done, -- 1 --- probe_in3(0) => si5341_config_error, -- 1 --- probe_in4 => clk_100_freq_r, -- 32 --- probe_in5 => clk_100_cnt_r, -- 32 --- probe_in6 => qsfp2_freq_r, -- 32 --- probe_in7 => qsfp2_cnt_r, -- 32 --- probe_in8 => qsfp3_freq_r, -- 32 --- probe_in9 => qsfp3_cnt_r, -- 32 --- --- probe_out0(0) => man_clk_gen_en, -- 1 --- probe_out1(0) => man_clk_gen_cfg_reset -- 1 --- ); - - process(clk_100_in) - begin - if (rising_edge(clk_100_in)) then - clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms; - if (clk_100_tick_1ms_r(0 to 1) = "01") then - clk_100_freq_r <= clk_100_cnt_r; - clk_100_cnt_r <= (others => '0'); - else - clk_100_cnt_r <= clk_100_cnt_r + 1; - end if; - end if; - end process; - - process(qsfp2_clk_in) - begin - if (rising_edge(qsfp2_clk_in)) then - qsfp2_tick_1ms_r <= qsfp2_tick_1ms_r(1 to 2) & tick_1ms; - if (qsfp2_tick_1ms_r(0 to 1) = "01") then - qsfp2_freq_r <= qsfp2_cnt_r; - qsfp2_cnt_r <= (others => '0'); - else - qsfp2_cnt_r <= qsfp2_cnt_r + 1; - end if; - end if; - end process; - - process(qsfp3_clk_in) - begin - if (rising_edge(qsfp3_clk_in)) then - qsfp3_tick_1ms_r <= qsfp3_tick_1ms_r(1 to 2) & tick_1ms; - if (qsfp3_tick_1ms_r(0 to 1) = "01") then - qsfp3_freq_r <= qsfp3_cnt_r; - qsfp3_cnt_r <= (others => '0'); - else - qsfp3_cnt_r <= qsfp3_cnt_r + 1; - end if; - end if; - end process; - - end architecture imp; diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml index 083cc97..c36d602 100644 --- a/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml +++ b/ip_repo/dds_pulse_intfc_x4_1_0/ad9081_fmca_ebz_vcu128.gen/sources_1/ip/axis_register_slice_32/axis_register_slice_32.xml @@ -718,6 +718,49 @@ + + xilinx_verilogbehavioralsimulation + Verilog Simulation + verilogSource:vivado.xilinx.com:simulation + verilog + axis_register_slice_v1_1_29_axis_register_slice + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + + xilinx_verilogbehavioralsimulation_view_fileset + + + + GENtimestamp + Wed Jul 15 19:17:47 UTC 2026 + + + outputProductCRC + 9:abb75340 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + axis_register_slice_32 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Wed Jul 15 19:17:47 UTC 2026 + + + outputProductCRC + 9:abb75340 + + + xilinx_verilogsynthesis Verilog Synthesis @@ -771,6 +814,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -783,6 +827,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -805,6 +850,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -820,6 +866,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -842,6 +889,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -857,6 +905,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -880,6 +929,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -906,6 +956,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -932,6 +983,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -954,6 +1006,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -980,6 +1033,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1006,6 +1060,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1032,6 +1087,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1054,6 +1110,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1066,6 +1123,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1092,6 +1150,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1115,6 +1174,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1138,6 +1198,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1157,6 +1218,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1180,6 +1242,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1203,6 +1266,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1226,6 +1290,7 @@ wire xilinx_verilogsynthesis + xilinx_verilogbehavioralsimulation @@ -1366,6 +1431,46 @@ USED_IN_synthesis + + xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset + + hdl/axis_infrastructure_v1_1_1.vh + verilogSource + USED_IN_ipstatic + true + axis_infrastructure_v1_1_1 + + + hdl/axis_infrastructure_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_infrastructure_v1_1_1 + + + + + + + + + + + xilinx_verilogbehavioralsimulation_view_fileset + + hdl/axis_register_slice_v1_1_vl_rfs.v + verilogSource + USED_IN_ipstatic + axis_register_slice_v1_1_29 + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/axis_register_slice_32.v + verilogSource + xil_defaultlib + + xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset @@ -1381,7 +1486,7 @@ - + diff --git a/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci b/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci index cd633f0..6f0c562 100644 --- a/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci +++ b/ip_repo/dds_pulse_intfc_x4_1_0/src/addsub/addsub.xci @@ -4,7 +4,7 @@ "xci_name": "addsub", "component_reference": "xilinx.com:ip:c_addsub:12.0", "ip_revision": "16", - "gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/addsub", + "gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/addsub", "parameters": { "component_parameters": { "Component_Name": [ { "value": "addsub", "resolve_type": "user", "usage": "all" } ], diff --git a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd index e25d70b..09ccd56 100644 --- a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd +++ b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd @@ -35,7 +35,6 @@ entity qsfp_intfc_v1_0 is -- sysref_in : in std_logic; ref_clk_div2_in : in std_logic; qsfp2_clk_in : in std_logic; - qsfp3_clk_in : in std_logic; pl_clk3_0 : in std_logic; QSFP1_SI570_CLOCK_P : in std_logic; @@ -63,6 +62,14 @@ entity qsfp_intfc_v1_0 is QSFP1_RESETL_LS : out std_logic; QSFP1_MODPRSL_LS : in std_logic; QSFP1_INTL_LS : in std_logic; +----------------- + QSFP2_RESETL_LS : out std_logic; + QSFP2_MODPRSL_LS : in std_logic; + QSFP2_INTL_LS : in std_logic; +----------------- + QSFP3_RESETL_LS : out std_logic; + QSFP3_MODPRSL_LS : in std_logic; + QSFP3_INTL_LS : in std_logic; ----------------- QSFP4_SI570_CLOCK_P : in std_logic; QSFP4_SI570_CLOCK_N : in std_logic; @@ -107,7 +114,7 @@ entity qsfp_intfc_v1_0 is qsfp1_capture_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0); qsfp1_tx_fifo_128_aempty_cnt_in : in std_logic_vector(31 downto 0); qsfp1_capture_rx_data_ready_cnt_in : in std_logic_vector(31 downto 0); - qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); + qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); mem_xfer_tx_upload_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); dac_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); @@ -117,42 +124,13 @@ entity qsfp_intfc_v1_0 is qsfp4_playback_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0); fiber_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0); + cmac_0_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0); + cmac_0_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0); cnt_reset_out : out std_logic; slv_reg9_out : out std_logic_vector(31 downto 0); slv_reg10_out : out std_logic_vector(31 downto 0); - - slv_reg21_out : out std_logic_vector(31 downto 0); - slv_reg22_out : out std_logic_vector(31 downto 0); - slv_reg23_out : out std_logic_vector(31 downto 0); - slv_reg24_out : out std_logic_vector(31 downto 0); - slv_reg25_out : out std_logic_vector(31 downto 0); - slv_reg26_out : out std_logic_vector(31 downto 0); - slv_reg27_out : out std_logic_vector(31 downto 0); - slv_reg28_out : out std_logic_vector(31 downto 0); - slv_reg29_out : out std_logic_vector(31 downto 0); - slv_reg30_out : out std_logic_vector(31 downto 0); - - slv_reg31_out : out std_logic_vector(31 downto 0); - slv_reg32_out : out std_logic_vector(31 downto 0); - slv_reg33_out : out std_logic_vector(31 downto 0); - slv_reg34_out : out std_logic_vector(31 downto 0); - slv_reg35_out : out std_logic_vector(31 downto 0); - slv_reg36_out : out std_logic_vector(31 downto 0); - slv_reg37_out : out std_logic_vector(31 downto 0); - slv_reg38_out : out std_logic_vector(31 downto 0); - slv_reg39_out : out std_logic_vector(31 downto 0); - slv_reg40_out : out std_logic_vector(31 downto 0); - - slv_reg41_out : out std_logic_vector(31 downto 0); - slv_reg42_out : out std_logic_vector(31 downto 0); - slv_reg43_out : out std_logic_vector(31 downto 0); - slv_reg44_out : out std_logic_vector(31 downto 0); - slv_reg45_out : out std_logic_vector(31 downto 0); - slv_reg46_out : out std_logic_vector(31 downto 0); - slv_reg47_out : out std_logic_vector(31 downto 0); - slv_reg48_out : out std_logic_vector(31 downto 0); -- User ports ends -- Do not modify the ports beyond this line @@ -226,6 +204,16 @@ architecture arch_imp of qsfp_intfc_v1_0 is signal qsfp1_m_axis_tdata : std_logic_vector(239 downto 0); signal qsfp1_m_axis_tvalid : std_logic; +-- + signal qsfp2_reset_n_i : std_logic; + signal qsfp2_modprsl : std_logic; + signal qsfp2_intl : std_logic; + signal qsfp2_reset_n : std_logic; +-- + signal qsfp3_reset_n_i : std_logic; + signal qsfp3_modprsl : std_logic; + signal qsfp3_intl : std_logic; + signal qsfp3_reset_n : std_logic; -- signal qsfp4_axis_aclk : std_logic; signal qsfp4_axis_aresetn : std_logic; @@ -284,10 +272,6 @@ architecture arch_imp of qsfp_intfc_v1_0 is signal qsfp2_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0'); signal qsfp2_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp3_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); - signal qsfp3_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0'); - signal qsfp3_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); - signal slv_reg0 : std_logic_vector(31 downto 0); signal slv_reg1 : std_logic_vector(31 downto 0); signal slv_reg2 : std_logic_vector(31 downto 0); @@ -375,39 +359,39 @@ begin slv_reg19_in => clk_250_freq_r, -- 0x8000_004C slv_reg20_in => clk_250_cnt_r, -- 0x8000_0050 - slv_reg21_out => slv_reg21_out, -- 0x8000_0054 - slv_reg22_out => slv_reg22_out, -- 0x8000_0058 - slv_reg23_out => slv_reg23_out, -- 0x8000_005C * - slv_reg24_out => slv_reg24_out, -- 0x8000_0060 - slv_reg25_out => slv_reg25_out, -- 0x8000_0064 * - slv_reg26_out => slv_reg26_out, -- 0x8000_0068 * - slv_reg27_out => slv_reg27_out, -- 0x8000_006C - slv_reg28_out => slv_reg28_out, -- 0x8000_0070 + slv_reg21_out => open, -- 0x8000_0054 + slv_reg22_out => open, -- 0x8000_0058 + slv_reg23_out => open, -- 0x8000_005C + slv_reg24_out => open, -- 0x8000_0060 + slv_reg25_out => open, -- 0x8000_0064 + slv_reg26_out => open, -- 0x8000_0068 + slv_reg27_out => open, -- 0x8000_006C + slv_reg28_out => open, -- 0x8000_0070 - slv_reg29_out => slv_reg29_out, -- 0x8000_0074 - slv_reg30_out => slv_reg30_out, -- 0x8000_0078 - slv_reg31_out => slv_reg31_out, -- 0x8000_007C * - slv_reg32_out => slv_reg32_out, -- 0x8000_0080 - slv_reg33_out => slv_reg33_out, -- 0x8000_0084 * - slv_reg34_out => slv_reg34_out, -- 0x8000_0088 * - slv_reg35_out => slv_reg35_out, -- 0x8000_008C - slv_reg36_out => slv_reg36_out, -- 0x8000_0090 + slv_reg29_out => open, -- 0x8000_0074 + slv_reg30_out => open, -- 0x8000_0078 + slv_reg31_out => open, -- 0x8000_007C + slv_reg32_out => open, -- 0x8000_0080 + slv_reg33_out => open, -- 0x8000_0084 + slv_reg34_out => open, -- 0x8000_0088 + slv_reg35_out => open, -- 0x8000_008C + slv_reg36_out => open, -- 0x8000_0090 - slv_reg37_out => slv_reg37_out, -- 0x8000_0094 - slv_reg38_out => slv_reg38_out, -- 0x8000_0098 - slv_reg39_out => slv_reg39_out, -- 0x8000_009C * - slv_reg40_out => slv_reg40_out, -- 0x8000_00A0 - slv_reg41_out => slv_reg41_out, -- 0x8000_00A4 * - slv_reg42_out => slv_reg42_out, -- 0x8000_00A8 * - slv_reg43_out => slv_reg43_out, -- 0x8000_00AC - slv_reg44_out => slv_reg44_out, -- 0x8000_00B0 - - slv_reg45_out => slv_reg45_out, -- 0x8000_00B4 - slv_reg46_out => slv_reg46_out, -- 0x8000_00B8 - slv_reg47_out => slv_reg47_out, -- 0x8000_00BC * - slv_reg48_out => slv_reg48_out, -- 0x8000_00C0 - slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4 * - slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8 * + slv_reg37_out => open, -- 0x8000_0094 + slv_reg38_out => open, -- 0x8000_0098 + slv_reg39_out => open, -- 0x8000_009C + slv_reg40_out => open, -- 0x8000_00A0 + slv_reg41_out => open, -- 0x8000_00A4 + slv_reg42_out => open, -- 0x8000_00A8 + slv_reg43_out => open, -- 0x8000_00AC + slv_reg44_out => open, -- 0x8000_00B0 + + slv_reg45_out => open, -- 0x8000_00B4 + slv_reg46_out => open, -- 0x8000_00B8 + slv_reg47_in => cmac_0_tx_tvalid_512b_cnt_in, -- 0x8000_00BC + slv_reg48_in => cmac_0_rx_tvalid_512b_cnt_in, -- 0x8000_00C0 + slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4 + slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8 slv_reg51_in => dig_iq_interface_ready_1_cnt_r, -- 0x8000_00CC slv_reg52_in => adc_rx_tvalid_128b_overflow_cnt_in, -- 0x8000_00D0 @@ -415,7 +399,7 @@ begin slv_reg54_in => qsfp1_capture_overflow_240b_cnt_in, -- 0x8000_00D8 slv_reg55_in => qsfp4_playback_tvalid_128b_cnt_in, -- 0x8000_00DC - slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0 + slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0 slv_reg57_in => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 0x8000_00E4 slv_reg58_in => adc_rx_tvalid_128b_cnt_in, -- 0x8000_00E8 slv_reg59_in => fiber_tx_tvalid_128b_cnt_in, -- 0x8000_00EC @@ -455,12 +439,12 @@ begin slv_reg1(2) <= qsfp1_intl; slv_reg1(3) <= '0'; slv_reg1(4) <= '0'; --dig_iq_interface_ready_1(0); - slv_reg1(5) <= '1'; --qsfp2_modprsl; - slv_reg1(6) <= '1'; --qsfp2_intl; + slv_reg1(5) <= qsfp2_modprsl; + slv_reg1(6) <= qsfp2_intl; slv_reg1(7) <= '0'; slv_reg1(8) <= '0'; --dig_iq_interface_ready_1(1); - slv_reg1(9) <= '1'; --qsfp3_modprsl; - slv_reg1(10) <= '1'; --qsfp3_intl; + slv_reg1(9) <= qsfp3_modprsl; + slv_reg1(10) <= qsfp3_intl; slv_reg1(11) <= '0'; slv_reg1(12) <= dig_iq_interface_ready(1); slv_reg1(13) <= qsfp4_modprsl; @@ -477,7 +461,9 @@ begin -- dig_iq_cmd_strb_i <= slv_reg5(0); -- 0x8000_0014 qsfp1_reset_n_i <= slv_reg5(16); - qsfp4_reset_n_i <= slv_reg5(24); + qsfp2_reset_n_i <= slv_reg5(20); + qsfp3_reset_n_i <= slv_reg5(24); + qsfp4_reset_n_i <= slv_reg5(28); -- dig_iq_cmd_wdata_i <= slv_reg6(31 downto 0); -- 0x8000_0018 -- @@ -512,6 +498,14 @@ begin QSFP1_RESETL_LS <= qsfp1_reset_n; qsfp1_modprsl <= QSFP1_MODPRSL_LS; qsfp1_intl <= QSFP1_INTL_LS; +------- + QSFP2_RESETL_LS <= qsfp2_reset_n; + qsfp2_modprsl <= QSFP2_MODPRSL_LS; + qsfp2_intl <= QSFP2_INTL_LS; +------- + QSFP3_RESETL_LS <= qsfp3_reset_n; + qsfp3_modprsl <= QSFP3_MODPRSL_LS; + qsfp3_intl <= QSFP3_INTL_LS; ------- QSFP4_TX1_P <= qsfp4_tx_txp(0); QSFP4_TX1_N <= qsfp4_tx_txn(0); @@ -545,6 +539,8 @@ begin qsfp1_reset_n <= qsfp1_reset_n_i; dig_iq_interface_reset(0) <= not qsfp1_reset_n; + qsfp2_reset_n <= qsfp2_reset_n_i; + qsfp3_reset_n <= qsfp3_reset_n_i; qsfp4_reset_n <= qsfp4_reset_n_i; dig_iq_interface_reset(1) <= not qsfp4_reset_n; @@ -870,20 +866,6 @@ begin end if; end process; - process(qsfp3_clk_in) - begin - if (rising_edge(qsfp3_clk_in)) then - qsfp3_clk_tick_1ms_r <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms; - if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then - qsfp3_clk_freq_r <= qsfp3_clk_cnt_r; - qsfp3_clk_cnt_r <= (others => '0'); - else - qsfp3_clk_cnt_r <= qsfp3_clk_cnt_r + 1; - end if; - end if; - end process; - - process(pl_clk3_0) begin if (rising_edge(pl_clk3_0)) then diff --git a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd index 39c8905..86bc56c 100644 --- a/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd +++ b/ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd @@ -68,8 +68,8 @@ entity qsfp_intfc_v1_0_S00_AXI is slv_reg44_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg45_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg46_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - slv_reg47_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); - slv_reg48_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + slv_reg47_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + slv_reg48_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg49_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg50_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); slv_reg51_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); @@ -374,41 +374,41 @@ begin slv_reg19 <= (others => '0'); slv_reg20 <= (others => '0'); - slv_reg21 <= x"00008000"; --(UP-SWEEP) from 1MHz to 5MHz in 5uS - slv_reg22 <= x"00000000"; - slv_reg23 <= x"0000D6BF"; - slv_reg24 <= x"00000000"; - slv_reg25 <= x"000004E2"; --(~5 us) - slv_reg26 <= x"010624DD"; --(~1 MHz) - slv_reg27 <= x"00000000"; - slv_reg28 <= x"00008000"; + slv_reg21 <= (others => '0'); + slv_reg22 <= (others => '0'); + slv_reg23 <= (others => '0'); + slv_reg24 <= (others => '0'); + slv_reg25 <= (others => '0'); + slv_reg26 <= (others => '0'); + slv_reg27 <= (others => '0'); + slv_reg28 <= (others => '0'); - slv_reg29 <= x"00008000"; --(DOWN-SWEEP) - slv_reg30 <= x"00000000"; - slv_reg31 <= x"00FEF391"; - slv_reg32 <= x"00000000"; - slv_reg33 <= x"000004E2"; --(~5 us) - slv_reg34 <= x"0624DD2F"; --(~6 MHz) - slv_reg35 <= x"00000000"; - slv_reg36 <= x"00008000"; + slv_reg29 <= (others => '0'); + slv_reg30 <= (others => '0'); + slv_reg31 <= (others => '0'); + slv_reg32 <= (others => '0'); + slv_reg33 <= (others => '0'); + slv_reg34 <= (others => '0'); + slv_reg35 <= (others => '0'); + slv_reg36 <= (others => '0'); - slv_reg37 <= x"00008000"; --(CW) - slv_reg38 <= x"00000000"; - slv_reg39 <= x"00000000"; - slv_reg40 <= x"00000000"; - slv_reg41 <= x"000004E2"; --(~5 us) - slv_reg42 <= x"0A3D70A3"; --(~10 MHz) - slv_reg43 <= x"00000000"; - slv_reg44 <= x"00008000"; + slv_reg37 <= (others => '0'); + slv_reg38 <= (others => '0'); + slv_reg39 <= (others => '0'); + slv_reg40 <= (others => '0'); + slv_reg41 <= (others => '0'); + slv_reg42 <= (others => '0'); + slv_reg43 <= (others => '0'); + slv_reg44 <= (others => '0'); - slv_reg45 <= x"00008000"; --(CW) - slv_reg46 <= x"00000000"; - slv_reg47 <= x"00000000"; - slv_reg48 <= x"00000000"; - slv_reg49 <= x"000004E2"; --(~5 us) - slv_reg50 <= x"0F5C28F5"; --(~15 MHz) - slv_reg51 <= x"00000000"; - slv_reg52 <= x"00008000"; + slv_reg45 <= (others => '0'); + slv_reg46 <= (others => '0'); + slv_reg47 <= (others => '0'); + slv_reg48 <= (others => '0'); + slv_reg49 <= (others => '0'); + slv_reg50 <= (others => '0'); + slv_reg51 <= (others => '0'); + slv_reg52 <= (others => '0'); slv_reg53 <= (others => '0'); slv_reg54 <= (others => '0'); @@ -1202,9 +1202,9 @@ begin when b"101110" => reg_data_out <= slv_reg46; when b"101111" => - reg_data_out <= slv_reg47; + reg_data_out <= slv_reg47_in; when b"110000" => - reg_data_out <= slv_reg48; + reg_data_out <= slv_reg48_in; when b"110001" => reg_data_out <= slv_reg49_in; --slv_reg49; when b"110010" => @@ -1314,8 +1314,6 @@ begin slv_reg44_out <= slv_reg44; slv_reg45_out <= slv_reg45; slv_reg46_out <= slv_reg46; - slv_reg47_out <= slv_reg47; - slv_reg48_out <= slv_reg48; -- User logic ends diff --git a/sim/dds_wrapper_tb.vhd b/sim/dds_wrapper_tb.vhd index c833f3d..ae98135 100644 --- a/sim/dds_wrapper_tb.vhd +++ b/sim/dds_wrapper_tb.vhd @@ -149,7 +149,6 @@ begin cmd_idx_in => "000", dac_holdoff_in => dac_holdoff_r, - dds_chan_en_in => "1111", cmd_send_0_in => cmd_send_0_r(0), scale_0_in => x"8000", @@ -166,7 +165,7 @@ begin dds_phase_inc_dwell_time_1_in => x"00000000", dds_phase_inc_step_size_1_in => x"0000D6BF", idle_samples_1_in => x"00000000", - dds_samples_1_in => x"000014E2", --x"000004E2", + dds_samples_1_in => x"000004E2", --x"000004E2", phase_inc_1_in => x"010624DD", phase_off_1_in => x"00000000", swap_sf_1_in => x"00008000", @@ -193,13 +192,19 @@ begin m_axis_aclk_in => clk_250, m_axis_aresetn_in => clk_250_aresetn(0), - m_axis_tdata_out => m_axis_tdata, - m_axis_tvalid_out => m_axis_tvalid, - m_axis_tready_in => m_axis_tready, + m0_axis_tdata_out => m_axis_tdata, + m0_axis_tvalid_out => m_axis_tvalid, + m0_axis_tready_in => m_axis_tready, + m1_axis_tdata_out => open, + m1_axis_tvalid_out => open, + m1_axis_tready_in => '1', + cnt_reset_in => cnt_reset, - m_axis_tvalid_cnt_out => open, - dds_pulse_data_cnt_out => open + m0_axis_tvalid_cnt_out => open, + m0_dds_pulse_data_cnt_out => open, + m1_axis_tvalid_cnt_out => open, + m1_dds_pulse_data_cnt_out => open ); diff --git a/source/axis_demux_128b.vhd b/source/axis_demux_128b.vhd new file mode 100644 index 0000000..b63bf2e --- /dev/null +++ b/source/axis_demux_128b.vhd @@ -0,0 +1,46 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library xpm; +use xpm.vcomponents.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity axis_demux_128b is + port ( + aselect : in std_logic; + + s_axis_tdata : in std_logic_vector(127 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + + m0_axis_tdata : out std_logic_vector(127 downto 0); + m0_axis_tvalid : out std_logic; + m0_axis_tready : in std_logic; + + m1_axis_tdata : out std_logic_vector(127 downto 0); + m1_axis_tvalid : out std_logic; + m1_axis_tready : in std_logic + ); +end entity axis_demux_128b; + +architecture imp of axis_demux_128b is + +begin + + m0_axis_tdata <= s_axis_tdata; + m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0'; + + m1_axis_tdata <= s_axis_tdata; + m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0'; + + s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready; + +end imp; + diff --git a/source/axis_mux_128b.vhd b/source/axis_mux_128b.vhd index 7783575..fbd3207 100644 --- a/source/axis_mux_128b.vhd +++ b/source/axis_mux_128b.vhd @@ -14,9 +14,7 @@ use xpm.vcomponents.all; entity axis_mux_128b is port ( - aclk : in STD_LOGIC; - aresetn : in std_logic; - aselect : in std_logic_vector(1 downto 0); + aselect : in std_logic_vector(2 downto 0); s0_axis_tdata : in std_logic_vector(127 downto 0); s0_axis_tvalid : in std_logic; @@ -34,6 +32,10 @@ entity axis_mux_128b is s3_axis_tvalid : in std_logic; s3_axis_tready : out std_logic; + s4_axis_tdata : in std_logic_vector(127 downto 0); + s4_axis_tvalid : in std_logic; + s4_axis_tready : out std_logic; + m_axis_tdata : out std_logic_vector(127 downto 0); m_axis_tvalid : out std_logic; m_axis_tready : in std_logic @@ -43,23 +45,24 @@ end entity axis_mux_128b; architecture imp of axis_mux_128b is begin - - m_axis_tdata <= s0_axis_tdata when aselect = "00" else - s1_axis_tdata when aselect = "01" else - s2_axis_tdata when aselect = "10" else - s3_axis_tdata; + m_axis_tdata <= s0_axis_tdata when aselect = "000" else + s1_axis_tdata when aselect = "001" else + s2_axis_tdata when aselect = "010" else + s3_axis_tdata when aselect = "011" else + s4_axis_tdata; - m_axis_tvalid <= s0_axis_tvalid when aselect = "00" else - s1_axis_tvalid when aselect = "01" else - s2_axis_tvalid when aselect = "10" else - s3_axis_tvalid; + m_axis_tvalid <= s0_axis_tvalid when aselect = "000" else + s1_axis_tvalid when aselect = "001" else + s2_axis_tvalid when aselect = "010" else + s3_axis_tvalid when aselect = "011" else + s4_axis_tvalid; - s0_axis_tready <= m_axis_tready when aselect = "00" else '0'; - s1_axis_tready <= m_axis_tready when aselect = "01" else '0'; - s2_axis_tready <= m_axis_tready when aselect = "10" else '0'; - s3_axis_tready <= m_axis_tready when aselect = "11" else '0'; - + s0_axis_tready <= m_axis_tready when aselect = "000" else '0'; + s1_axis_tready <= m_axis_tready when aselect = "001" else '0'; + s2_axis_tready <= m_axis_tready when aselect = "010" else '0'; + s3_axis_tready <= m_axis_tready when aselect = "011" else '0'; + s4_axis_tready <= m_axis_tready when aselect = "100" else '0'; end imp; diff --git a/source/axis_mux_512b.vhd b/source/axis_mux_512b.vhd new file mode 100644 index 0000000..36a9109 --- /dev/null +++ b/source/axis_mux_512b.vhd @@ -0,0 +1,47 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +Library xpm; +use xpm.vcomponents.all; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity axis_mux_512b is + port ( + aselect : in std_logic; + + s0_axis_tdata : in std_logic_vector(511 downto 0); + s0_axis_tvalid : in std_logic; + s0_axis_tready : out std_logic; + + s1_axis_tdata : in std_logic_vector(511 downto 0); + s1_axis_tvalid : in std_logic; + s1_axis_tready : out std_logic; + + m_axis_tdata : out std_logic_vector(511 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic + ); +end entity axis_mux_512b; + +architecture imp of axis_mux_512b is + +begin + + m_axis_tdata <= s0_axis_tdata when aselect = '0' else + s1_axis_tdata; + + m_axis_tvalid <= s0_axis_tvalid when aselect = '0' else + s1_axis_tvalid; + + s0_axis_tready <= m_axis_tready when aselect = '0' else '0'; + s1_axis_tready <= m_axis_tready when aselect = '1' else '0'; + +end imp; + diff --git a/source/axis_mux_s2_128b.vhd b/source/axis_mux_s2_128b.vhd index 2490caa..7663261 100644 --- a/source/axis_mux_s2_128b.vhd +++ b/source/axis_mux_s2_128b.vhd @@ -14,8 +14,6 @@ use xpm.vcomponents.all; entity axis_mux_s2_128b is port ( - aclk : in STD_LOGIC; - aresetn : in std_logic; aselect : in std_logic; s0_axis_tdata : in std_logic_vector(127 downto 0); diff --git a/source/eth_flowctrl_rx.vhd b/source/eth_flowctrl_rx.vhd new file mode 100644 index 0000000..9c05693 --- /dev/null +++ b/source/eth_flowctrl_rx.vhd @@ -0,0 +1,79 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M Blevins +-- +-- Create Date: 01/05/2026 11:59:12 AM +-- Design Name: +-- Module Name: eth_flowctrl_rx - behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eth_flowctrl_rx is + Port ( + clk : in STD_LOGIC; + resetn : in STD_LOGIC; + rx_pause : in STD_LOGIC; + rx_pause_quanta8 : in STD_LOGIC_VECTOR(15 downto 0); + rx_pause_cnt : out std_logic_vector(31 downto 0); + pause : out STD_LOGIC + ); +end eth_flowctrl_rx; + +architecture behavioral of eth_flowctrl_rx is + + signal pause_r : std_logic := '0'; + signal cnt_r : unsigned(15 downto 0) := (others => '0'); + signal rx_pause_cnt_r : unsigned(31 downto 0) := (others => '0'); + +begin + + pause <= pause_r; + rx_pause_cnt <= std_logic_vector(rx_pause_cnt_r); + + process(clk) + begin + if(rising_edge(clk))then + if(resetn = '0')then + cnt_r <= (others => '0'); + pause_r <= '0'; + rx_pause_cnt_r <= (others => '0'); + else + if(rx_pause = '1')then + rx_pause_cnt_r <= rx_pause_cnt_r +1; + cnt_r <= unsigned(rx_pause_quanta8); + if(unsigned(rx_pause_quanta8) = 0)then + pause_r <= '0'; + else + pause_r <= '1'; + end if; + else + if(cnt_r > 0)then + cnt_r <= cnt_r -1; + end if; + if(cnt_r = 1)then + pause_r <= '0'; + end if; + end if; + end if; + end if; + end process; + + +end behavioral; diff --git a/source/eth_flowctrl_tx.vhd b/source/eth_flowctrl_tx.vhd new file mode 100644 index 0000000..364133c --- /dev/null +++ b/source/eth_flowctrl_tx.vhd @@ -0,0 +1,135 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: Jason M Blevins +-- +-- Create Date: 01/05/2026 11:59:12 AM +-- Design Name: +-- Module Name: eth_flowctrl_tx - behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eth_flowctrl_tx is + Port ( + clk : in STD_LOGIC; + resetn : in STD_LOGIC; + prog_full_manual : in STD_LOGIC; + data_cnt : in STD_LOGIC_VECTOR(31 downto 0); + prog_full_on : in STD_LOGIC_VECTOR(31 downto 0); + prog_full_off : in STD_LOGIC_VECTOR(31 downto 0); + ctl_tx_resend_pause : out STD_LOGIC; + ctl_tx_pause_req : out STD_LOGIC_VECTOR (8 downto 0); + tx_pause_cnt : out std_logic_vector(31 downto 0) + ); +end eth_flowctrl_tx; + +architecture behavioral of eth_flowctrl_tx is + + signal cnt : unsigned(3 downto 0); + signal cnt_r : unsigned(3 downto 0) := (others => '0'); + signal tx_pause_cnt_i : unsigned(31 downto 0); + signal tx_pause_cnt_r : unsigned(31 downto 0) := (others => '0'); + type state_type is (s0, s1, s2, s3); + signal state : state_type; + signal state_r : state_type := s0; + signal resend_pause : std_logic; + signal pause_req : std_logic_vector(8 downto 0); + signal resend_pause_r : std_logic := '0'; + signal pause_req_r : std_logic_vector(8 downto 0) := (others => '0'); + signal prog_full_r : std_logic := '0'; + +begin + + ctl_tx_resend_pause <= resend_pause_r; + ctl_tx_pause_req <= pause_req_r; + tx_pause_cnt <= std_logic_vector(tx_pause_cnt_r); + + process(clk) + begin + if(rising_edge(clk))then + if(resetn = '0')then + resend_pause_r <= '0'; + pause_req_r <= (others => '0'); + state_r <= s0; + cnt_r <= (others => '0'); + prog_full_r <= '0'; + tx_pause_cnt_r <= (others => '0'); + else + resend_pause_r <= resend_pause; + pause_req_r <= pause_req; + state_r <= state; + cnt_r <= cnt; + tx_pause_cnt_r <= tx_pause_cnt_i; + if(unsigned(data_cnt) > unsigned(prog_full_on) or prog_full_manual = '1')then + prog_full_r <= '1'; + elsif (unsigned(data_cnt) <= unsigned(prog_full_off) and prog_full_manual = '0')then + prog_full_r <= '0'; + end if; + end if; + end if; + end process; + + process(state_r, cnt_r, prog_full_r, resend_pause_r, pause_req_r, tx_pause_cnt_r) + begin + -- defaults + state <= state_r; + cnt <= cnt_r; + resend_pause <= resend_pause_r; + pause_req <= pause_req_r; + tx_pause_cnt_i <= tx_pause_cnt_r; + + case state_r is + when s0 => + if(prog_full_r = '1')then + state <= s1; + tx_pause_cnt_i <= tx_pause_cnt_r +1; + end if; + + when s1 => + pause_req <= "100000000"; + cnt <= cnt_r +1; + if(cnt_r = 15)then + state <= s2; + end if; + + when s2 => + if(prog_full_r = '0')then + state <= s3; + tx_pause_cnt_i <= tx_pause_cnt_r +1; + end if; + + when s3 => + pause_req <= (others => '0'); + cnt <= cnt_r +1; + if(cnt_r = 0)then + resend_pause <= '1'; + else + resend_pause <= '0'; + end if; + if(cnt_r = 15)then + state <= s0; + end if; + + when others => + end case; + + end process; + + +end behavioral; diff --git a/source/eth_frame_packer.vhd b/source/eth_frame_packer.vhd new file mode 100644 index 0000000..bad0e22 --- /dev/null +++ b/source/eth_frame_packer.vhd @@ -0,0 +1,258 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/30/2025 05:40:20 PM +-- Design Name: +-- Module Name: eth_frame_packer - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity eth_frame_packer is + port ( + clk : in std_logic; + resetn : in std_logic; + + pause : in std_logic := '0'; + cfg_dst_mac : in std_logic_vector(47 downto 0); -- DA + cfg_src_mac : in std_logic_vector(47 downto 0); -- SA + cfg_eth_type : in std_logic_vector(15 downto 0); -- EtherType/Length + + -- AXIS payload in (512-bit, 64B beats; multiples of 64B, aligned) + s_axis_tdata : in std_logic_vector(511 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tready : out std_logic; + s_axis_tlast : in std_logic; + + -- AXIS to CMAC TX client (512-bit) + m_axis_tdata : out std_logic_vector(511 downto 0); + m_axis_tkeep : out std_logic_vector(63 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tready : in std_logic; + m_axis_tlast : out std_logic; + m_axis_tuser : out std_logic; -- error flag to CMAC + + tx_cnt : out std_logic_vector(31 downto 0); + underrun_cnt : out std_logic_vector(31 downto 0) := (others => '0') + ); +end entity; + +architecture rtl of eth_frame_packer is + + --------------------------------------------------------------------------- + -- Functions (VHDL-93 safe) + --------------------------------------------------------------------------- + function mk_header( + da : std_logic_vector(47 downto 0); + sa : std_logic_vector(47 downto 0); + ety : std_logic_vector(15 downto 0) + ) return std_logic_vector is + variable h : std_logic_vector(111 downto 0); + begin + -- DA [0..5] + h( 7 downto 0) := da(47 downto 40); + h( 15 downto 8) := da(39 downto 32); + h( 23 downto 16) := da(31 downto 24); + h( 31 downto 24) := da(23 downto 16); + h( 39 downto 32) := da(15 downto 8); + h( 47 downto 40) := da( 7 downto 0); + -- SA [6..11] + h( 55 downto 48) := sa(47 downto 40); + h( 63 downto 56) := sa(39 downto 32); + h( 71 downto 64) := sa(31 downto 24); + h( 79 downto 72) := sa(23 downto 16); + h( 87 downto 80) := sa(15 downto 8); + h( 95 downto 88) := sa( 7 downto 0); + -- Type/Len [12..13] + h(103 downto 96) := ety(15 downto 8); + h(111 downto 104) := ety( 7 downto 0); + return h; + end function; + + --------------------------------------------------------------------------- + -- + --------------------------------------------------------------------------- + type state_type is (IDLE, RUN, FLUSH); + signal state : state_type; + signal state_r : state_type := IDLE; + signal carry_r : std_logic_vector(111 downto 0) := (others => '0'); + signal carry : std_logic_vector(111 downto 0); + signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0'); + signal m_tdata : std_logic_vector(511 downto 0); + signal m_tkeep_r : std_logic_vector(63 downto 0) := (others => '1'); + signal m_tkeep : std_logic_vector(63 downto 0); + signal m_tlast_r : std_logic := '0'; + signal m_tlast : std_logic; + signal m_tvalid_r : std_logic := '0'; + signal m_tvalid : std_logic; + signal m_tuser_r : std_logic := '0'; + signal m_tuser : std_logic; + signal header : std_logic_vector(111 downto 0); + signal underrun_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + signal tx_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + +begin + + header <= mk_header(cfg_dst_mac, cfg_src_mac, cfg_eth_type); + + --------------------------------------------------------------------------- + -- Drive Outputs + --------------------------------------------------------------------------- + m_axis_tuser <= m_tuser_r; + m_axis_tdata <= m_tdata_r; + m_axis_tkeep <= m_tkeep_r; + m_axis_tlast <= m_tlast_r; + m_axis_tvalid <= m_tvalid_r; + underrun_cnt <= underrun_cnt_r; + tx_cnt <= tx_cnt_r; + + --------------------------------------------------------------------------- + -- Combinational next-state / next-data + --------------------------------------------------------------------------- + process(state_r, carry_r, s_axis_tlast, s_axis_tvalid, m_axis_tready, m_tvalid_r, + m_tdata_r, m_tkeep_r, m_tlast_r, m_tuser_r, header, s_axis_tdata, pause) + begin + -- Defaults + state <= state_r; + carry <= carry_r; + m_tdata <= m_tdata_r; + m_tkeep <= m_tkeep_r; + m_tlast <= m_tlast_r; + m_tuser <= m_tuser_r; + m_tvalid <= m_tvalid_r; + s_axis_tready <= '0'; + + case state_r is + ----------------------------------------------------------------------- + when IDLE => + + --s_axis_tready <= m_axis_tready or not(m_tvalid_r); + + --m_tvalid <= (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0')) or (not(m_axis_tready) and m_tvalid_r); + if(m_axis_tready = '1')then + m_tvalid <= '0'; + end if; + + if (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0') and pause = '0') then + + s_axis_tready <= '1'; + + -- Emit first beat = [14B header] ++ [first 50B payload] + m_tdata <= s_axis_tdata(399 downto 0) & header; + m_tkeep <= (others => '1'); + m_tvalid <= '1'; + m_tuser <= '0'; + m_tlast <= '0'; + + -- Next carry = bytes 50..63 + carry <= s_axis_tdata(511 downto 400); + + if s_axis_tlast = '1' then + state <= FLUSH; + else + state <= RUN; + end if; + + end if; + + ----------------------------------------------------------------------- + when RUN => + + s_axis_tready <= m_axis_tready; + + if(s_axis_tvalid = '0')then + m_tuser <= '1'; -- s_axis_tvalid must be '1' or else this is an error condition, tx data underrun. + end if; + + if (m_axis_tready = '1') then + + -- Steady-state emit = [prev carry 14B] ++ [new payload 0..49] + m_tdata <= s_axis_tdata(399 downto 0) & carry_r; + --m_tkeep <= (others => '1'); + --m_tvalid <= '1'; + --m_tlast <= '0'; + + -- Next carry = bytes 50..63 + carry <= s_axis_tdata(511 downto 400); + + if s_axis_tlast = '1' then + state <= FLUSH; + else + state <= RUN; + end if; + end if; + + ----------------------------------------------------------------------- + when FLUSH => + + --s_axis_tready <= '0'; + + -- if(s_axis_tvalid = '0')then + -- m_tuser <= '1'; + -- end if; + + if (m_axis_tready = '1') then + + -- Emit the final 14B tail + m_tdata <= std_logic_vector(to_unsigned(0, 400)) & carry_r; + m_tkeep <= x"0000000000003FFF"; + m_tlast <= '1'; + --m_tvalid <= '1'; + + state <= IDLE; + end if; + + --when others => + + end case; + end process; + + --------------------------------------------------------------------------- + -- Registers + --------------------------------------------------------------------------- + seq_proc : process(clk) + begin + if rising_edge(clk) then + if resetn = '0' then + state_r <= IDLE; + m_tvalid_r <= '0'; + underrun_cnt_r <= (others => '0'); + tx_cnt_r <= (others => '0'); + else + state_r <= state; + m_tvalid_r <= m_tvalid; + + if(m_tlast_r = '1' and m_tvalid_r = '1' and m_tuser_r = '1' and m_axis_tready = '1')then + underrun_cnt_r <= std_logic_vector(unsigned(underrun_cnt_r) +1); + end if; + + if(m_tlast_r = '1' and m_tvalid_r = '1' and m_axis_tready = '1')then + tx_cnt_r <= std_logic_vector(unsigned(tx_cnt_r) +1); + end if; + + end if; + carry_r <= carry; + m_tdata_r <= m_tdata; + m_tkeep_r <= m_tkeep; + m_tlast_r <= m_tlast; + m_tuser_r <= m_tuser; + end if; + end process; + +end architecture; + diff --git a/source/eth_frame_unpacker.vhd b/source/eth_frame_unpacker.vhd new file mode 100644 index 0000000..e084880 --- /dev/null +++ b/source/eth_frame_unpacker.vhd @@ -0,0 +1,145 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09/30/2025 05:47:45 PM +-- Design Name: +-- Module Name: eth_frame_unpacker - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity eth_frame_unpacker is + port ( + clk : in std_logic; + resetn : in std_logic; -- active-low synchronous reset + + s_axis_tdata : in std_logic_vector(511 downto 0); + s_axis_tvalid : in std_logic; + s_axis_tlast : in std_logic; + s_axis_tkeep : in std_logic_vector(63 downto 0); + s_axis_tuser : in std_logic; -- frame error indicator (qualified by s_axis_tvalid and s_axis_tlast) + + m_axis_tdata : out std_logic_vector(511 downto 0); + m_axis_tvalid : out std_logic; + m_axis_tlast : out std_logic; + m_axis_tuser : out std_logic; -- frame error indicator (qualified by m_axis_tvalid and m_axis_tlast) + + rx_frame_err_cnt : out std_logic_vector(31 downto 0); + rx_frame_cnt : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture rtl of eth_frame_unpacker is + + type state_type is (IDLE, RUN); + + signal state_r : state_type := IDLE; + signal state : state_type; + signal carry : std_logic_vector(399 downto 0); + signal carry_r : std_logic_vector(399 downto 0) := (others => '0'); + signal frame_err_cnt_i : std_logic_vector(31 downto 0); + signal frame_err_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + signal frame_cnt_i : std_logic_vector(31 downto 0); + signal frame_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); + signal m_tvalid : std_logic; + signal m_tvalid_r : std_logic := '0'; + signal m_tdata : std_logic_vector(511 downto 0); + signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0'); + signal m_tuser : std_logic; + signal m_tuser_r : std_logic := '0'; + signal m_tlast : std_logic; + signal m_tlast_r : std_logic := '0'; + +begin + + -- Drive outputs + m_axis_tuser <= m_tuser_r; + m_axis_tdata <= m_tdata_r; + m_axis_tlast <= m_tlast_r; + m_axis_tvalid <= m_tvalid_r; + rx_frame_err_cnt <= frame_err_cnt_r; + rx_frame_cnt <= frame_cnt_r; + + ----------------------------------------------------------------------------- + -- Combinational next-state / next-data + ----------------------------------------------------------------------------- + process(state_r, carry_r, m_tdata_r, m_tuser_r, m_tlast_r, frame_err_cnt_r, + s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser, frame_cnt_r) + begin + -- Defaults + state <= state_r; + carry <= carry_r; + frame_err_cnt_i <= frame_err_cnt_r; + frame_cnt_i <= frame_cnt_r; + m_tvalid <= '0'; + m_tdata <= m_tdata_r; + m_tuser <= m_tuser_r; + m_tlast <= m_tlast_r; + + case state_r is + ------------------------------------------------------------------------- + when IDLE => + if s_axis_tvalid = '1' then + -- cache high 50B; no output yet (need second beat to form first 64B payload) + carry(399 downto 0) <= s_axis_tdata(511 downto 112); + state <= RUN; + end if; + ------------------------------------------------------------------------- + when RUN => + if s_axis_tvalid = '1' then + carry(399 downto 0) <= s_axis_tdata(511 downto 112); + m_tdata <= s_axis_tdata(111 downto 0) & carry_r; + m_tvalid <= '1'; + m_tuser <= s_axis_tuser; + m_tlast <= s_axis_tlast; + if(s_axis_tlast = '1')then + state <= IDLE; + frame_cnt_i <= std_logic_vector(unsigned(frame_cnt_r) +1); + end if; + if(s_axis_tlast = '1' and s_axis_tuser = '1')then + frame_err_cnt_i <= std_logic_vector(unsigned(frame_err_cnt_r) +1); + end if; + end if; + ------------------------------------------------------------------------- + end case; + end process; + + ----------------------------------------------------------------------------- + -- Regs + ----------------------------------------------------------------------------- + seq_proc : process(clk) + begin + if rising_edge(clk) then + if resetn = '0' then + state_r <= IDLE; + frame_err_cnt_r <= (others => '0'); + frame_cnt_r <= (others => '0'); + m_tvalid_r <= '0'; + else + state_r <= state; + frame_err_cnt_r <= frame_err_cnt_i; + frame_cnt_r <= frame_cnt_i; + m_tvalid_r <= m_tvalid; + end if; + carry_r <= carry; + m_tdata_r <= m_tdata; + m_tuser_r <= m_tuser; + m_tlast_r <= m_tlast; + end if; + end process; +end architecture; + diff --git a/source/system_top.v b/source/system_top.v index a393f45..7cab684 100644 --- a/source/system_top.v +++ b/source/system_top.v @@ -37,8 +37,8 @@ module system_top #( - parameter FPGA_REVISION_DATE = 32'h05282026, - parameter MINOR_REV = 8'h04, + parameter FPGA_REVISION_DATE = 32'h07162026, + parameter MINOR_REV = 8'h01, parameter TX_JESD_L = 8, parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 8, @@ -69,6 +69,35 @@ module system_top #( output QSFP1_TX3_P, output QSFP1_TX4_N, output QSFP1_TX4_P, +// + input QSFP2_INTL_LS, + input QSFP2_MODPRSL_LS, + output QSFP2_RESETL_LS, + input QSFP2_SI570_CLOCK_N,//CLK3_N + input QSFP2_SI570_CLOCK_P, +// + input QSFP3_INTL_LS, + input QSFP3_MODPRSL_LS, + output QSFP3_RESETL_LS, + input QSFP3_RX1_N, + input QSFP3_RX1_P, + input QSFP3_RX2_N, + input QSFP3_RX2_P, + input QSFP3_RX3_N, + input QSFP3_RX3_P, + input QSFP3_RX4_N, + input QSFP3_RX4_P, + input QSFP3_SI570_CLOCK_N,//CLK1_N + input QSFP3_SI570_CLOCK_P, + output QSFP3_TX1_N, + output QSFP3_TX1_P, + output QSFP3_TX2_N, + output QSFP3_TX2_P, + output QSFP3_TX3_N, + output QSFP3_TX3_P, + output QSFP3_TX4_N, + output QSFP3_TX4_P, +// input QSFP4_INTL_LS, input QSFP4_MODPRSL_LS, output QSFP4_RESETL_LS, @@ -90,14 +119,7 @@ module system_top #( output QSFP4_TX3_P, output QSFP4_TX4_N, output QSFP4_TX4_P, - - input QSFP2_SI570_CLOCK_N,//CLK3_N - input QSFP2_SI570_CLOCK_P, - - input QSFP3_SI570_CLOCK_N,//CLK1_N - input QSFP3_SI570_CLOCK_P, - - +// inout pll_scl, inout pll_sda, @@ -220,13 +242,13 @@ module system_top #( wire qsfp1_capture_tvalid_240b; wire [31:0] qsfp1_capture_tvalid_240b_cnt; - wire [31:0] qsfp1_tx_fifo_128_aempty_cnt; + wire [31:0] qsfp1_fifo_128_aempty_cnt; - wire [127:0] tx_tdata_128b; - wire tx_tvalid_128b; - wire tx_tready_128b; + wire [127:0] qsfp1_tdata_128b; + wire qsfp1_tvalid_128b; + wire qsfp1_tready_128b; - wire [31:0] qsfp1_tx_fifo_tvalid_128b_cnt; + wire [31:0] qsfp1_fifo_tvalid_128b_cnt; wire qsfp1_capture_rx_data_ready; wire [31:0] qsfp1_capture_rx_data_ready_cnt; @@ -253,38 +275,7 @@ module system_top #( wire [31:0] slv_reg9; wire [31:0] slv_reg10; - wire [31:0] slv_reg21; - wire [31:0] slv_reg22; - wire [31:0] slv_reg23; - wire [31:0] slv_reg24; - wire [31:0] slv_reg25; - wire [31:0] slv_reg26; - wire [31:0] slv_reg27; - wire [31:0] slv_reg28; - wire [31:0] slv_reg29; - wire [31:0] slv_reg30; - - wire [31:0] slv_reg31; - wire [31:0] slv_reg32; - wire [31:0] slv_reg33; - wire [31:0] slv_reg34; - wire [31:0] slv_reg35; - wire [31:0] slv_reg36; - wire [31:0] slv_reg37; - wire [31:0] slv_reg38; - wire [31:0] slv_reg39; - wire [31:0] slv_reg40; - - wire [31:0] slv_reg41; - wire [31:0] slv_reg42; - wire [31:0] slv_reg43; - wire [31:0] slv_reg44; - wire [31:0] slv_reg45; - wire [31:0] slv_reg46; - wire [31:0] slv_reg47; - wire [31:0] slv_reg48; - - wire [1:0] dac_src_data_sel; + wire [2:0] dac_src_data_sel; wire chan1to4_mode_sel; wire qsfp4_playback_path_data_enable_n; @@ -292,9 +283,6 @@ module system_top #( wire qsfp2_clk; wire qsfp2_clk_bufg; - wire qsfp3_clk; - wire qsfp3_clk_bufg; - wire clk_100; wire clk_100_aresetn; wire [31:0] M11_AXI_0_araddr; @@ -337,6 +325,26 @@ module system_top #( wire [3:0] M12_AXI_0_wstrb; wire M12_AXI_0_wvalid; + wire [31:0] M13_AXI_0_araddr; + wire [2:0] M13_AXI_0_arprot; + wire M13_AXI_0_arready; + wire M13_AXI_0_arvalid; + wire [31:0] M13_AXI_0_awaddr; + wire [2:0] M13_AXI_0_awprot; + wire M13_AXI_0_awready; + wire M13_AXI_0_awvalid; + wire M13_AXI_0_bready; + wire [1:0] M13_AXI_0_bresp; + wire M13_AXI_0_bvalid; + wire [31:0] M13_AXI_0_rdata; + wire M13_AXI_0_rready; + wire [1:0] M13_AXI_0_rresp; + wire M13_AXI_0_rvalid; + wire [31:0] M13_AXI_0_wdata; + wire M13_AXI_0_wready; + wire [3:0] M13_AXI_0_wstrb; + wire M13_AXI_0_wvalid; + wire sda_i; wire sda_o; wire sda_t; @@ -357,6 +365,10 @@ module system_top #( wire m1_dds_pulse_tvalid_128b; wire m1_dds_pulse_tready_128b; + wire [127:0] m1_dds_pulse_fifo_tdata_128b; + wire m1_dds_pulse_fifo_tvalid_128b; + wire m1_dds_pulse_fifo_tready_128b; + wire [127:0] fiber_tx_tdata_128b; wire fiber_tx_tvalid_128b; wire fiber_tx_tready_128b; @@ -369,6 +381,47 @@ module system_top #( wire qsfp1_capture_en_n; wire qsfp1_capture_rst; + + wire [3:0] cmac_gt_0_grx_n; + wire [3:0] cmac_gt_0_grx_p; + wire [3:0] cmac_gt_0_gtx_n; + wire [3:0] cmac_gt_0_gtx_p; + wire cmac_refclk_0_clk_n; + wire cmac_refclk_0_clk_p; + + wire cmac_tx_intfc_en; + wire cmac_rx_intfc_en; + +//// + wire [511:0] cmac_0_tx_tdata_512b; + wire cmac_0_tx_tvalid_512b; + wire cmac_0_tx_tvalid_512b_en; + wire cmac_0_tx_tready_512b; + wire cmac_0_tx_tready_512b_en; + reg [31:0] cmac_0_tx_tvalid_512b_cnt_r = 32'h0; + + wire [511:0] cmac_0_rx_tdata_512b; + wire cmac_0_rx_tvalid_512b; + wire cmac_0_rx_tvalid_512b_en; + wire cmac_0_rx_tready_512b; + wire cmac_0_rx_tready_512b_en; + reg [31:0] cmac_0_rx_tvalid_512b_cnt_r = 32'h0; + + wire [127:0] cmac_0_rx_tdata_128b; + wire cmac_0_rx_tvalid_128b; + wire cmac_0_rx_tready_128b; + + wire [127:0] dds2cmac_fifo_tdata_128b; + wire dds2cmac_fifo_tvalid_128b; + wire dds2cmac_fifo_tready_128b; + + wire dds_out_dest_sel; + wire cmac_tx_src_data_sel; + + wire [511:0] adc_tdata_512b; + wire adc_tvalid_512b; + wire adc_tready_512b; + //////////////////////////////////////////////////////////////// // instantiations @@ -472,27 +525,6 @@ module system_top #( .DIV (3'b000), .O (qsfp2_clk_bufg) ); - -////////// - IBUFDS_GTE4 i_ibufds_qsfp3 ( - .I (QSFP3_SI570_CLOCK_P), - .IB (QSFP3_SI570_CLOCK_N), - .CEB (1'b0), - .O (), - .ODIV2 (qsfp3_clk) - ); - - BUFG_GT i_bufgt_qsfp3 ( - .I (qsfp3_clk), - .CE (1'b1), - .CEMASK (1'b0), - .CLR (1'b0), - .CLRMASK (1'b0), - .DIV (3'b000), - .O (qsfp3_clk_bufg) - ); - - // assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal; @@ -736,6 +768,26 @@ module system_top #( .M12_AXI_0_wstrb (M12_AXI_0_wstrb), .M12_AXI_0_wvalid (M12_AXI_0_wvalid), + .M13_AXI_0_araddr (M13_AXI_0_araddr), + .M13_AXI_0_arprot (M13_AXI_0_arprot), + .M13_AXI_0_arready (M13_AXI_0_arready), + .M13_AXI_0_arvalid (M13_AXI_0_arvalid), + .M13_AXI_0_awaddr (M13_AXI_0_awaddr), + .M13_AXI_0_awprot (M13_AXI_0_awprot), + .M13_AXI_0_awready (M13_AXI_0_awready), + .M13_AXI_0_awvalid (M13_AXI_0_awvalid), + .M13_AXI_0_bready (M13_AXI_0_bready), + .M13_AXI_0_bresp (M13_AXI_0_bresp), + .M13_AXI_0_bvalid (M13_AXI_0_bvalid), + .M13_AXI_0_rdata (M13_AXI_0_rdata), + .M13_AXI_0_rready (M13_AXI_0_rready), + .M13_AXI_0_rresp (M13_AXI_0_rresp), + .M13_AXI_0_rvalid (M13_AXI_0_rvalid), + .M13_AXI_0_wdata (M13_AXI_0_wdata), + .M13_AXI_0_wready (M13_AXI_0_wready), + .M13_AXI_0_wstrb (M13_AXI_0_wstrb), + .M13_AXI_0_wvalid (M13_AXI_0_wvalid), + .Res_0 (), //mxfe_rx_data_offload_s_axis_tready from Rx DMA engine .pl_clk3_0 (pl_clk3_0), @@ -781,7 +833,6 @@ module system_top #( // .sysref_in (sysref), .ref_clk_div2_in (ref_clk_div2_bufg), .qsfp2_clk_in (qsfp2_clk_bufg), - .qsfp3_clk_in (qsfp3_clk_bufg), .pl_clk3_0 (pl_clk3_0), .QSFP1_INTL_LS (QSFP1_INTL_LS), @@ -805,6 +856,15 @@ module system_top #( .QSFP1_TX3_P (QSFP1_TX3_P), .QSFP1_TX4_N (QSFP1_TX4_N), .QSFP1_TX4_P (QSFP1_TX4_P), +/////////// + .QSFP2_RESETL_LS (QSFP2_RESETL_LS), + .QSFP2_MODPRSL_LS (QSFP2_MODPRSL_LS), + .QSFP2_INTL_LS (QSFP2_INTL_LS), +/////////// + .QSFP3_RESETL_LS (QSFP3_RESETL_LS), + .QSFP3_MODPRSL_LS (QSFP3_MODPRSL_LS), + .QSFP3_INTL_LS (QSFP3_INTL_LS), +/////////// .QSFP4_INTL_LS (QSFP4_INTL_LS), .QSFP4_MODPRSL_LS (QSFP4_MODPRSL_LS), .QSFP4_RESETL_LS (QSFP4_RESETL_LS), @@ -842,9 +902,9 @@ module system_top #( .qsfp1_capture_tvalid_240b_cnt_in (qsfp1_capture_tvalid_240b_cnt), .qsfp1_capture_overflow_240b_cnt_in (qsfp1_capture_overflow_240b_cnt), .qsfp1_capture_tvalid_512b_cnt_in (qsfp1_capture_tvalid_512b_cnt), - .qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_tx_fifo_128_aempty_cnt), + .qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_fifo_128_aempty_cnt), .qsfp1_capture_rx_data_ready_cnt_in (qsfp1_capture_rx_data_ready_cnt), - .qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_tx_fifo_tvalid_128b_cnt), + .qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_fifo_tvalid_128b_cnt), .mem_xfer_tx_upload_tvalid_128b_cnt_in (mem_xfer_tx_upload_tvalid_128b_cnt_r), .dac_tx_tvalid_128b_cnt_in (dac_tx_tvalid_128b_cnt_r), @@ -853,44 +913,17 @@ module system_top #( .qsfp4_playback_tvalid_128b_cnt_in (qsfp4_playback_tvalid_128b_cnt), .qsfp4_playback_tvalid_240b_cnt_in (qsfp4_playback_tvalid_240b_cnt), - .fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r), + .fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r), + .cmac_0_tx_tvalid_512b_cnt_in (cmac_0_tx_tvalid_512b_cnt_r), + .cmac_0_rx_tvalid_512b_cnt_in (cmac_0_rx_tvalid_512b_cnt_r), + + .cnt_reset_out (cnt_reset), .slv_reg9_out (slv_reg9), .slv_reg10_out (slv_reg10), - .slv_reg21_out (slv_reg21), - .slv_reg22_out (slv_reg22), - .slv_reg23_out (slv_reg23), - .slv_reg24_out (slv_reg24), - .slv_reg25_out (slv_reg25), - .slv_reg26_out (slv_reg26), - .slv_reg27_out (slv_reg27), - .slv_reg28_out (slv_reg28), - .slv_reg29_out (slv_reg29), - .slv_reg30_out (slv_reg30), - - .slv_reg31_out (slv_reg31), - .slv_reg32_out (slv_reg32), - .slv_reg33_out (slv_reg33), - .slv_reg34_out (slv_reg34), - .slv_reg35_out (slv_reg35), - .slv_reg36_out (slv_reg36), - .slv_reg37_out (slv_reg37), - .slv_reg38_out (slv_reg38), - .slv_reg39_out (slv_reg39), - .slv_reg40_out (slv_reg40), - - .slv_reg41_out (slv_reg41), - .slv_reg42_out (slv_reg42), - .slv_reg43_out (slv_reg43), - .slv_reg44_out (slv_reg44), - .slv_reg45_out (slv_reg45), - .slv_reg46_out (slv_reg46), - .slv_reg47_out (slv_reg47), - .slv_reg48_out (slv_reg48), - .sys_cpu_clk_in (clk_100), .s00_axi_aresetn (clk_100_aresetn), .s00_axi_awaddr (M11_AXI_0_awaddr[7:0]), @@ -918,12 +951,19 @@ module system_top #( //assign = slv_reg10[3:1]; assign qsfp1_capture_rst = slv_reg10[4]; //assign = slv_reg10[7:5]; - assign dac_src_data_sel = slv_reg10[9:8]; -//assign = slv_reg10[11:10]; + assign dac_src_data_sel = slv_reg10[10:8]; +//assign = slv_reg10[11]; assign chan1to4_mode_sel = slv_reg10[12]; //assign = slv_reg10[14:13]; assign qsfp1_capture_en_n = slv_reg10[15]; -//assign = slv_reg10[30:16]; +//assign = slv_reg10[18:16]; + assign cmac_tx_src_data_sel = slv_reg10[19]; +//assign = slv_reg10[23:20]; + assign dds_out_dest_sel = slv_reg10[24]; +//assign = slv_reg10[27:25]; + assign cmac_tx_intfc_en = slv_reg10[28]; + assign cmac_rx_intfc_en = slv_reg10[29]; +//assign = slv_reg10[30]; assign qsfp4_playback_path_data_enable_n = slv_reg10[31]; /////////////////////////////// @@ -942,11 +982,11 @@ module system_top #( .tx_device_clk_in (tx_device_clk_1), .tx_device_clk_aresetn_in (tx_device_clk_aresetn), - .tx_fifo_tdata_128b_out (tx_tdata_128b), // out - .tx_fifo_tvalid_128b_out (tx_tvalid_128b), // out - .tx_fifo_tready_128b_in (tx_tready_128b), // in - .qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_tx_fifo_tvalid_128b_cnt), - .qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_tx_fifo_128_aempty_cnt), + .tx_fifo_tdata_128b_out (qsfp1_tdata_128b), // out + .tx_fifo_tvalid_128b_out (qsfp1_tvalid_128b), // out + .tx_fifo_tready_128b_in (qsfp1_tready_128b), // in + .qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_fifo_tvalid_128b_cnt), + .qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_fifo_128_aempty_cnt), .qsfp1_capture_en_n_in (qsfp1_capture_en_n), .qsfp1_capture_rst_in (qsfp1_capture_rst), @@ -957,17 +997,15 @@ module system_top #( //// to DAC - data source from DMA Tx axis data, QSFP1 and ADC_INTFC ///////////////////////////////////////////// axis_mux_128b i_dac_axis_mux_128b ( - .aclk (tx_device_clk_1), // input - .aresetn (tx_device_clk_aresetn), // input .aselect (dac_src_data_sel), // input .s0_axis_tdata (mem_xfer_tx_upload_tdata_128b), // input .s0_axis_tvalid (mem_xfer_tx_upload_tvalid_128b), // input .s0_axis_tready (mem_xfer_tx_upload_tready_128b), // output - .s1_axis_tdata (tx_tdata_128b), // input - .s1_axis_tvalid (tx_tvalid_128b), // input - .s1_axis_tready (tx_tready_128b), // output + .s1_axis_tdata (qsfp1_tdata_128b), // input + .s1_axis_tvalid (qsfp1_tvalid_128b), // input + .s1_axis_tready (qsfp1_tready_128b), // output .s2_axis_tdata (adc_loopback_tdata_128b_mux), // input .s2_axis_tvalid (adc_loopback_tvalid_128b), // input @@ -977,6 +1015,10 @@ module system_top #( .s3_axis_tvalid (m0_dds_pulse_tvalid_128b), // input .s3_axis_tready (m0_dds_pulse_tready_128b), // output + .s4_axis_tdata (cmac_0_rx_tdata_128b), // input + .s4_axis_tvalid (cmac_0_rx_tvalid_128b), // input + .s4_axis_tready (cmac_0_rx_tready_128b), // output + .m_axis_tdata (dac_tx_tdata_128b), // output .m_axis_tvalid (dac_tx_tvalid_128b), // output .m_axis_tready (dac_tx_tready_128b) // input @@ -1004,14 +1046,28 @@ module system_top #( .s_axis_tready (m1_dds_pulse_tready_128b), // out .m_axis_aclk (rx_device_clk_1), // in - .m_axis_tdata (dds2fiber_fifo_tdata_128b), // out - .m_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out - .m_axis_tready (dds2fiber_fifo_tready_128b) // in + .m_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // out + .m_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // out + .m_axis_tready (m1_dds_pulse_fifo_tready_128b) // in + ); + + axis_demux_128b i_axis_demux_128b ( + .aselect (dds_out_dest_sel), // in + + .s_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // in + .s_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // in + .s_axis_tready (m1_dds_pulse_fifo_tready_128b), // out + + .m0_axis_tdata (dds2fiber_fifo_tdata_128b), // out + .m0_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out + .m0_axis_tready (dds2fiber_fifo_tready_128b), // in + + .m1_axis_tdata (dds2cmac_fifo_tdata_128b), // out + .m1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // out + .m1_axis_tready (dds2cmac_fifo_tready_128b) // in ); axis_mux_s2_128b i_axis_mux_s2_128b ( - .aclk (rx_device_clk_1), // input - .aresetn (rx_device_clk_aresetn), // input .aselect (fiber_tx_src_data_sel), // input .s0_axis_tdata (adc_rx_tdata_128b), // input @@ -1151,6 +1207,145 @@ module system_top #( .s00_axi_rready (M12_AXI_0_rready) ); +/////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + + assign cmac_refclk_0_clk_p = QSFP3_SI570_CLOCK_P; + assign cmac_refclk_0_clk_n = QSFP3_SI570_CLOCK_N; + + assign cmac_gt_0_grx_p[0] = QSFP3_RX1_P; + assign cmac_gt_0_grx_n[0] = QSFP3_RX1_N; + assign cmac_gt_0_grx_p[1] = QSFP3_RX2_P; + assign cmac_gt_0_grx_n[1] = QSFP3_RX2_N; + assign cmac_gt_0_grx_p[2] = QSFP3_RX3_P; + assign cmac_gt_0_grx_n[2] = QSFP3_RX3_N; + assign cmac_gt_0_grx_p[3] = QSFP3_RX4_P; + assign cmac_gt_0_grx_n[3] = QSFP3_RX4_N; + + assign QSFP3_TX1_P = cmac_gt_0_gtx_p[0]; + assign QSFP3_TX1_N = cmac_gt_0_gtx_n[0]; + assign QSFP3_TX2_P = cmac_gt_0_gtx_p[1]; + assign QSFP3_TX2_N = cmac_gt_0_gtx_n[1]; + assign QSFP3_TX3_P = cmac_gt_0_gtx_p[2]; + assign QSFP3_TX3_N = cmac_gt_0_gtx_n[2]; + assign QSFP3_TX4_P = cmac_gt_0_gtx_p[3]; + assign QSFP3_TX4_N = cmac_gt_0_gtx_n[3]; + + raw_eth_wrapper i_raw_eth_cmac_0 ( + .clk_100_0 (clk_100), + .clk_100_reset_0 (clk_100_areset), + + .cmac_gt_0_grx_n (cmac_gt_0_grx_n), //in + .cmac_gt_0_grx_p (cmac_gt_0_grx_p), //in + .cmac_gt_0_gtx_n (cmac_gt_0_gtx_n), //out + .cmac_gt_0_gtx_p (cmac_gt_0_gtx_p), //out + .cmac_refclk_0_clk_n (cmac_refclk_0_clk_n), + .cmac_refclk_0_clk_p (cmac_refclk_0_clk_p), + + .m_axis_aclk (tx_device_clk_1), + .m_axis_aresetn (tx_device_clk_aresetn), + .m_axis_tdata (cmac_0_rx_tdata_512b), // out + .m_axis_tvalid (cmac_0_rx_tvalid_512b), // out + .m_axis_tready (cmac_0_rx_tready_512b_en), // in + + .axil_clk_0 (clk_100), + .axil_resetn_0 (clk_100_aresetn), + + .s_axil_0_awaddr (M13_AXI_0_awaddr), + .s_axil_0_awprot (M13_AXI_0_awprot), + .s_axil_0_awvalid (M13_AXI_0_awvalid), + .s_axil_0_awready (M13_AXI_0_awready), + + .s_axil_0_wdata (M13_AXI_0_wdata), + .s_axil_0_wstrb (M13_AXI_0_wstrb), + .s_axil_0_wvalid (M13_AXI_0_wvalid), + .s_axil_0_wready (M13_AXI_0_wready), + + .s_axil_0_bresp (M13_AXI_0_bresp), + .s_axil_0_bvalid (M13_AXI_0_bvalid), + .s_axil_0_bready (M13_AXI_0_bready), + + .s_axil_0_araddr (M13_AXI_0_araddr), + .s_axil_0_arprot (M13_AXI_0_arprot), + .s_axil_0_arvalid (M13_AXI_0_arvalid), + .s_axil_0_arready (M13_AXI_0_arready), + + .s_axil_0_rdata (M13_AXI_0_rdata), + .s_axil_0_rresp (M13_AXI_0_rresp), + .s_axil_0_rvalid (M13_AXI_0_rvalid), + .s_axil_0_rready (M13_AXI_0_rready), + + .s_axis_clk (rx_device_clk_1), + .s_axis_aresetn (rx_device_clk_aresetn), + .s_axis_tdata (cmac_0_tx_tdata_512b), // in + .s_axis_tvalid (cmac_0_tx_tvalid_512b_en), // in + .s_axis_tready (cmac_0_tx_tready_512b) // out + ); + + axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b ( + .aclk (rx_device_clk_1), // in + .aresetn (rx_device_clk_aresetn), // in + + .s_axis_tdata (adc_rx_tdata_128b), // in + .s_axis_tvalid (adc_rx_tvalid_128b), // in + .s_axis_tready ( ), // out + + .m_axis_tdata (adc_tdata_512b), // out + .m_axis_tvalid (adc_tvalid_512b), // out + .m_axis_tready (adc_tready_512b) // in + ); + + axis_mux_512b i_axis_mux_512b ( + .aselect (cmac_tx_src_data_sel), // input + + .s0_axis_tdata (adc_tdata_512b), // input + .s0_axis_tvalid (adc_tvalid_512b), // input + .s0_axis_tready (adc_tready_512b), // output + + .s1_axis_tdata (dds2cmac_fifo_tdata_128b), // input + .s1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // input + .s1_axis_tready (dds2cmac_fifo_tready_128b), // output + + .m_axis_tdata (cmac_0_tx_tdata_512b), // output + .m_axis_tvalid (cmac_0_tx_tvalid_512b), // output + .m_axis_tready (cmac_0_tx_tready_512b_en) // input + ); + + assign cmac_0_tx_tvalid_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tvalid_512b : 1'b0; + assign cmac_0_tx_tready_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tready_512b : 1'b0; + + always @(posedge rx_device_clk_1) + begin + if (rx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1) + cmac_0_tx_tvalid_512b_cnt_r <= 32'h0; + else if (cmac_0_tx_tvalid_512b_en == 1'b1 && cmac_0_tx_tready_512b_en == 1'b1) + cmac_0_tx_tvalid_512b_cnt_r <= cmac_0_tx_tvalid_512b_cnt_r + 1; + end +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// + assign cmac_0_rx_tvalid_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tvalid_512b : 1'b0; + assign cmac_0_rx_tready_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tready_512b : 1'b0; + + axis_dwidth_converter_512b_to_128b i_axis_dwidth_converter_512b_to_128b_cmac_0 ( + .aclk (tx_device_clk_1), // in + .aresetn (tx_device_clk_aresetn), // in + + .s_axis_tdata (cmac_0_rx_tdata_512b), // in + .s_axis_tvalid (cmac_0_rx_tvalid_512b_en), // in + .s_axis_tready (cmac_0_rx_tready_512b), // out + + .m_axis_tdata (cmac_0_rx_tdata_128b), // out + .m_axis_tvalid (cmac_0_rx_tvalid_128b), // out + .m_axis_tready (cmac_0_rx_tready_128b) // in + ); + + always @(posedge tx_device_clk_1) + begin + if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1) + cmac_0_rx_tvalid_512b_cnt_r <= 32'h0; + else if (cmac_0_rx_tvalid_512b_en == 1'b1 && cmac_0_rx_tready_512b_en == 1'b1) + cmac_0_rx_tvalid_512b_cnt_r <= cmac_0_rx_tvalid_512b_cnt_r + 1; + end ////////////////////////// si5332_wrapper i_si5332_wrapper ( @@ -1163,10 +1358,7 @@ module system_top #( .scl_in (scl_i), .scl_out (scl_o), - .scl_t_out (scl_t), - - .qsfp2_clk_in (qsfp2_clk_bufg), - .qsfp3_clk_in (qsfp3_clk_bufg) + .scl_t_out (scl_t) ); IOBUF i_scl_iobuf (