Erisys/alinx_z19_ad9081
6
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

added CMAC interface out of QSFP3

Browse Source
This commit is contained in:
nsantana
2026-07-17 15:55:55 -04:00
parent 69be245f2a
commit 3f25b73be7
20 changed files with 2869 additions and 524 deletions
Download Patch File Download Diff File Expand all files Collapse all files
source/axis_demux_128b.vhd
+46
View File
@@ -0,0 +1,46 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_demux_128b is
port (
aselect : in std_logic;
s_axis_tdata : in std_logic_vector(127 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
m0_axis_tdata : out std_logic_vector(127 downto 0);
m0_axis_tvalid : out std_logic;
m0_axis_tready : in std_logic;
m1_axis_tdata : out std_logic_vector(127 downto 0);
m1_axis_tvalid : out std_logic;
m1_axis_tready : in std_logic
);
end entity axis_demux_128b;
architecture imp of axis_demux_128b is
begin
m0_axis_tdata <= s_axis_tdata;
m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0';
m1_axis_tdata <= s_axis_tdata;
m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0';
s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready;
end imp;
source/axis_mux_128b.vhd
+20 -17
View File
@@ -14,9 +14,7 @@ use xpm.vcomponents.all;
entity axis_mux_128b is
port (
aclk : in STD_LOGIC;
aresetn : in std_logic;
aselect : in std_logic_vector(1 downto 0);
aselect : in std_logic_vector(2 downto 0);
s0_axis_tdata : in std_logic_vector(127 downto 0);
s0_axis_tvalid : in std_logic;
@@ -34,6 +32,10 @@ entity axis_mux_128b is
s3_axis_tvalid : in std_logic;
s3_axis_tready : out std_logic;
s4_axis_tdata : in std_logic_vector(127 downto 0);
s4_axis_tvalid : in std_logic;
s4_axis_tready : out std_logic;
m_axis_tdata : out std_logic_vector(127 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic
@@ -43,23 +45,24 @@ end entity axis_mux_128b;
architecture imp of axis_mux_128b is
begin
m_axis_tdata <= s0_axis_tdata when aselect = "00" else
s1_axis_tdata when aselect = "01" else
s2_axis_tdata when aselect = "10" else
s3_axis_tdata;
m_axis_tdata <= s0_axis_tdata when aselect = "000" else
s1_axis_tdata when aselect = "001" else
s2_axis_tdata when aselect = "010" else
s3_axis_tdata when aselect = "011" else
s4_axis_tdata;
m_axis_tvalid <= s0_axis_tvalid when aselect = "00" else
s1_axis_tvalid when aselect = "01" else
s2_axis_tvalid when aselect = "10" else
s3_axis_tvalid;
m_axis_tvalid <= s0_axis_tvalid when aselect = "000" else
s1_axis_tvalid when aselect = "001" else
s2_axis_tvalid when aselect = "010" else
s3_axis_tvalid when aselect = "011" else
s4_axis_tvalid;
s0_axis_tready <= m_axis_tready when aselect = "00" else '0';
s1_axis_tready <= m_axis_tready when aselect = "01" else '0';
s2_axis_tready <= m_axis_tready when aselect = "10" else '0';
s3_axis_tready <= m_axis_tready when aselect = "11" else '0';
s0_axis_tready <= m_axis_tready when aselect = "000" else '0';
s1_axis_tready <= m_axis_tready when aselect = "001" else '0';
s2_axis_tready <= m_axis_tready when aselect = "010" else '0';
s3_axis_tready <= m_axis_tready when aselect = "011" else '0';
s4_axis_tready <= m_axis_tready when aselect = "100" else '0';
end imp;
source/axis_mux_512b.vhd
+47
View File
@@ -0,0 +1,47 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity axis_mux_512b is
port (
aselect : in std_logic;
s0_axis_tdata : in std_logic_vector(511 downto 0);
s0_axis_tvalid : in std_logic;
s0_axis_tready : out std_logic;
s1_axis_tdata : in std_logic_vector(511 downto 0);
s1_axis_tvalid : in std_logic;
s1_axis_tready : out std_logic;
m_axis_tdata : out std_logic_vector(511 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic
);
end entity axis_mux_512b;
architecture imp of axis_mux_512b is
begin
m_axis_tdata <= s0_axis_tdata when aselect = '0' else
s1_axis_tdata;
m_axis_tvalid <= s0_axis_tvalid when aselect = '0' else
s1_axis_tvalid;
s0_axis_tready <= m_axis_tready when aselect = '0' else '0';
s1_axis_tready <= m_axis_tready when aselect = '1' else '0';
end imp;
source/axis_mux_s2_128b.vhd
-2
View File
@@ -14,8 +14,6 @@ use xpm.vcomponents.all;
entity axis_mux_s2_128b is
port (
aclk : in STD_LOGIC;
aresetn : in std_logic;
aselect : in std_logic;
s0_axis_tdata : in std_logic_vector(127 downto 0);
source/eth_flowctrl_rx.vhd
+79
View File
@@ -0,0 +1,79 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M Blevins
--
-- Create Date: 01/05/2026 11:59:12 AM
-- Design Name:
-- Module Name: eth_flowctrl_rx - behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity eth_flowctrl_rx is
Port (
clk : in STD_LOGIC;
resetn : in STD_LOGIC;
rx_pause : in STD_LOGIC;
rx_pause_quanta8 : in STD_LOGIC_VECTOR(15 downto 0);
rx_pause_cnt : out std_logic_vector(31 downto 0);
pause : out STD_LOGIC
);
end eth_flowctrl_rx;
architecture behavioral of eth_flowctrl_rx is
signal pause_r : std_logic := '0';
signal cnt_r : unsigned(15 downto 0) := (others => '0');
signal rx_pause_cnt_r : unsigned(31 downto 0) := (others => '0');
begin
pause <= pause_r;
rx_pause_cnt <= std_logic_vector(rx_pause_cnt_r);
process(clk)
begin
if(rising_edge(clk))then
if(resetn = '0')then
cnt_r <= (others => '0');
pause_r <= '0';
rx_pause_cnt_r <= (others => '0');
else
if(rx_pause = '1')then
rx_pause_cnt_r <= rx_pause_cnt_r +1;
cnt_r <= unsigned(rx_pause_quanta8);
if(unsigned(rx_pause_quanta8) = 0)then
pause_r <= '0';
else
pause_r <= '1';
end if;
else
if(cnt_r > 0)then
cnt_r <= cnt_r -1;
end if;
if(cnt_r = 1)then
pause_r <= '0';
end if;
end if;
end if;
end if;
end process;
end behavioral;
source/eth_flowctrl_tx.vhd
+135
View File
@@ -0,0 +1,135 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Jason M Blevins
--
-- Create Date: 01/05/2026 11:59:12 AM
-- Design Name:
-- Module Name: eth_flowctrl_tx - behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity eth_flowctrl_tx is
Port (
clk : in STD_LOGIC;
resetn : in STD_LOGIC;
prog_full_manual : in STD_LOGIC;
data_cnt : in STD_LOGIC_VECTOR(31 downto 0);
prog_full_on : in STD_LOGIC_VECTOR(31 downto 0);
prog_full_off : in STD_LOGIC_VECTOR(31 downto 0);
ctl_tx_resend_pause : out STD_LOGIC;
ctl_tx_pause_req : out STD_LOGIC_VECTOR (8 downto 0);
tx_pause_cnt : out std_logic_vector(31 downto 0)
);
end eth_flowctrl_tx;
architecture behavioral of eth_flowctrl_tx is
signal cnt : unsigned(3 downto 0);
signal cnt_r : unsigned(3 downto 0) := (others => '0');
signal tx_pause_cnt_i : unsigned(31 downto 0);
signal tx_pause_cnt_r : unsigned(31 downto 0) := (others => '0');
type state_type is (s0, s1, s2, s3);
signal state : state_type;
signal state_r : state_type := s0;
signal resend_pause : std_logic;
signal pause_req : std_logic_vector(8 downto 0);
signal resend_pause_r : std_logic := '0';
signal pause_req_r : std_logic_vector(8 downto 0) := (others => '0');
signal prog_full_r : std_logic := '0';
begin
ctl_tx_resend_pause <= resend_pause_r;
ctl_tx_pause_req <= pause_req_r;
tx_pause_cnt <= std_logic_vector(tx_pause_cnt_r);
process(clk)
begin
if(rising_edge(clk))then
if(resetn = '0')then
resend_pause_r <= '0';
pause_req_r <= (others => '0');
state_r <= s0;
cnt_r <= (others => '0');
prog_full_r <= '0';
tx_pause_cnt_r <= (others => '0');
else
resend_pause_r <= resend_pause;
pause_req_r <= pause_req;
state_r <= state;
cnt_r <= cnt;
tx_pause_cnt_r <= tx_pause_cnt_i;
if(unsigned(data_cnt) > unsigned(prog_full_on) or prog_full_manual = '1')then
prog_full_r <= '1';
elsif (unsigned(data_cnt) <= unsigned(prog_full_off) and prog_full_manual = '0')then
prog_full_r <= '0';
end if;
end if;
end if;
end process;
process(state_r, cnt_r, prog_full_r, resend_pause_r, pause_req_r, tx_pause_cnt_r)
begin
-- defaults
state <= state_r;
cnt <= cnt_r;
resend_pause <= resend_pause_r;
pause_req <= pause_req_r;
tx_pause_cnt_i <= tx_pause_cnt_r;
case state_r is
when s0 =>
if(prog_full_r = '1')then
state <= s1;
tx_pause_cnt_i <= tx_pause_cnt_r +1;
end if;
when s1 =>
pause_req <= "100000000";
cnt <= cnt_r +1;
if(cnt_r = 15)then
state <= s2;
end if;
when s2 =>
if(prog_full_r = '0')then
state <= s3;
tx_pause_cnt_i <= tx_pause_cnt_r +1;
end if;
when s3 =>
pause_req <= (others => '0');
cnt <= cnt_r +1;
if(cnt_r = 0)then
resend_pause <= '1';
else
resend_pause <= '0';
end if;
if(cnt_r = 15)then
state <= s0;
end if;
when others =>
end case;
end process;
end behavioral;
source/eth_frame_packer.vhd
+258
View File
@@ -0,0 +1,258 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/30/2025 05:40:20 PM
-- Design Name:
-- Module Name: eth_frame_packer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eth_frame_packer is
port (
clk : in std_logic;
resetn : in std_logic;
pause : in std_logic := '0';
cfg_dst_mac : in std_logic_vector(47 downto 0); -- DA
cfg_src_mac : in std_logic_vector(47 downto 0); -- SA
cfg_eth_type : in std_logic_vector(15 downto 0); -- EtherType/Length
-- AXIS payload in (512-bit, 64B beats; multiples of 64B, aligned)
s_axis_tdata : in std_logic_vector(511 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tlast : in std_logic;
-- AXIS to CMAC TX client (512-bit)
m_axis_tdata : out std_logic_vector(511 downto 0);
m_axis_tkeep : out std_logic_vector(63 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic;
m_axis_tuser : out std_logic; -- error flag to CMAC
tx_cnt : out std_logic_vector(31 downto 0);
underrun_cnt : out std_logic_vector(31 downto 0) := (others => '0')
);
end entity;
architecture rtl of eth_frame_packer is
---------------------------------------------------------------------------
-- Functions (VHDL-93 safe)
---------------------------------------------------------------------------
function mk_header(
da : std_logic_vector(47 downto 0);
sa : std_logic_vector(47 downto 0);
ety : std_logic_vector(15 downto 0)
) return std_logic_vector is
variable h : std_logic_vector(111 downto 0);
begin
-- DA [0..5]
h( 7 downto 0) := da(47 downto 40);
h( 15 downto 8) := da(39 downto 32);
h( 23 downto 16) := da(31 downto 24);
h( 31 downto 24) := da(23 downto 16);
h( 39 downto 32) := da(15 downto 8);
h( 47 downto 40) := da( 7 downto 0);
-- SA [6..11]
h( 55 downto 48) := sa(47 downto 40);
h( 63 downto 56) := sa(39 downto 32);
h( 71 downto 64) := sa(31 downto 24);
h( 79 downto 72) := sa(23 downto 16);
h( 87 downto 80) := sa(15 downto 8);
h( 95 downto 88) := sa( 7 downto 0);
-- Type/Len [12..13]
h(103 downto 96) := ety(15 downto 8);
h(111 downto 104) := ety( 7 downto 0);
return h;
end function;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
type state_type is (IDLE, RUN, FLUSH);
signal state : state_type;
signal state_r : state_type := IDLE;
signal carry_r : std_logic_vector(111 downto 0) := (others => '0');
signal carry : std_logic_vector(111 downto 0);
signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0');
signal m_tdata : std_logic_vector(511 downto 0);
signal m_tkeep_r : std_logic_vector(63 downto 0) := (others => '1');
signal m_tkeep : std_logic_vector(63 downto 0);
signal m_tlast_r : std_logic := '0';
signal m_tlast : std_logic;
signal m_tvalid_r : std_logic := '0';
signal m_tvalid : std_logic;
signal m_tuser_r : std_logic := '0';
signal m_tuser : std_logic;
signal header : std_logic_vector(111 downto 0);
signal underrun_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal tx_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
begin
header <= mk_header(cfg_dst_mac, cfg_src_mac, cfg_eth_type);
---------------------------------------------------------------------------
-- Drive Outputs
---------------------------------------------------------------------------
m_axis_tuser <= m_tuser_r;
m_axis_tdata <= m_tdata_r;
m_axis_tkeep <= m_tkeep_r;
m_axis_tlast <= m_tlast_r;
m_axis_tvalid <= m_tvalid_r;
underrun_cnt <= underrun_cnt_r;
tx_cnt <= tx_cnt_r;
---------------------------------------------------------------------------
-- Combinational next-state / next-data
---------------------------------------------------------------------------
process(state_r, carry_r, s_axis_tlast, s_axis_tvalid, m_axis_tready, m_tvalid_r,
m_tdata_r, m_tkeep_r, m_tlast_r, m_tuser_r, header, s_axis_tdata, pause)
begin
-- Defaults
state <= state_r;
carry <= carry_r;
m_tdata <= m_tdata_r;
m_tkeep <= m_tkeep_r;
m_tlast <= m_tlast_r;
m_tuser <= m_tuser_r;
m_tvalid <= m_tvalid_r;
s_axis_tready <= '0';
case state_r is
-----------------------------------------------------------------------
when IDLE =>
--s_axis_tready <= m_axis_tready or not(m_tvalid_r);
--m_tvalid <= (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0')) or (not(m_axis_tready) and m_tvalid_r);
if(m_axis_tready = '1')then
m_tvalid <= '0';
end if;
if (s_axis_tvalid = '1' and (m_axis_tready = '1' or m_tvalid_r = '0') and pause = '0') then
s_axis_tready <= '1';
-- Emit first beat = [14B header] ++ [first 50B payload]
m_tdata <= s_axis_tdata(399 downto 0) & header;
m_tkeep <= (others => '1');
m_tvalid <= '1';
m_tuser <= '0';
m_tlast <= '0';
-- Next carry = bytes 50..63
carry <= s_axis_tdata(511 downto 400);
if s_axis_tlast = '1' then
state <= FLUSH;
else
state <= RUN;
end if;
end if;
-----------------------------------------------------------------------
when RUN =>
s_axis_tready <= m_axis_tready;
if(s_axis_tvalid = '0')then
m_tuser <= '1'; -- s_axis_tvalid must be '1' or else this is an error condition, tx data underrun.
end if;
if (m_axis_tready = '1') then
-- Steady-state emit = [prev carry 14B] ++ [new payload 0..49]
m_tdata <= s_axis_tdata(399 downto 0) & carry_r;
--m_tkeep <= (others => '1');
--m_tvalid <= '1';
--m_tlast <= '0';
-- Next carry = bytes 50..63
carry <= s_axis_tdata(511 downto 400);
if s_axis_tlast = '1' then
state <= FLUSH;
else
state <= RUN;
end if;
end if;
-----------------------------------------------------------------------
when FLUSH =>
--s_axis_tready <= '0';
-- if(s_axis_tvalid = '0')then
-- m_tuser <= '1';
-- end if;
if (m_axis_tready = '1') then
-- Emit the final 14B tail
m_tdata <= std_logic_vector(to_unsigned(0, 400)) & carry_r;
m_tkeep <= x"0000000000003FFF";
m_tlast <= '1';
--m_tvalid <= '1';
state <= IDLE;
end if;
--when others =>
end case;
end process;
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
if resetn = '0' then
state_r <= IDLE;
m_tvalid_r <= '0';
underrun_cnt_r <= (others => '0');
tx_cnt_r <= (others => '0');
else
state_r <= state;
m_tvalid_r <= m_tvalid;
if(m_tlast_r = '1' and m_tvalid_r = '1' and m_tuser_r = '1' and m_axis_tready = '1')then
underrun_cnt_r <= std_logic_vector(unsigned(underrun_cnt_r) +1);
end if;
if(m_tlast_r = '1' and m_tvalid_r = '1' and m_axis_tready = '1')then
tx_cnt_r <= std_logic_vector(unsigned(tx_cnt_r) +1);
end if;
end if;
carry_r <= carry;
m_tdata_r <= m_tdata;
m_tkeep_r <= m_tkeep;
m_tlast_r <= m_tlast;
m_tuser_r <= m_tuser;
end if;
end process;
end architecture;
source/eth_frame_unpacker.vhd
+145
View File
@@ -0,0 +1,145 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/30/2025 05:47:45 PM
-- Design Name:
-- Module Name: eth_frame_unpacker - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity eth_frame_unpacker is
port (
clk : in std_logic;
resetn : in std_logic; -- active-low synchronous reset
s_axis_tdata : in std_logic_vector(511 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tlast : in std_logic;
s_axis_tkeep : in std_logic_vector(63 downto 0);
s_axis_tuser : in std_logic; -- frame error indicator (qualified by s_axis_tvalid and s_axis_tlast)
m_axis_tdata : out std_logic_vector(511 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tlast : out std_logic;
m_axis_tuser : out std_logic; -- frame error indicator (qualified by m_axis_tvalid and m_axis_tlast)
rx_frame_err_cnt : out std_logic_vector(31 downto 0);
rx_frame_cnt : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of eth_frame_unpacker is
type state_type is (IDLE, RUN);
signal state_r : state_type := IDLE;
signal state : state_type;
signal carry : std_logic_vector(399 downto 0);
signal carry_r : std_logic_vector(399 downto 0) := (others => '0');
signal frame_err_cnt_i : std_logic_vector(31 downto 0);
signal frame_err_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal frame_cnt_i : std_logic_vector(31 downto 0);
signal frame_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal m_tvalid : std_logic;
signal m_tvalid_r : std_logic := '0';
signal m_tdata : std_logic_vector(511 downto 0);
signal m_tdata_r : std_logic_vector(511 downto 0) := (others => '0');
signal m_tuser : std_logic;
signal m_tuser_r : std_logic := '0';
signal m_tlast : std_logic;
signal m_tlast_r : std_logic := '0';
begin
-- Drive outputs
m_axis_tuser <= m_tuser_r;
m_axis_tdata <= m_tdata_r;
m_axis_tlast <= m_tlast_r;
m_axis_tvalid <= m_tvalid_r;
rx_frame_err_cnt <= frame_err_cnt_r;
rx_frame_cnt <= frame_cnt_r;
-----------------------------------------------------------------------------
-- Combinational next-state / next-data
-----------------------------------------------------------------------------
process(state_r, carry_r, m_tdata_r, m_tuser_r, m_tlast_r, frame_err_cnt_r,
s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser, frame_cnt_r)
begin
-- Defaults
state <= state_r;
carry <= carry_r;
frame_err_cnt_i <= frame_err_cnt_r;
frame_cnt_i <= frame_cnt_r;
m_tvalid <= '0';
m_tdata <= m_tdata_r;
m_tuser <= m_tuser_r;
m_tlast <= m_tlast_r;
case state_r is
-------------------------------------------------------------------------
when IDLE =>
if s_axis_tvalid = '1' then
-- cache high 50B; no output yet (need second beat to form first 64B payload)
carry(399 downto 0) <= s_axis_tdata(511 downto 112);
state <= RUN;
end if;
-------------------------------------------------------------------------
when RUN =>
if s_axis_tvalid = '1' then
carry(399 downto 0) <= s_axis_tdata(511 downto 112);
m_tdata <= s_axis_tdata(111 downto 0) & carry_r;
m_tvalid <= '1';
m_tuser <= s_axis_tuser;
m_tlast <= s_axis_tlast;
if(s_axis_tlast = '1')then
state <= IDLE;
frame_cnt_i <= std_logic_vector(unsigned(frame_cnt_r) +1);
end if;
if(s_axis_tlast = '1' and s_axis_tuser = '1')then
frame_err_cnt_i <= std_logic_vector(unsigned(frame_err_cnt_r) +1);
end if;
end if;
-------------------------------------------------------------------------
end case;
end process;
-----------------------------------------------------------------------------
-- Regs
-----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
if resetn = '0' then
state_r <= IDLE;
frame_err_cnt_r <= (others => '0');
frame_cnt_r <= (others => '0');
m_tvalid_r <= '0';
else
state_r <= state;
frame_err_cnt_r <= frame_err_cnt_i;
frame_cnt_r <= frame_cnt_i;
m_tvalid_r <= m_tvalid;
end if;
carry_r <= carry;
m_tdata_r <= m_tdata;
m_tuser_r <= m_tuser;
m_tlast_r <= m_tlast;
end if;
end process;
end architecture;
source/system_top.v
+320 -128
View File
@@ -37,8 +37,8 @@
module system_top #(
parameter FPGA_REVISION_DATE = 32'h05282026,
parameter MINOR_REV = 8'h04,
parameter FPGA_REVISION_DATE = 32'h07162026,
parameter MINOR_REV = 8'h01,
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
@@ -69,6 +69,35 @@ module system_top #(
output QSFP1_TX3_P,
output QSFP1_TX4_N,
output QSFP1_TX4_P,
//
input QSFP2_INTL_LS,
input QSFP2_MODPRSL_LS,
output QSFP2_RESETL_LS,
input QSFP2_SI570_CLOCK_N,//CLK3_N
input QSFP2_SI570_CLOCK_P,
//
input QSFP3_INTL_LS,
input QSFP3_MODPRSL_LS,
output QSFP3_RESETL_LS,
input QSFP3_RX1_N,
input QSFP3_RX1_P,
input QSFP3_RX2_N,
input QSFP3_RX2_P,
input QSFP3_RX3_N,
input QSFP3_RX3_P,
input QSFP3_RX4_N,
input QSFP3_RX4_P,
input QSFP3_SI570_CLOCK_N,//CLK1_N
input QSFP3_SI570_CLOCK_P,
output QSFP3_TX1_N,
output QSFP3_TX1_P,
output QSFP3_TX2_N,
output QSFP3_TX2_P,
output QSFP3_TX3_N,
output QSFP3_TX3_P,
output QSFP3_TX4_N,
output QSFP3_TX4_P,
//
input QSFP4_INTL_LS,
input QSFP4_MODPRSL_LS,
output QSFP4_RESETL_LS,
@@ -90,14 +119,7 @@ module system_top #(
output QSFP4_TX3_P,
output QSFP4_TX4_N,
output QSFP4_TX4_P,
input QSFP2_SI570_CLOCK_N,//CLK3_N
input QSFP2_SI570_CLOCK_P,
input QSFP3_SI570_CLOCK_N,//CLK1_N
input QSFP3_SI570_CLOCK_P,
//
inout pll_scl,
inout pll_sda,
@@ -220,13 +242,13 @@ module system_top #(
wire qsfp1_capture_tvalid_240b;
wire [31:0] qsfp1_capture_tvalid_240b_cnt;
wire [31:0] qsfp1_tx_fifo_128_aempty_cnt;
wire [31:0] qsfp1_fifo_128_aempty_cnt;
wire [127:0] tx_tdata_128b;
wire tx_tvalid_128b;
wire tx_tready_128b;
wire [127:0] qsfp1_tdata_128b;
wire qsfp1_tvalid_128b;
wire qsfp1_tready_128b;
wire [31:0] qsfp1_tx_fifo_tvalid_128b_cnt;
wire [31:0] qsfp1_fifo_tvalid_128b_cnt;
wire qsfp1_capture_rx_data_ready;
wire [31:0] qsfp1_capture_rx_data_ready_cnt;
@@ -253,38 +275,7 @@ module system_top #(
wire [31:0] slv_reg9;
wire [31:0] slv_reg10;
wire [31:0] slv_reg21;
wire [31:0] slv_reg22;
wire [31:0] slv_reg23;
wire [31:0] slv_reg24;
wire [31:0] slv_reg25;
wire [31:0] slv_reg26;
wire [31:0] slv_reg27;
wire [31:0] slv_reg28;
wire [31:0] slv_reg29;
wire [31:0] slv_reg30;
wire [31:0] slv_reg31;
wire [31:0] slv_reg32;
wire [31:0] slv_reg33;
wire [31:0] slv_reg34;
wire [31:0] slv_reg35;
wire [31:0] slv_reg36;
wire [31:0] slv_reg37;
wire [31:0] slv_reg38;
wire [31:0] slv_reg39;
wire [31:0] slv_reg40;
wire [31:0] slv_reg41;
wire [31:0] slv_reg42;
wire [31:0] slv_reg43;
wire [31:0] slv_reg44;
wire [31:0] slv_reg45;
wire [31:0] slv_reg46;
wire [31:0] slv_reg47;
wire [31:0] slv_reg48;
wire [1:0] dac_src_data_sel;
wire [2:0] dac_src_data_sel;
wire chan1to4_mode_sel;
wire qsfp4_playback_path_data_enable_n;
@@ -292,9 +283,6 @@ module system_top #(
wire qsfp2_clk;
wire qsfp2_clk_bufg;
wire qsfp3_clk;
wire qsfp3_clk_bufg;
wire clk_100;
wire clk_100_aresetn;
wire [31:0] M11_AXI_0_araddr;
@@ -337,6 +325,26 @@ module system_top #(
wire [3:0] M12_AXI_0_wstrb;
wire M12_AXI_0_wvalid;
wire [31:0] M13_AXI_0_araddr;
wire [2:0] M13_AXI_0_arprot;
wire M13_AXI_0_arready;
wire M13_AXI_0_arvalid;
wire [31:0] M13_AXI_0_awaddr;
wire [2:0] M13_AXI_0_awprot;
wire M13_AXI_0_awready;
wire M13_AXI_0_awvalid;
wire M13_AXI_0_bready;
wire [1:0] M13_AXI_0_bresp;
wire M13_AXI_0_bvalid;
wire [31:0] M13_AXI_0_rdata;
wire M13_AXI_0_rready;
wire [1:0] M13_AXI_0_rresp;
wire M13_AXI_0_rvalid;
wire [31:0] M13_AXI_0_wdata;
wire M13_AXI_0_wready;
wire [3:0] M13_AXI_0_wstrb;
wire M13_AXI_0_wvalid;
wire sda_i;
wire sda_o;
wire sda_t;
@@ -357,6 +365,10 @@ module system_top #(
wire m1_dds_pulse_tvalid_128b;
wire m1_dds_pulse_tready_128b;
wire [127:0] m1_dds_pulse_fifo_tdata_128b;
wire m1_dds_pulse_fifo_tvalid_128b;
wire m1_dds_pulse_fifo_tready_128b;
wire [127:0] fiber_tx_tdata_128b;
wire fiber_tx_tvalid_128b;
wire fiber_tx_tready_128b;
@@ -369,6 +381,47 @@ module system_top #(
wire qsfp1_capture_en_n;
wire qsfp1_capture_rst;
wire [3:0] cmac_gt_0_grx_n;
wire [3:0] cmac_gt_0_grx_p;
wire [3:0] cmac_gt_0_gtx_n;
wire [3:0] cmac_gt_0_gtx_p;
wire cmac_refclk_0_clk_n;
wire cmac_refclk_0_clk_p;
wire cmac_tx_intfc_en;
wire cmac_rx_intfc_en;
////
wire [511:0] cmac_0_tx_tdata_512b;
wire cmac_0_tx_tvalid_512b;
wire cmac_0_tx_tvalid_512b_en;
wire cmac_0_tx_tready_512b;
wire cmac_0_tx_tready_512b_en;
reg [31:0] cmac_0_tx_tvalid_512b_cnt_r = 32'h0;
wire [511:0] cmac_0_rx_tdata_512b;
wire cmac_0_rx_tvalid_512b;
wire cmac_0_rx_tvalid_512b_en;
wire cmac_0_rx_tready_512b;
wire cmac_0_rx_tready_512b_en;
reg [31:0] cmac_0_rx_tvalid_512b_cnt_r = 32'h0;
wire [127:0] cmac_0_rx_tdata_128b;
wire cmac_0_rx_tvalid_128b;
wire cmac_0_rx_tready_128b;
wire [127:0] dds2cmac_fifo_tdata_128b;
wire dds2cmac_fifo_tvalid_128b;
wire dds2cmac_fifo_tready_128b;
wire dds_out_dest_sel;
wire cmac_tx_src_data_sel;
wire [511:0] adc_tdata_512b;
wire adc_tvalid_512b;
wire adc_tready_512b;
////////////////////////////////////////////////////////////////
// instantiations
@@ -472,27 +525,6 @@ module system_top #(
.DIV (3'b000),
.O (qsfp2_clk_bufg)
);
//////////
IBUFDS_GTE4 i_ibufds_qsfp3 (
.I (QSFP3_SI570_CLOCK_P),
.IB (QSFP3_SI570_CLOCK_N),
.CEB (1'b0),
.O (),
.ODIV2 (qsfp3_clk)
);
BUFG_GT i_bufgt_qsfp3 (
.I (qsfp3_clk),
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'b000),
.O (qsfp3_clk_bufg)
);
// assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
@@ -736,6 +768,26 @@ module system_top #(
.M12_AXI_0_wstrb (M12_AXI_0_wstrb),
.M12_AXI_0_wvalid (M12_AXI_0_wvalid),
.M13_AXI_0_araddr (M13_AXI_0_araddr),
.M13_AXI_0_arprot (M13_AXI_0_arprot),
.M13_AXI_0_arready (M13_AXI_0_arready),
.M13_AXI_0_arvalid (M13_AXI_0_arvalid),
.M13_AXI_0_awaddr (M13_AXI_0_awaddr),
.M13_AXI_0_awprot (M13_AXI_0_awprot),
.M13_AXI_0_awready (M13_AXI_0_awready),
.M13_AXI_0_awvalid (M13_AXI_0_awvalid),
.M13_AXI_0_bready (M13_AXI_0_bready),
.M13_AXI_0_bresp (M13_AXI_0_bresp),
.M13_AXI_0_bvalid (M13_AXI_0_bvalid),
.M13_AXI_0_rdata (M13_AXI_0_rdata),
.M13_AXI_0_rready (M13_AXI_0_rready),
.M13_AXI_0_rresp (M13_AXI_0_rresp),
.M13_AXI_0_rvalid (M13_AXI_0_rvalid),
.M13_AXI_0_wdata (M13_AXI_0_wdata),
.M13_AXI_0_wready (M13_AXI_0_wready),
.M13_AXI_0_wstrb (M13_AXI_0_wstrb),
.M13_AXI_0_wvalid (M13_AXI_0_wvalid),
.Res_0 (), //mxfe_rx_data_offload_s_axis_tready from Rx DMA engine
.pl_clk3_0 (pl_clk3_0),
@@ -781,7 +833,6 @@ module system_top #(
// .sysref_in (sysref),
.ref_clk_div2_in (ref_clk_div2_bufg),
.qsfp2_clk_in (qsfp2_clk_bufg),
.qsfp3_clk_in (qsfp3_clk_bufg),
.pl_clk3_0 (pl_clk3_0),
.QSFP1_INTL_LS (QSFP1_INTL_LS),
@@ -805,6 +856,15 @@ module system_top #(
.QSFP1_TX3_P (QSFP1_TX3_P),
.QSFP1_TX4_N (QSFP1_TX4_N),
.QSFP1_TX4_P (QSFP1_TX4_P),
///////////
.QSFP2_RESETL_LS (QSFP2_RESETL_LS),
.QSFP2_MODPRSL_LS (QSFP2_MODPRSL_LS),
.QSFP2_INTL_LS (QSFP2_INTL_LS),
///////////
.QSFP3_RESETL_LS (QSFP3_RESETL_LS),
.QSFP3_MODPRSL_LS (QSFP3_MODPRSL_LS),
.QSFP3_INTL_LS (QSFP3_INTL_LS),
///////////
.QSFP4_INTL_LS (QSFP4_INTL_LS),
.QSFP4_MODPRSL_LS (QSFP4_MODPRSL_LS),
.QSFP4_RESETL_LS (QSFP4_RESETL_LS),
@@ -842,9 +902,9 @@ module system_top #(
.qsfp1_capture_tvalid_240b_cnt_in (qsfp1_capture_tvalid_240b_cnt),
.qsfp1_capture_overflow_240b_cnt_in (qsfp1_capture_overflow_240b_cnt),
.qsfp1_capture_tvalid_512b_cnt_in (qsfp1_capture_tvalid_512b_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_tx_fifo_128_aempty_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_in (qsfp1_fifo_128_aempty_cnt),
.qsfp1_capture_rx_data_ready_cnt_in (qsfp1_capture_rx_data_ready_cnt),
.qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_tx_fifo_tvalid_128b_cnt),
.qsfp1_tx_fifo_tvalid_128b_cnt_in (qsfp1_fifo_tvalid_128b_cnt),
.mem_xfer_tx_upload_tvalid_128b_cnt_in (mem_xfer_tx_upload_tvalid_128b_cnt_r),
.dac_tx_tvalid_128b_cnt_in (dac_tx_tvalid_128b_cnt_r),
@@ -853,44 +913,17 @@ module system_top #(
.qsfp4_playback_tvalid_128b_cnt_in (qsfp4_playback_tvalid_128b_cnt),
.qsfp4_playback_tvalid_240b_cnt_in (qsfp4_playback_tvalid_240b_cnt),
.fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r),
.fiber_tx_tvalid_128b_cnt_in (fiber_tx_tvalid_128b_cnt_r),
.cmac_0_tx_tvalid_512b_cnt_in (cmac_0_tx_tvalid_512b_cnt_r),
.cmac_0_rx_tvalid_512b_cnt_in (cmac_0_rx_tvalid_512b_cnt_r),
.cnt_reset_out (cnt_reset),
.slv_reg9_out (slv_reg9),
.slv_reg10_out (slv_reg10),
.slv_reg21_out (slv_reg21),
.slv_reg22_out (slv_reg22),
.slv_reg23_out (slv_reg23),
.slv_reg24_out (slv_reg24),
.slv_reg25_out (slv_reg25),
.slv_reg26_out (slv_reg26),
.slv_reg27_out (slv_reg27),
.slv_reg28_out (slv_reg28),
.slv_reg29_out (slv_reg29),
.slv_reg30_out (slv_reg30),
.slv_reg31_out (slv_reg31),
.slv_reg32_out (slv_reg32),
.slv_reg33_out (slv_reg33),
.slv_reg34_out (slv_reg34),
.slv_reg35_out (slv_reg35),
.slv_reg36_out (slv_reg36),
.slv_reg37_out (slv_reg37),
.slv_reg38_out (slv_reg38),
.slv_reg39_out (slv_reg39),
.slv_reg40_out (slv_reg40),
.slv_reg41_out (slv_reg41),
.slv_reg42_out (slv_reg42),
.slv_reg43_out (slv_reg43),
.slv_reg44_out (slv_reg44),
.slv_reg45_out (slv_reg45),
.slv_reg46_out (slv_reg46),
.slv_reg47_out (slv_reg47),
.slv_reg48_out (slv_reg48),
.sys_cpu_clk_in (clk_100),
.s00_axi_aresetn (clk_100_aresetn),
.s00_axi_awaddr (M11_AXI_0_awaddr[7:0]),
@@ -918,12 +951,19 @@ module system_top #(
//assign = slv_reg10[3:1];
assign qsfp1_capture_rst = slv_reg10[4];
//assign = slv_reg10[7:5];
assign dac_src_data_sel = slv_reg10[9:8];
//assign = slv_reg10[11:10];
assign dac_src_data_sel = slv_reg10[10:8];
//assign = slv_reg10[11];
assign chan1to4_mode_sel = slv_reg10[12];
//assign = slv_reg10[14:13];
assign qsfp1_capture_en_n = slv_reg10[15];
//assign = slv_reg10[30:16];
//assign = slv_reg10[18:16];
assign cmac_tx_src_data_sel = slv_reg10[19];
//assign = slv_reg10[23:20];
assign dds_out_dest_sel = slv_reg10[24];
//assign = slv_reg10[27:25];
assign cmac_tx_intfc_en = slv_reg10[28];
assign cmac_rx_intfc_en = slv_reg10[29];
//assign = slv_reg10[30];
assign qsfp4_playback_path_data_enable_n = slv_reg10[31];
///////////////////////////////
@@ -942,11 +982,11 @@ module system_top #(
.tx_device_clk_in (tx_device_clk_1),
.tx_device_clk_aresetn_in (tx_device_clk_aresetn),
.tx_fifo_tdata_128b_out (tx_tdata_128b), // out
.tx_fifo_tvalid_128b_out (tx_tvalid_128b), // out
.tx_fifo_tready_128b_in (tx_tready_128b), // in
.qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_tx_fifo_tvalid_128b_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_tx_fifo_128_aempty_cnt),
.tx_fifo_tdata_128b_out (qsfp1_tdata_128b), // out
.tx_fifo_tvalid_128b_out (qsfp1_tvalid_128b), // out
.tx_fifo_tready_128b_in (qsfp1_tready_128b), // in
.qsfp1_tx_fifo_tvalid_128b_cnt_out (qsfp1_fifo_tvalid_128b_cnt),
.qsfp1_tx_fifo_128_aempty_cnt_out (qsfp1_fifo_128_aempty_cnt),
.qsfp1_capture_en_n_in (qsfp1_capture_en_n),
.qsfp1_capture_rst_in (qsfp1_capture_rst),
@@ -957,17 +997,15 @@ module system_top #(
//// to DAC - data source from DMA Tx axis data, QSFP1 and ADC_INTFC
/////////////////////////////////////////////
axis_mux_128b i_dac_axis_mux_128b (
.aclk (tx_device_clk_1), // input
.aresetn (tx_device_clk_aresetn), // input
.aselect (dac_src_data_sel), // input
.s0_axis_tdata (mem_xfer_tx_upload_tdata_128b), // input
.s0_axis_tvalid (mem_xfer_tx_upload_tvalid_128b), // input
.s0_axis_tready (mem_xfer_tx_upload_tready_128b), // output
.s1_axis_tdata (tx_tdata_128b), // input
.s1_axis_tvalid (tx_tvalid_128b), // input
.s1_axis_tready (tx_tready_128b), // output
.s1_axis_tdata (qsfp1_tdata_128b), // input
.s1_axis_tvalid (qsfp1_tvalid_128b), // input
.s1_axis_tready (qsfp1_tready_128b), // output
.s2_axis_tdata (adc_loopback_tdata_128b_mux), // input
.s2_axis_tvalid (adc_loopback_tvalid_128b), // input
@@ -977,6 +1015,10 @@ module system_top #(
.s3_axis_tvalid (m0_dds_pulse_tvalid_128b), // input
.s3_axis_tready (m0_dds_pulse_tready_128b), // output
.s4_axis_tdata (cmac_0_rx_tdata_128b), // input
.s4_axis_tvalid (cmac_0_rx_tvalid_128b), // input
.s4_axis_tready (cmac_0_rx_tready_128b), // output
.m_axis_tdata (dac_tx_tdata_128b), // output
.m_axis_tvalid (dac_tx_tvalid_128b), // output
.m_axis_tready (dac_tx_tready_128b) // input
@@ -1004,14 +1046,28 @@ module system_top #(
.s_axis_tready (m1_dds_pulse_tready_128b), // out
.m_axis_aclk (rx_device_clk_1), // in
.m_axis_tdata (dds2fiber_fifo_tdata_128b), // out
.m_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out
.m_axis_tready (dds2fiber_fifo_tready_128b) // in
.m_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // out
.m_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // out
.m_axis_tready (m1_dds_pulse_fifo_tready_128b) // in
);
axis_demux_128b i_axis_demux_128b (
.aselect (dds_out_dest_sel), // in
.s_axis_tdata (m1_dds_pulse_fifo_tdata_128b), // in
.s_axis_tvalid (m1_dds_pulse_fifo_tvalid_128b), // in
.s_axis_tready (m1_dds_pulse_fifo_tready_128b), // out
.m0_axis_tdata (dds2fiber_fifo_tdata_128b), // out
.m0_axis_tvalid (dds2fiber_fifo_tvalid_128b), // out
.m0_axis_tready (dds2fiber_fifo_tready_128b), // in
.m1_axis_tdata (dds2cmac_fifo_tdata_128b), // out
.m1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // out
.m1_axis_tready (dds2cmac_fifo_tready_128b) // in
);
axis_mux_s2_128b i_axis_mux_s2_128b (
.aclk (rx_device_clk_1), // input
.aresetn (rx_device_clk_aresetn), // input
.aselect (fiber_tx_src_data_sel), // input
.s0_axis_tdata (adc_rx_tdata_128b), // input
@@ -1151,6 +1207,145 @@ module system_top #(
.s00_axi_rready (M12_AXI_0_rready)
);
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
assign cmac_refclk_0_clk_p = QSFP3_SI570_CLOCK_P;
assign cmac_refclk_0_clk_n = QSFP3_SI570_CLOCK_N;
assign cmac_gt_0_grx_p[0] = QSFP3_RX1_P;
assign cmac_gt_0_grx_n[0] = QSFP3_RX1_N;
assign cmac_gt_0_grx_p[1] = QSFP3_RX2_P;
assign cmac_gt_0_grx_n[1] = QSFP3_RX2_N;
assign cmac_gt_0_grx_p[2] = QSFP3_RX3_P;
assign cmac_gt_0_grx_n[2] = QSFP3_RX3_N;
assign cmac_gt_0_grx_p[3] = QSFP3_RX4_P;
assign cmac_gt_0_grx_n[3] = QSFP3_RX4_N;
assign QSFP3_TX1_P = cmac_gt_0_gtx_p[0];
assign QSFP3_TX1_N = cmac_gt_0_gtx_n[0];
assign QSFP3_TX2_P = cmac_gt_0_gtx_p[1];
assign QSFP3_TX2_N = cmac_gt_0_gtx_n[1];
assign QSFP3_TX3_P = cmac_gt_0_gtx_p[2];
assign QSFP3_TX3_N = cmac_gt_0_gtx_n[2];
assign QSFP3_TX4_P = cmac_gt_0_gtx_p[3];
assign QSFP3_TX4_N = cmac_gt_0_gtx_n[3];
raw_eth_wrapper i_raw_eth_cmac_0 (
.clk_100_0 (clk_100),
.clk_100_reset_0 (clk_100_areset),
.cmac_gt_0_grx_n (cmac_gt_0_grx_n), //in
.cmac_gt_0_grx_p (cmac_gt_0_grx_p), //in
.cmac_gt_0_gtx_n (cmac_gt_0_gtx_n), //out
.cmac_gt_0_gtx_p (cmac_gt_0_gtx_p), //out
.cmac_refclk_0_clk_n (cmac_refclk_0_clk_n),
.cmac_refclk_0_clk_p (cmac_refclk_0_clk_p),
.m_axis_aclk (tx_device_clk_1),
.m_axis_aresetn (tx_device_clk_aresetn),
.m_axis_tdata (cmac_0_rx_tdata_512b), // out
.m_axis_tvalid (cmac_0_rx_tvalid_512b), // out
.m_axis_tready (cmac_0_rx_tready_512b_en), // in
.axil_clk_0 (clk_100),
.axil_resetn_0 (clk_100_aresetn),
.s_axil_0_awaddr (M13_AXI_0_awaddr),
.s_axil_0_awprot (M13_AXI_0_awprot),
.s_axil_0_awvalid (M13_AXI_0_awvalid),
.s_axil_0_awready (M13_AXI_0_awready),
.s_axil_0_wdata (M13_AXI_0_wdata),
.s_axil_0_wstrb (M13_AXI_0_wstrb),
.s_axil_0_wvalid (M13_AXI_0_wvalid),
.s_axil_0_wready (M13_AXI_0_wready),
.s_axil_0_bresp (M13_AXI_0_bresp),
.s_axil_0_bvalid (M13_AXI_0_bvalid),
.s_axil_0_bready (M13_AXI_0_bready),
.s_axil_0_araddr (M13_AXI_0_araddr),
.s_axil_0_arprot (M13_AXI_0_arprot),
.s_axil_0_arvalid (M13_AXI_0_arvalid),
.s_axil_0_arready (M13_AXI_0_arready),
.s_axil_0_rdata (M13_AXI_0_rdata),
.s_axil_0_rresp (M13_AXI_0_rresp),
.s_axil_0_rvalid (M13_AXI_0_rvalid),
.s_axil_0_rready (M13_AXI_0_rready),
.s_axis_clk (rx_device_clk_1),
.s_axis_aresetn (rx_device_clk_aresetn),
.s_axis_tdata (cmac_0_tx_tdata_512b), // in
.s_axis_tvalid (cmac_0_tx_tvalid_512b_en), // in
.s_axis_tready (cmac_0_tx_tready_512b) // out
);
axis_dwidth_converter_128b_to_512b i_axis_dwidth_converter_128b_to_512b (
.aclk (rx_device_clk_1), // in
.aresetn (rx_device_clk_aresetn), // in
.s_axis_tdata (adc_rx_tdata_128b), // in
.s_axis_tvalid (adc_rx_tvalid_128b), // in
.s_axis_tready ( ), // out
.m_axis_tdata (adc_tdata_512b), // out
.m_axis_tvalid (adc_tvalid_512b), // out
.m_axis_tready (adc_tready_512b) // in
);
axis_mux_512b i_axis_mux_512b (
.aselect (cmac_tx_src_data_sel), // input
.s0_axis_tdata (adc_tdata_512b), // input
.s0_axis_tvalid (adc_tvalid_512b), // input
.s0_axis_tready (adc_tready_512b), // output
.s1_axis_tdata (dds2cmac_fifo_tdata_128b), // input
.s1_axis_tvalid (dds2cmac_fifo_tvalid_128b), // input
.s1_axis_tready (dds2cmac_fifo_tready_128b), // output
.m_axis_tdata (cmac_0_tx_tdata_512b), // output
.m_axis_tvalid (cmac_0_tx_tvalid_512b), // output
.m_axis_tready (cmac_0_tx_tready_512b_en) // input
);
assign cmac_0_tx_tvalid_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tvalid_512b : 1'b0;
assign cmac_0_tx_tready_512b_en = (cmac_tx_intfc_en == 1'b1) ? cmac_0_tx_tready_512b : 1'b0;
always @(posedge rx_device_clk_1)
begin
if (rx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
cmac_0_tx_tvalid_512b_cnt_r <= 32'h0;
else if (cmac_0_tx_tvalid_512b_en == 1'b1 && cmac_0_tx_tready_512b_en == 1'b1)
cmac_0_tx_tvalid_512b_cnt_r <= cmac_0_tx_tvalid_512b_cnt_r + 1;
end
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
assign cmac_0_rx_tvalid_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tvalid_512b : 1'b0;
assign cmac_0_rx_tready_512b_en = (cmac_rx_intfc_en == 1'b1) ? cmac_0_rx_tready_512b : 1'b0;
axis_dwidth_converter_512b_to_128b i_axis_dwidth_converter_512b_to_128b_cmac_0 (
.aclk (tx_device_clk_1), // in
.aresetn (tx_device_clk_aresetn), // in
.s_axis_tdata (cmac_0_rx_tdata_512b), // in
.s_axis_tvalid (cmac_0_rx_tvalid_512b_en), // in
.s_axis_tready (cmac_0_rx_tready_512b), // out
.m_axis_tdata (cmac_0_rx_tdata_128b), // out
.m_axis_tvalid (cmac_0_rx_tvalid_128b), // out
.m_axis_tready (cmac_0_rx_tready_128b) // in
);
always @(posedge tx_device_clk_1)
begin
if (tx_device_clk_aresetn == 1'b0 || cnt_reset == 1'b1)
cmac_0_rx_tvalid_512b_cnt_r <= 32'h0;
else if (cmac_0_rx_tvalid_512b_en == 1'b1 && cmac_0_rx_tready_512b_en == 1'b1)
cmac_0_rx_tvalid_512b_cnt_r <= cmac_0_rx_tvalid_512b_cnt_r + 1;
end
//////////////////////////
si5332_wrapper i_si5332_wrapper (
@@ -1163,10 +1358,7 @@ module system_top #(
.scl_in (scl_i),
.scl_out (scl_o),
.scl_t_out (scl_t),
.qsfp2_clk_in (qsfp2_clk_bufg),
.qsfp3_clk_in (qsfp3_clk_bufg)
.scl_t_out (scl_t)
);
IOBUF i_scl_iobuf (