Erisys/alinx_z19_ad9081
6
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

added CMAC interface out of QSFP3

Browse Source
This commit is contained in:
nsantana
2026-07-17 15:55:55 -04:00
parent 69be245f2a
commit 3f25b73be7
20 changed files with 2869 additions and 524 deletions
Download Patch File Download Diff File Expand all files Collapse all files
ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0.vhd
+70 -88
View File
@@ -35,7 +35,6 @@ entity qsfp_intfc_v1_0 is
-- sysref_in : in std_logic;
ref_clk_div2_in : in std_logic;
qsfp2_clk_in : in std_logic;
qsfp3_clk_in : in std_logic;
pl_clk3_0 : in std_logic;
QSFP1_SI570_CLOCK_P : in std_logic;
@@ -63,6 +62,14 @@ entity qsfp_intfc_v1_0 is
QSFP1_RESETL_LS : out std_logic;
QSFP1_MODPRSL_LS : in std_logic;
QSFP1_INTL_LS : in std_logic;
-----------------
QSFP2_RESETL_LS : out std_logic;
QSFP2_MODPRSL_LS : in std_logic;
QSFP2_INTL_LS : in std_logic;
-----------------
QSFP3_RESETL_LS : out std_logic;
QSFP3_MODPRSL_LS : in std_logic;
QSFP3_INTL_LS : in std_logic;
-----------------
QSFP4_SI570_CLOCK_P : in std_logic;
QSFP4_SI570_CLOCK_N : in std_logic;
@@ -107,7 +114,7 @@ entity qsfp_intfc_v1_0 is
qsfp1_capture_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_tx_fifo_128_aempty_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_capture_rx_data_ready_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
mem_xfer_tx_upload_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
dac_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
@@ -117,42 +124,13 @@ entity qsfp_intfc_v1_0 is
qsfp4_playback_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
fiber_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
cmac_0_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
cmac_0_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
cnt_reset_out : out std_logic;
slv_reg9_out : out std_logic_vector(31 downto 0);
slv_reg10_out : out std_logic_vector(31 downto 0);
slv_reg21_out : out std_logic_vector(31 downto 0);
slv_reg22_out : out std_logic_vector(31 downto 0);
slv_reg23_out : out std_logic_vector(31 downto 0);
slv_reg24_out : out std_logic_vector(31 downto 0);
slv_reg25_out : out std_logic_vector(31 downto 0);
slv_reg26_out : out std_logic_vector(31 downto 0);
slv_reg27_out : out std_logic_vector(31 downto 0);
slv_reg28_out : out std_logic_vector(31 downto 0);
slv_reg29_out : out std_logic_vector(31 downto 0);
slv_reg30_out : out std_logic_vector(31 downto 0);
slv_reg31_out : out std_logic_vector(31 downto 0);
slv_reg32_out : out std_logic_vector(31 downto 0);
slv_reg33_out : out std_logic_vector(31 downto 0);
slv_reg34_out : out std_logic_vector(31 downto 0);
slv_reg35_out : out std_logic_vector(31 downto 0);
slv_reg36_out : out std_logic_vector(31 downto 0);
slv_reg37_out : out std_logic_vector(31 downto 0);
slv_reg38_out : out std_logic_vector(31 downto 0);
slv_reg39_out : out std_logic_vector(31 downto 0);
slv_reg40_out : out std_logic_vector(31 downto 0);
slv_reg41_out : out std_logic_vector(31 downto 0);
slv_reg42_out : out std_logic_vector(31 downto 0);
slv_reg43_out : out std_logic_vector(31 downto 0);
slv_reg44_out : out std_logic_vector(31 downto 0);
slv_reg45_out : out std_logic_vector(31 downto 0);
slv_reg46_out : out std_logic_vector(31 downto 0);
slv_reg47_out : out std_logic_vector(31 downto 0);
slv_reg48_out : out std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
@@ -226,6 +204,16 @@ architecture arch_imp of qsfp_intfc_v1_0 is
signal qsfp1_m_axis_tdata : std_logic_vector(239 downto 0);
signal qsfp1_m_axis_tvalid : std_logic;
--
signal qsfp2_reset_n_i : std_logic;
signal qsfp2_modprsl : std_logic;
signal qsfp2_intl : std_logic;
signal qsfp2_reset_n : std_logic;
--
signal qsfp3_reset_n_i : std_logic;
signal qsfp3_modprsl : std_logic;
signal qsfp3_intl : std_logic;
signal qsfp3_reset_n : std_logic;
--
signal qsfp4_axis_aclk : std_logic;
signal qsfp4_axis_aresetn : std_logic;
@@ -284,10 +272,6 @@ architecture arch_imp of qsfp_intfc_v1_0 is
signal qsfp2_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp2_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp3_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
signal qsfp3_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
signal qsfp3_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
signal slv_reg0 : std_logic_vector(31 downto 0);
signal slv_reg1 : std_logic_vector(31 downto 0);
signal slv_reg2 : std_logic_vector(31 downto 0);
@@ -375,39 +359,39 @@ begin
slv_reg19_in => clk_250_freq_r, -- 0x8000_004C
slv_reg20_in => clk_250_cnt_r, -- 0x8000_0050
slv_reg21_out => slv_reg21_out, -- 0x8000_0054
slv_reg22_out => slv_reg22_out, -- 0x8000_0058
slv_reg23_out => slv_reg23_out, -- 0x8000_005C *
slv_reg24_out => slv_reg24_out, -- 0x8000_0060
slv_reg25_out => slv_reg25_out, -- 0x8000_0064 *
slv_reg26_out => slv_reg26_out, -- 0x8000_0068 *
slv_reg27_out => slv_reg27_out, -- 0x8000_006C
slv_reg28_out => slv_reg28_out, -- 0x8000_0070
slv_reg21_out => open, -- 0x8000_0054
slv_reg22_out => open, -- 0x8000_0058
slv_reg23_out => open, -- 0x8000_005C
slv_reg24_out => open, -- 0x8000_0060
slv_reg25_out => open, -- 0x8000_0064
slv_reg26_out => open, -- 0x8000_0068
slv_reg27_out => open, -- 0x8000_006C
slv_reg28_out => open, -- 0x8000_0070
slv_reg29_out => slv_reg29_out, -- 0x8000_0074
slv_reg30_out => slv_reg30_out, -- 0x8000_0078
slv_reg31_out => slv_reg31_out, -- 0x8000_007C *
slv_reg32_out => slv_reg32_out, -- 0x8000_0080
slv_reg33_out => slv_reg33_out, -- 0x8000_0084 *
slv_reg34_out => slv_reg34_out, -- 0x8000_0088 *
slv_reg35_out => slv_reg35_out, -- 0x8000_008C
slv_reg36_out => slv_reg36_out, -- 0x8000_0090
slv_reg29_out => open, -- 0x8000_0074
slv_reg30_out => open, -- 0x8000_0078
slv_reg31_out => open, -- 0x8000_007C
slv_reg32_out => open, -- 0x8000_0080
slv_reg33_out => open, -- 0x8000_0084
slv_reg34_out => open, -- 0x8000_0088
slv_reg35_out => open, -- 0x8000_008C
slv_reg36_out => open, -- 0x8000_0090
slv_reg37_out => slv_reg37_out, -- 0x8000_0094
slv_reg38_out => slv_reg38_out, -- 0x8000_0098
slv_reg39_out => slv_reg39_out, -- 0x8000_009C *
slv_reg40_out => slv_reg40_out, -- 0x8000_00A0
slv_reg41_out => slv_reg41_out, -- 0x8000_00A4 *
slv_reg42_out => slv_reg42_out, -- 0x8000_00A8 *
slv_reg43_out => slv_reg43_out, -- 0x8000_00AC
slv_reg44_out => slv_reg44_out, -- 0x8000_00B0
slv_reg45_out => slv_reg45_out, -- 0x8000_00B4
slv_reg46_out => slv_reg46_out, -- 0x8000_00B8
slv_reg47_out => slv_reg47_out, -- 0x8000_00BC *
slv_reg48_out => slv_reg48_out, -- 0x8000_00C0
slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4 *
slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8 *
slv_reg37_out => open, -- 0x8000_0094
slv_reg38_out => open, -- 0x8000_0098
slv_reg39_out => open, -- 0x8000_009C
slv_reg40_out => open, -- 0x8000_00A0
slv_reg41_out => open, -- 0x8000_00A4
slv_reg42_out => open, -- 0x8000_00A8
slv_reg43_out => open, -- 0x8000_00AC
slv_reg44_out => open, -- 0x8000_00B0
slv_reg45_out => open, -- 0x8000_00B4
slv_reg46_out => open, -- 0x8000_00B8
slv_reg47_in => cmac_0_tx_tvalid_512b_cnt_in, -- 0x8000_00BC
slv_reg48_in => cmac_0_rx_tvalid_512b_cnt_in, -- 0x8000_00C0
slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4
slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8
slv_reg51_in => dig_iq_interface_ready_1_cnt_r, -- 0x8000_00CC
slv_reg52_in => adc_rx_tvalid_128b_overflow_cnt_in, -- 0x8000_00D0
@@ -415,7 +399,7 @@ begin
slv_reg54_in => qsfp1_capture_overflow_240b_cnt_in, -- 0x8000_00D8
slv_reg55_in => qsfp4_playback_tvalid_128b_cnt_in, -- 0x8000_00DC
slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0
slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0
slv_reg57_in => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 0x8000_00E4
slv_reg58_in => adc_rx_tvalid_128b_cnt_in, -- 0x8000_00E8
slv_reg59_in => fiber_tx_tvalid_128b_cnt_in, -- 0x8000_00EC
@@ -455,12 +439,12 @@ begin
slv_reg1(2) <= qsfp1_intl;
slv_reg1(3) <= '0';
slv_reg1(4) <= '0'; --dig_iq_interface_ready_1(0);
slv_reg1(5) <= '1'; --qsfp2_modprsl;
slv_reg1(6) <= '1'; --qsfp2_intl;
slv_reg1(5) <= qsfp2_modprsl;
slv_reg1(6) <= qsfp2_intl;
slv_reg1(7) <= '0';
slv_reg1(8) <= '0'; --dig_iq_interface_ready_1(1);
slv_reg1(9) <= '1'; --qsfp3_modprsl;
slv_reg1(10) <= '1'; --qsfp3_intl;
slv_reg1(9) <= qsfp3_modprsl;
slv_reg1(10) <= qsfp3_intl;
slv_reg1(11) <= '0';
slv_reg1(12) <= dig_iq_interface_ready(1);
slv_reg1(13) <= qsfp4_modprsl;
@@ -477,7 +461,9 @@ begin
--
dig_iq_cmd_strb_i <= slv_reg5(0); -- 0x8000_0014
qsfp1_reset_n_i <= slv_reg5(16);
qsfp4_reset_n_i <= slv_reg5(24);
qsfp2_reset_n_i <= slv_reg5(20);
qsfp3_reset_n_i <= slv_reg5(24);
qsfp4_reset_n_i <= slv_reg5(28);
--
dig_iq_cmd_wdata_i <= slv_reg6(31 downto 0); -- 0x8000_0018
--
@@ -512,6 +498,14 @@ begin
QSFP1_RESETL_LS <= qsfp1_reset_n;
qsfp1_modprsl <= QSFP1_MODPRSL_LS;
qsfp1_intl <= QSFP1_INTL_LS;
-------
QSFP2_RESETL_LS <= qsfp2_reset_n;
qsfp2_modprsl <= QSFP2_MODPRSL_LS;
qsfp2_intl <= QSFP2_INTL_LS;
-------
QSFP3_RESETL_LS <= qsfp3_reset_n;
qsfp3_modprsl <= QSFP3_MODPRSL_LS;
qsfp3_intl <= QSFP3_INTL_LS;
-------
QSFP4_TX1_P <= qsfp4_tx_txp(0);
QSFP4_TX1_N <= qsfp4_tx_txn(0);
@@ -545,6 +539,8 @@ begin
qsfp1_reset_n <= qsfp1_reset_n_i;
dig_iq_interface_reset(0) <= not qsfp1_reset_n;
qsfp2_reset_n <= qsfp2_reset_n_i;
qsfp3_reset_n <= qsfp3_reset_n_i;
qsfp4_reset_n <= qsfp4_reset_n_i;
dig_iq_interface_reset(1) <= not qsfp4_reset_n;
@@ -870,20 +866,6 @@ begin
end if;
end process;
process(qsfp3_clk_in)
begin
if (rising_edge(qsfp3_clk_in)) then
qsfp3_clk_tick_1ms_r <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms;
if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then
qsfp3_clk_freq_r <= qsfp3_clk_cnt_r;
qsfp3_clk_cnt_r <= (others => '0');
else
qsfp3_clk_cnt_r <= qsfp3_clk_cnt_r + 1;
end if;
end if;
end process;
process(pl_clk3_0)
begin
if (rising_edge(pl_clk3_0)) then
ip_repo/qsfp_intfc_1_0/hdl/qsfp_intfc_v1_0_S00_AXI.vhd
+36 -38
View File
@@ -68,8 +68,8 @@ entity qsfp_intfc_v1_0_S00_AXI is
slv_reg44_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg45_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg46_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg47_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg48_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg47_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg48_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg49_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg50_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
slv_reg51_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
@@ -374,41 +374,41 @@ begin
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= x"00008000"; --(UP-SWEEP) from 1MHz to 5MHz in 5uS
slv_reg22 <= x"00000000";
slv_reg23 <= x"0000D6BF";
slv_reg24 <= x"00000000";
slv_reg25 <= x"000004E2"; --(~5 us)
slv_reg26 <= x"010624DD"; --(~1 MHz)
slv_reg27 <= x"00000000";
slv_reg28 <= x"00008000";
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= x"00008000"; --(DOWN-SWEEP)
slv_reg30 <= x"00000000";
slv_reg31 <= x"00FEF391";
slv_reg32 <= x"00000000";
slv_reg33 <= x"000004E2"; --(~5 us)
slv_reg34 <= x"0624DD2F"; --(~6 MHz)
slv_reg35 <= x"00000000";
slv_reg36 <= x"00008000";
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
slv_reg32 <= (others => '0');
slv_reg33 <= (others => '0');
slv_reg34 <= (others => '0');
slv_reg35 <= (others => '0');
slv_reg36 <= (others => '0');
slv_reg37 <= x"00008000"; --(CW)
slv_reg38 <= x"00000000";
slv_reg39 <= x"00000000";
slv_reg40 <= x"00000000";
slv_reg41 <= x"000004E2"; --(~5 us)
slv_reg42 <= x"0A3D70A3"; --(~10 MHz)
slv_reg43 <= x"00000000";
slv_reg44 <= x"00008000";
slv_reg37 <= (others => '0');
slv_reg38 <= (others => '0');
slv_reg39 <= (others => '0');
slv_reg40 <= (others => '0');
slv_reg41 <= (others => '0');
slv_reg42 <= (others => '0');
slv_reg43 <= (others => '0');
slv_reg44 <= (others => '0');
slv_reg45 <= x"00008000"; --(CW)
slv_reg46 <= x"00000000";
slv_reg47 <= x"00000000";
slv_reg48 <= x"00000000";
slv_reg49 <= x"000004E2"; --(~5 us)
slv_reg50 <= x"0F5C28F5"; --(~15 MHz)
slv_reg51 <= x"00000000";
slv_reg52 <= x"00008000";
slv_reg45 <= (others => '0');
slv_reg46 <= (others => '0');
slv_reg47 <= (others => '0');
slv_reg48 <= (others => '0');
slv_reg49 <= (others => '0');
slv_reg50 <= (others => '0');
slv_reg51 <= (others => '0');
slv_reg52 <= (others => '0');
slv_reg53 <= (others => '0');
slv_reg54 <= (others => '0');
@@ -1202,9 +1202,9 @@ begin
when b"101110" =>
reg_data_out <= slv_reg46;
when b"101111" =>
reg_data_out <= slv_reg47;
reg_data_out <= slv_reg47_in;
when b"110000" =>
reg_data_out <= slv_reg48;
reg_data_out <= slv_reg48_in;
when b"110001" =>
reg_data_out <= slv_reg49_in; --slv_reg49;
when b"110010" =>
@@ -1314,8 +1314,6 @@ begin
slv_reg44_out <= slv_reg44;
slv_reg45_out <= slv_reg45;
slv_reg46_out <= slv_reg46;
slv_reg47_out <= slv_reg47;
slv_reg48_out <= slv_reg48;
-- User logic ends