added CMAC interface out of QSFP3
This commit is contained in:
@@ -44,21 +44,6 @@ architecture imp of si5332_wrapper is
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signal man_clk_gen_en : std_logic := '0';
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signal man_clk_gen_cfg_reset : std_logic := '0';
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signal clk_100_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
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signal clk_100_freq_r : std_logic_vector(31 downto 0) := (others => '0');
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signal clk_100_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal qsfp2_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
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signal qsfp2_freq_r : std_logic_vector(31 downto 0) := (others => '0');
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signal qsfp2_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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signal qsfp3_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
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signal qsfp3_freq_r : std_logic_vector(31 downto 0) := (others => '0');
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signal qsfp3_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
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begin
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@@ -105,63 +90,4 @@ begin
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reset_in => clk_100_areset_in
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);
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-- i_vio_3 : entity work.vio_3
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-- port map (
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-- clk => clk_100_in,
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-- probe_in0(0) => i2c_mux_access_ok, -- 1
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-- probe_in1(0) => si5341_access_ok, -- 1
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-- probe_in2(0) => si5341_config_done, -- 1
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-- probe_in3(0) => si5341_config_error, -- 1
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-- probe_in4 => clk_100_freq_r, -- 32
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-- probe_in5 => clk_100_cnt_r, -- 32
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-- probe_in6 => qsfp2_freq_r, -- 32
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-- probe_in7 => qsfp2_cnt_r, -- 32
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-- probe_in8 => qsfp3_freq_r, -- 32
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-- probe_in9 => qsfp3_cnt_r, -- 32
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--
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-- probe_out0(0) => man_clk_gen_en, -- 1
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-- probe_out1(0) => man_clk_gen_cfg_reset -- 1
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-- );
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process(clk_100_in)
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begin
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if (rising_edge(clk_100_in)) then
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clk_100_tick_1ms_r <= clk_100_tick_1ms_r(1 to 2) & tick_1ms;
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if (clk_100_tick_1ms_r(0 to 1) = "01") then
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clk_100_freq_r <= clk_100_cnt_r;
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clk_100_cnt_r <= (others => '0');
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else
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clk_100_cnt_r <= clk_100_cnt_r + 1;
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end if;
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end if;
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end process;
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process(qsfp2_clk_in)
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begin
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if (rising_edge(qsfp2_clk_in)) then
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qsfp2_tick_1ms_r <= qsfp2_tick_1ms_r(1 to 2) & tick_1ms;
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if (qsfp2_tick_1ms_r(0 to 1) = "01") then
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qsfp2_freq_r <= qsfp2_cnt_r;
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qsfp2_cnt_r <= (others => '0');
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else
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qsfp2_cnt_r <= qsfp2_cnt_r + 1;
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end if;
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end if;
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end process;
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process(qsfp3_clk_in)
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begin
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if (rising_edge(qsfp3_clk_in)) then
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qsfp3_tick_1ms_r <= qsfp3_tick_1ms_r(1 to 2) & tick_1ms;
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if (qsfp3_tick_1ms_r(0 to 1) = "01") then
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qsfp3_freq_r <= qsfp3_cnt_r;
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qsfp3_cnt_r <= (others => '0');
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else
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qsfp3_cnt_r <= qsfp3_cnt_r + 1;
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end if;
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end if;
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end process;
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end architecture imp;
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+106
-1
@@ -718,6 +718,49 @@
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>axis_register_slice_v1_1_29_axis_register_slice</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
|
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Jul 15 19:17:47 UTC 2026</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:abb75340</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
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<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>axis_register_slice_32</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
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<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Wed Jul 15 19:17:47 UTC 2026</spirit:value>
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||||
</spirit:parameter>
|
||||
<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:abb75340</spirit:value>
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</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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@@ -771,6 +814,7 @@
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@@ -783,6 +827,7 @@
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
|
||||
<spirit:driver>
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@@ -805,6 +850,7 @@
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<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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@@ -820,6 +866,7 @@
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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||||
</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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@@ -842,6 +889,7 @@
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
|
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<spirit:driver>
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||||
@@ -857,6 +905,7 @@
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||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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@@ -880,6 +929,7 @@
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<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
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||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
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@@ -906,6 +956,7 @@
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||||
<spirit:wireTypeDef>
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||||
<spirit:typeName>wire</spirit:typeName>
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||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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||||
<spirit:driver>
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@@ -932,6 +983,7 @@
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||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
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@@ -954,6 +1006,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -980,6 +1033,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
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@@ -1006,6 +1060,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1032,6 +1087,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1054,6 +1110,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1066,6 +1123,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
@@ -1092,6 +1150,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1115,6 +1174,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1138,6 +1198,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1157,6 +1218,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1180,6 +1242,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1203,6 +1266,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1226,6 +1290,7 @@
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>wire</spirit:typeName>
|
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
@@ -1366,6 +1431,46 @@
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
|
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<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogbehavioralsimulation_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset</spirit:name>
|
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<spirit:file>
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||||
<spirit:name>hdl/axis_infrastructure_v1_1_1.vh</spirit:name>
|
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<spirit:fileType>verilogSource</spirit:fileType>
|
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<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:isIncludeFile>true</spirit:isIncludeFile>
|
||||
<spirit:logicalName>axis_infrastructure_v1_1_1</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/axis_infrastructure_v1_1_vl_rfs.v</spirit:name>
|
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<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>axis_infrastructure_v1_1_1</spirit:logicalName>
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</spirit:file>
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<spirit:vendorExtensions>
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<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_infrastructure" xilinx:version="1.1" xilinx:isGenerated="true" xilinx:checksum="793e142a">
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||||
<xilinx:mode xilinx:name="copy_mode"/>
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||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
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</spirit:vendorExtensions>
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||||
</spirit:fileSet>
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<spirit:fileSet>
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||||
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/axis_register_slice_v1_1_vl_rfs.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>axis_register_slice_v1_1_29</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/axis_register_slice_32.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
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</spirit:file>
|
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</spirit:fileSet>
|
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<spirit:fileSet>
|
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<spirit:name>xilinx_verilogsynthesis_xilinx_com_ip_axis_infrastructure_1_1__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
@@ -1381,7 +1486,7 @@
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xsi:type="xilinx:componentRefType" xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_infrastructure" xilinx:version="1.1" xilinx:isGenerated="true" xilinx:checksum="793e142a">
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axis_infrastructure" xilinx:version="1.1" xilinx:isGenerated="true" xilinx:checksum="793e142a">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
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||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
"xci_name": "addsub",
|
||||
"component_reference": "xilinx.com:ip:c_addsub:12.0",
|
||||
"ip_revision": "16",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/addsub",
|
||||
"gen_directory": "../../ad9081_fmca_ebz_vcu128.gen/sources_1/ip/addsub",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "addsub", "resolve_type": "user", "usage": "all" } ],
|
||||
|
||||
@@ -35,7 +35,6 @@ entity qsfp_intfc_v1_0 is
|
||||
-- sysref_in : in std_logic;
|
||||
ref_clk_div2_in : in std_logic;
|
||||
qsfp2_clk_in : in std_logic;
|
||||
qsfp3_clk_in : in std_logic;
|
||||
pl_clk3_0 : in std_logic;
|
||||
|
||||
QSFP1_SI570_CLOCK_P : in std_logic;
|
||||
@@ -63,6 +62,14 @@ entity qsfp_intfc_v1_0 is
|
||||
QSFP1_RESETL_LS : out std_logic;
|
||||
QSFP1_MODPRSL_LS : in std_logic;
|
||||
QSFP1_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP2_RESETL_LS : out std_logic;
|
||||
QSFP2_MODPRSL_LS : in std_logic;
|
||||
QSFP2_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP3_RESETL_LS : out std_logic;
|
||||
QSFP3_MODPRSL_LS : in std_logic;
|
||||
QSFP3_INTL_LS : in std_logic;
|
||||
-----------------
|
||||
QSFP4_SI570_CLOCK_P : in std_logic;
|
||||
QSFP4_SI570_CLOCK_N : in std_logic;
|
||||
@@ -107,7 +114,7 @@ entity qsfp_intfc_v1_0 is
|
||||
qsfp1_capture_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_tx_fifo_128_aempty_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_capture_rx_data_ready_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
qsfp1_tx_fifo_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
mem_xfer_tx_upload_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
dac_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
@@ -117,42 +124,13 @@ entity qsfp_intfc_v1_0 is
|
||||
qsfp4_playback_tvalid_240b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
fiber_tx_tvalid_128b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
cmac_0_tx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
cmac_0_rx_tvalid_512b_cnt_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
cnt_reset_out : out std_logic;
|
||||
|
||||
slv_reg9_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg10_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg21_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg22_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg23_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg24_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg25_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg26_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg27_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg28_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg29_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg30_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg31_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg32_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg33_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg34_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg35_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg36_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg37_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg38_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg39_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg40_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
slv_reg41_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg42_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg43_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg44_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg45_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg46_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg47_out : out std_logic_vector(31 downto 0);
|
||||
slv_reg48_out : out std_logic_vector(31 downto 0);
|
||||
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
@@ -226,6 +204,16 @@ architecture arch_imp of qsfp_intfc_v1_0 is
|
||||
|
||||
signal qsfp1_m_axis_tdata : std_logic_vector(239 downto 0);
|
||||
signal qsfp1_m_axis_tvalid : std_logic;
|
||||
--
|
||||
signal qsfp2_reset_n_i : std_logic;
|
||||
signal qsfp2_modprsl : std_logic;
|
||||
signal qsfp2_intl : std_logic;
|
||||
signal qsfp2_reset_n : std_logic;
|
||||
--
|
||||
signal qsfp3_reset_n_i : std_logic;
|
||||
signal qsfp3_modprsl : std_logic;
|
||||
signal qsfp3_intl : std_logic;
|
||||
signal qsfp3_reset_n : std_logic;
|
||||
--
|
||||
signal qsfp4_axis_aclk : std_logic;
|
||||
signal qsfp4_axis_aresetn : std_logic;
|
||||
@@ -284,10 +272,6 @@ architecture arch_imp of qsfp_intfc_v1_0 is
|
||||
signal qsfp2_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp2_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal qsfp3_clk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal qsfp3_clk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal qsfp3_clk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal slv_reg0 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg1 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg2 : std_logic_vector(31 downto 0);
|
||||
@@ -375,39 +359,39 @@ begin
|
||||
slv_reg19_in => clk_250_freq_r, -- 0x8000_004C
|
||||
slv_reg20_in => clk_250_cnt_r, -- 0x8000_0050
|
||||
|
||||
slv_reg21_out => slv_reg21_out, -- 0x8000_0054
|
||||
slv_reg22_out => slv_reg22_out, -- 0x8000_0058
|
||||
slv_reg23_out => slv_reg23_out, -- 0x8000_005C *
|
||||
slv_reg24_out => slv_reg24_out, -- 0x8000_0060
|
||||
slv_reg25_out => slv_reg25_out, -- 0x8000_0064 *
|
||||
slv_reg26_out => slv_reg26_out, -- 0x8000_0068 *
|
||||
slv_reg27_out => slv_reg27_out, -- 0x8000_006C
|
||||
slv_reg28_out => slv_reg28_out, -- 0x8000_0070
|
||||
slv_reg21_out => open, -- 0x8000_0054
|
||||
slv_reg22_out => open, -- 0x8000_0058
|
||||
slv_reg23_out => open, -- 0x8000_005C
|
||||
slv_reg24_out => open, -- 0x8000_0060
|
||||
slv_reg25_out => open, -- 0x8000_0064
|
||||
slv_reg26_out => open, -- 0x8000_0068
|
||||
slv_reg27_out => open, -- 0x8000_006C
|
||||
slv_reg28_out => open, -- 0x8000_0070
|
||||
|
||||
slv_reg29_out => slv_reg29_out, -- 0x8000_0074
|
||||
slv_reg30_out => slv_reg30_out, -- 0x8000_0078
|
||||
slv_reg31_out => slv_reg31_out, -- 0x8000_007C *
|
||||
slv_reg32_out => slv_reg32_out, -- 0x8000_0080
|
||||
slv_reg33_out => slv_reg33_out, -- 0x8000_0084 *
|
||||
slv_reg34_out => slv_reg34_out, -- 0x8000_0088 *
|
||||
slv_reg35_out => slv_reg35_out, -- 0x8000_008C
|
||||
slv_reg36_out => slv_reg36_out, -- 0x8000_0090
|
||||
slv_reg29_out => open, -- 0x8000_0074
|
||||
slv_reg30_out => open, -- 0x8000_0078
|
||||
slv_reg31_out => open, -- 0x8000_007C
|
||||
slv_reg32_out => open, -- 0x8000_0080
|
||||
slv_reg33_out => open, -- 0x8000_0084
|
||||
slv_reg34_out => open, -- 0x8000_0088
|
||||
slv_reg35_out => open, -- 0x8000_008C
|
||||
slv_reg36_out => open, -- 0x8000_0090
|
||||
|
||||
slv_reg37_out => slv_reg37_out, -- 0x8000_0094
|
||||
slv_reg38_out => slv_reg38_out, -- 0x8000_0098
|
||||
slv_reg39_out => slv_reg39_out, -- 0x8000_009C *
|
||||
slv_reg40_out => slv_reg40_out, -- 0x8000_00A0
|
||||
slv_reg41_out => slv_reg41_out, -- 0x8000_00A4 *
|
||||
slv_reg42_out => slv_reg42_out, -- 0x8000_00A8 *
|
||||
slv_reg43_out => slv_reg43_out, -- 0x8000_00AC
|
||||
slv_reg44_out => slv_reg44_out, -- 0x8000_00B0
|
||||
|
||||
slv_reg45_out => slv_reg45_out, -- 0x8000_00B4
|
||||
slv_reg46_out => slv_reg46_out, -- 0x8000_00B8
|
||||
slv_reg47_out => slv_reg47_out, -- 0x8000_00BC *
|
||||
slv_reg48_out => slv_reg48_out, -- 0x8000_00C0
|
||||
slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4 *
|
||||
slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8 *
|
||||
slv_reg37_out => open, -- 0x8000_0094
|
||||
slv_reg38_out => open, -- 0x8000_0098
|
||||
slv_reg39_out => open, -- 0x8000_009C
|
||||
slv_reg40_out => open, -- 0x8000_00A0
|
||||
slv_reg41_out => open, -- 0x8000_00A4
|
||||
slv_reg42_out => open, -- 0x8000_00A8
|
||||
slv_reg43_out => open, -- 0x8000_00AC
|
||||
slv_reg44_out => open, -- 0x8000_00B0
|
||||
|
||||
slv_reg45_out => open, -- 0x8000_00B4
|
||||
slv_reg46_out => open, -- 0x8000_00B8
|
||||
slv_reg47_in => cmac_0_tx_tvalid_512b_cnt_in, -- 0x8000_00BC
|
||||
slv_reg48_in => cmac_0_rx_tvalid_512b_cnt_in, -- 0x8000_00C0
|
||||
slv_reg49_in => qsfp1_capture_tvalid_512b_cnt_in, -- 0x8000_00C4
|
||||
slv_reg50_in => dig_iq_interface_ready_0_cnt_r, -- 0x8000_00C8
|
||||
slv_reg51_in => dig_iq_interface_ready_1_cnt_r, -- 0x8000_00CC
|
||||
slv_reg52_in => adc_rx_tvalid_128b_overflow_cnt_in, -- 0x8000_00D0
|
||||
|
||||
@@ -415,7 +399,7 @@ begin
|
||||
slv_reg54_in => qsfp1_capture_overflow_240b_cnt_in, -- 0x8000_00D8
|
||||
|
||||
slv_reg55_in => qsfp4_playback_tvalid_128b_cnt_in, -- 0x8000_00DC
|
||||
slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0
|
||||
slv_reg56_in => qsfp1_tx_fifo_tvalid_128b_cnt_in, -- 0x8000_00E0
|
||||
slv_reg57_in => mem_xfer_tx_upload_tvalid_128b_cnt_in, -- 0x8000_00E4
|
||||
slv_reg58_in => adc_rx_tvalid_128b_cnt_in, -- 0x8000_00E8
|
||||
slv_reg59_in => fiber_tx_tvalid_128b_cnt_in, -- 0x8000_00EC
|
||||
@@ -455,12 +439,12 @@ begin
|
||||
slv_reg1(2) <= qsfp1_intl;
|
||||
slv_reg1(3) <= '0';
|
||||
slv_reg1(4) <= '0'; --dig_iq_interface_ready_1(0);
|
||||
slv_reg1(5) <= '1'; --qsfp2_modprsl;
|
||||
slv_reg1(6) <= '1'; --qsfp2_intl;
|
||||
slv_reg1(5) <= qsfp2_modprsl;
|
||||
slv_reg1(6) <= qsfp2_intl;
|
||||
slv_reg1(7) <= '0';
|
||||
slv_reg1(8) <= '0'; --dig_iq_interface_ready_1(1);
|
||||
slv_reg1(9) <= '1'; --qsfp3_modprsl;
|
||||
slv_reg1(10) <= '1'; --qsfp3_intl;
|
||||
slv_reg1(9) <= qsfp3_modprsl;
|
||||
slv_reg1(10) <= qsfp3_intl;
|
||||
slv_reg1(11) <= '0';
|
||||
slv_reg1(12) <= dig_iq_interface_ready(1);
|
||||
slv_reg1(13) <= qsfp4_modprsl;
|
||||
@@ -477,7 +461,9 @@ begin
|
||||
--
|
||||
dig_iq_cmd_strb_i <= slv_reg5(0); -- 0x8000_0014
|
||||
qsfp1_reset_n_i <= slv_reg5(16);
|
||||
qsfp4_reset_n_i <= slv_reg5(24);
|
||||
qsfp2_reset_n_i <= slv_reg5(20);
|
||||
qsfp3_reset_n_i <= slv_reg5(24);
|
||||
qsfp4_reset_n_i <= slv_reg5(28);
|
||||
--
|
||||
dig_iq_cmd_wdata_i <= slv_reg6(31 downto 0); -- 0x8000_0018
|
||||
--
|
||||
@@ -512,6 +498,14 @@ begin
|
||||
QSFP1_RESETL_LS <= qsfp1_reset_n;
|
||||
qsfp1_modprsl <= QSFP1_MODPRSL_LS;
|
||||
qsfp1_intl <= QSFP1_INTL_LS;
|
||||
-------
|
||||
QSFP2_RESETL_LS <= qsfp2_reset_n;
|
||||
qsfp2_modprsl <= QSFP2_MODPRSL_LS;
|
||||
qsfp2_intl <= QSFP2_INTL_LS;
|
||||
-------
|
||||
QSFP3_RESETL_LS <= qsfp3_reset_n;
|
||||
qsfp3_modprsl <= QSFP3_MODPRSL_LS;
|
||||
qsfp3_intl <= QSFP3_INTL_LS;
|
||||
-------
|
||||
QSFP4_TX1_P <= qsfp4_tx_txp(0);
|
||||
QSFP4_TX1_N <= qsfp4_tx_txn(0);
|
||||
@@ -545,6 +539,8 @@ begin
|
||||
|
||||
qsfp1_reset_n <= qsfp1_reset_n_i;
|
||||
dig_iq_interface_reset(0) <= not qsfp1_reset_n;
|
||||
qsfp2_reset_n <= qsfp2_reset_n_i;
|
||||
qsfp3_reset_n <= qsfp3_reset_n_i;
|
||||
qsfp4_reset_n <= qsfp4_reset_n_i;
|
||||
dig_iq_interface_reset(1) <= not qsfp4_reset_n;
|
||||
|
||||
@@ -870,20 +866,6 @@ begin
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(qsfp3_clk_in)
|
||||
begin
|
||||
if (rising_edge(qsfp3_clk_in)) then
|
||||
qsfp3_clk_tick_1ms_r <= qsfp3_clk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (qsfp3_clk_tick_1ms_r(0 to 1) = "01") then
|
||||
qsfp3_clk_freq_r <= qsfp3_clk_cnt_r;
|
||||
qsfp3_clk_cnt_r <= (others => '0');
|
||||
else
|
||||
qsfp3_clk_cnt_r <= qsfp3_clk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process(pl_clk3_0)
|
||||
begin
|
||||
if (rising_edge(pl_clk3_0)) then
|
||||
|
||||
@@ -68,8 +68,8 @@ entity qsfp_intfc_v1_0_S00_AXI is
|
||||
slv_reg44_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg45_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg46_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg47_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg48_out :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg47_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg48_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg49_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg50_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg51_in :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
@@ -374,41 +374,41 @@ begin
|
||||
slv_reg19 <= (others => '0');
|
||||
slv_reg20 <= (others => '0');
|
||||
|
||||
slv_reg21 <= x"00008000"; --(UP-SWEEP) from 1MHz to 5MHz in 5uS
|
||||
slv_reg22 <= x"00000000";
|
||||
slv_reg23 <= x"0000D6BF";
|
||||
slv_reg24 <= x"00000000";
|
||||
slv_reg25 <= x"000004E2"; --(~5 us)
|
||||
slv_reg26 <= x"010624DD"; --(~1 MHz)
|
||||
slv_reg27 <= x"00000000";
|
||||
slv_reg28 <= x"00008000";
|
||||
slv_reg21 <= (others => '0');
|
||||
slv_reg22 <= (others => '0');
|
||||
slv_reg23 <= (others => '0');
|
||||
slv_reg24 <= (others => '0');
|
||||
slv_reg25 <= (others => '0');
|
||||
slv_reg26 <= (others => '0');
|
||||
slv_reg27 <= (others => '0');
|
||||
slv_reg28 <= (others => '0');
|
||||
|
||||
slv_reg29 <= x"00008000"; --(DOWN-SWEEP)
|
||||
slv_reg30 <= x"00000000";
|
||||
slv_reg31 <= x"00FEF391";
|
||||
slv_reg32 <= x"00000000";
|
||||
slv_reg33 <= x"000004E2"; --(~5 us)
|
||||
slv_reg34 <= x"0624DD2F"; --(~6 MHz)
|
||||
slv_reg35 <= x"00000000";
|
||||
slv_reg36 <= x"00008000";
|
||||
slv_reg29 <= (others => '0');
|
||||
slv_reg30 <= (others => '0');
|
||||
slv_reg31 <= (others => '0');
|
||||
slv_reg32 <= (others => '0');
|
||||
slv_reg33 <= (others => '0');
|
||||
slv_reg34 <= (others => '0');
|
||||
slv_reg35 <= (others => '0');
|
||||
slv_reg36 <= (others => '0');
|
||||
|
||||
slv_reg37 <= x"00008000"; --(CW)
|
||||
slv_reg38 <= x"00000000";
|
||||
slv_reg39 <= x"00000000";
|
||||
slv_reg40 <= x"00000000";
|
||||
slv_reg41 <= x"000004E2"; --(~5 us)
|
||||
slv_reg42 <= x"0A3D70A3"; --(~10 MHz)
|
||||
slv_reg43 <= x"00000000";
|
||||
slv_reg44 <= x"00008000";
|
||||
slv_reg37 <= (others => '0');
|
||||
slv_reg38 <= (others => '0');
|
||||
slv_reg39 <= (others => '0');
|
||||
slv_reg40 <= (others => '0');
|
||||
slv_reg41 <= (others => '0');
|
||||
slv_reg42 <= (others => '0');
|
||||
slv_reg43 <= (others => '0');
|
||||
slv_reg44 <= (others => '0');
|
||||
|
||||
slv_reg45 <= x"00008000"; --(CW)
|
||||
slv_reg46 <= x"00000000";
|
||||
slv_reg47 <= x"00000000";
|
||||
slv_reg48 <= x"00000000";
|
||||
slv_reg49 <= x"000004E2"; --(~5 us)
|
||||
slv_reg50 <= x"0F5C28F5"; --(~15 MHz)
|
||||
slv_reg51 <= x"00000000";
|
||||
slv_reg52 <= x"00008000";
|
||||
slv_reg45 <= (others => '0');
|
||||
slv_reg46 <= (others => '0');
|
||||
slv_reg47 <= (others => '0');
|
||||
slv_reg48 <= (others => '0');
|
||||
slv_reg49 <= (others => '0');
|
||||
slv_reg50 <= (others => '0');
|
||||
slv_reg51 <= (others => '0');
|
||||
slv_reg52 <= (others => '0');
|
||||
|
||||
slv_reg53 <= (others => '0');
|
||||
slv_reg54 <= (others => '0');
|
||||
@@ -1202,9 +1202,9 @@ begin
|
||||
when b"101110" =>
|
||||
reg_data_out <= slv_reg46;
|
||||
when b"101111" =>
|
||||
reg_data_out <= slv_reg47;
|
||||
reg_data_out <= slv_reg47_in;
|
||||
when b"110000" =>
|
||||
reg_data_out <= slv_reg48;
|
||||
reg_data_out <= slv_reg48_in;
|
||||
when b"110001" =>
|
||||
reg_data_out <= slv_reg49_in; --slv_reg49;
|
||||
when b"110010" =>
|
||||
@@ -1314,8 +1314,6 @@ begin
|
||||
slv_reg44_out <= slv_reg44;
|
||||
slv_reg45_out <= slv_reg45;
|
||||
slv_reg46_out <= slv_reg46;
|
||||
slv_reg47_out <= slv_reg47;
|
||||
slv_reg48_out <= slv_reg48;
|
||||
|
||||
-- User logic ends
|
||||
|
||||
|
||||
Reference in New Issue
Block a user