xilinx.com user dds_pulse_wrapper 1.0 m_axis_out TDATA m_axis_tdata_out TVALID m_axis_tvalid_out TREADY m_axis_tready_in xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL dds_pulse_wrapper xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum d4e6fb9a xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL dds_pulse_wrapper xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset 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xgui/dds_pulse_wrapper_v1_0.tcl tclSource CHECKSUM_c12c7cc7 XGUI_VERSION_2 dds_pulse_wrapper_v1_0 SIM_ENABLED Sim Enabled FALSE Component_Name dds_pulse_wrapper_v1_0 FPGA_REVISION_DATE Fpga Revision Date 0x10242023 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /UserIP dds_pulse_wrapper_v1_0 package_project XPM_CDC XPM_FIFO XPM_MEMORY 22 2023-10-24T20:32:50Z 2022.2