-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:53:22 03/24/2017 -- Design Name: -- Module Name: -- Project Name: xem7350 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: dac_interface -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; entity tb_fifos is end tb_fifos; architecture behavior of tb_fifos is constant C_M_AXI_DATA_WIDTH : integer := 32; constant C_M_AXI_ADDR_WIDTH : integer := 32; -- Clock period definitions constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz signal m_axis_aclk : std_logic := '0'; signal reset_n : std_logic_vector(0 to 2) := (others => '0'); signal reset : std_logic; signal s00_axi_aclk : std_logic := '0'; signal dds_pulse_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal dds_pulse_dval_0 : std_logic := '0'; signal m_axis_tdata_0 : std_logic_vector(31 downto 0); signal m_axis_tvalid_0 : std_logic; signal dds_pulse_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal dds_pulse_dval_1 : std_logic := '0'; signal m_axis_tdata_1 : std_logic_vector(31 downto 0); signal m_axis_tvalid_1 : std_logic; signal dds_pulse_data_2 : std_logic_vector(31 downto 0) := (others => '0'); signal dds_pulse_dval_2 : std_logic := '0'; signal m_axis_tdata_2 : std_logic_vector(31 downto 0); signal m_axis_tvalid_2 : std_logic; signal dds_pulse_data_3 : std_logic_vector(31 downto 0) := (others => '0'); signal dds_pulse_dval_3 : std_logic := '0'; signal m_axis_tdata_3 : std_logic_vector(31 downto 0); signal m_axis_tvalid_3 : std_logic; signal dds_pulse_data_word : std_logic_vector(127 downto 0); signal dds_pulse_data_word_dval : std_logic; signal dds_pulse_data_word_tready : std_logic; signal dds_pulse_data_word_tready_valid : std_logic; signal m_axis_tdata_i : std_logic_vector(127 downto 0); signal m_axis_tvalid_i : std_logic; signal m_axis_tready_i : std_logic; signal s_axis_tready_0 : std_logic; signal s_axis_tready_1 : std_logic; signal s_axis_tready_2 : std_logic; signal s_axis_tready_3 : std_logic; signal fifo_en : std_logic := '1'; signal fifo_rd_data_0 : std_logic_vector(15 downto 0); signal fifo_rd_data_1 : std_logic_vector(15 downto 0); signal fifo_rd_data_2 : std_logic_vector(15 downto 0); signal fifo_rd_data_3 : std_logic_vector(15 downto 0); signal fifo_rd_data_4 : std_logic_vector(15 downto 0); signal fifo_rd_data_5 : std_logic_vector(15 downto 0); signal fifo_rd_data_6 : std_logic_vector(15 downto 0); signal fifo_rd_data_7 : std_logic_vector(15 downto 0); signal fifo_rd_data_8 : std_logic_vector(15 downto 0); signal fifo_rd_data_9 : std_logic_vector(15 downto 0); signal fifo_rd_data_10 : std_logic_vector(15 downto 0); signal fifo_rd_data_11 : std_logic_vector(15 downto 0); signal fifo_rd_data_12 : std_logic_vector(15 downto 0); signal fifo_rd_data_13 : std_logic_vector(15 downto 0); signal fifo_rd_data_14 : std_logic_vector(15 downto 0); signal fifo_rd_data_15 : std_logic_vector(15 downto 0); signal fifo_rd_data_16 : std_logic_vector(15 downto 0); signal fifo_rd_data_17 : std_logic_vector(15 downto 0); signal fifo_rd_data_18 : std_logic_vector(15 downto 0); signal fifo_rd_data_19 : std_logic_vector(15 downto 0); signal fifo_rd_data_20 : std_logic_vector(15 downto 0); signal fifo_rd_data_21 : std_logic_vector(15 downto 0); signal fifo_rd_data_22 : std_logic_vector(15 downto 0); signal fifo_rd_data_23 : std_logic_vector(15 downto 0); signal fifo_rd_data_24 : std_logic_vector(15 downto 0); signal fifo_rd_data_25 : std_logic_vector(15 downto 0); signal fifo_rd_data_26 : std_logic_vector(15 downto 0); signal fifo_rd_data_27 : std_logic_vector(15 downto 0); signal fifo_rd_data_28 : std_logic_vector(15 downto 0); signal fifo_rd_data_29 : std_logic_vector(15 downto 0); signal fifo_rd_data_30 : std_logic_vector(15 downto 0); signal fifo_rd_data_31 : std_logic_vector(15 downto 0); signal fifo_rd_data_32 : std_logic_vector(15 downto 0); signal fifo_rd_data_33 : std_logic_vector(15 downto 0); signal fifo_rd_data_34 : std_logic_vector(15 downto 0); signal fifo_rd_data_35 : std_logic_vector(15 downto 0); signal fifo_rd_data_36 : std_logic_vector(15 downto 0); signal fifo_rd_data_37 : std_logic_vector(15 downto 0); signal fifo_rd_data_38 : std_logic_vector(15 downto 0); signal fifo_rd_data_39 : std_logic_vector(15 downto 0); signal fifo_rd_data_40 : std_logic_vector(15 downto 0); signal fifo_rd_data_41 : std_logic_vector(15 downto 0); signal fifo_rd_data_42 : std_logic_vector(15 downto 0); signal fifo_rd_data_43 : std_logic_vector(15 downto 0); signal fifo_rd_data_44 : std_logic_vector(15 downto 0); signal fifo_rd_data_45 : std_logic_vector(15 downto 0); signal fifo_rd_data_46 : std_logic_vector(15 downto 0); signal fifo_rd_data_47 : std_logic_vector(15 downto 0); signal fifo_rd_data_48 : std_logic_vector(15 downto 0); signal fifo_rd_data_49 : std_logic_vector(15 downto 0); signal fifo_rd_data_50 : std_logic_vector(15 downto 0); signal fifo_rd_data_51 : std_logic_vector(15 downto 0); signal fifo_rd_data_52 : std_logic_vector(15 downto 0); signal fifo_rd_data_53 : std_logic_vector(15 downto 0); signal fifo_rd_data_54 : std_logic_vector(15 downto 0); signal fifo_rd_data_55 : std_logic_vector(15 downto 0); signal fifo_rd_data_56 : std_logic_vector(15 downto 0); signal fifo_rd_data_57 : std_logic_vector(15 downto 0); signal fifo_rd_data_58 : std_logic_vector(15 downto 0); signal fifo_rd_data_59 : std_logic_vector(15 downto 0); signal fifo_rd_data_60 : std_logic_vector(15 downto 0); signal fifo_rd_data_61 : std_logic_vector(15 downto 0); signal fifo_rd_data_62 : std_logic_vector(15 downto 0); signal fifo_rd_data_63 : std_logic_vector(15 downto 0); signal fifo_rd_valid : std_logic; signal fifo_rd_underflow : std_logic; signal cmd_send_0 : std_logic := '0'; signal dac_holdoff_0 : std_logic := '1'; signal fifo_rd_en : std_logic := '0'; begin m_axis_aclk <= not m_axis_aclk after M_AXI_ACLK_PERIOD/2; s00_axi_aclk <= not s00_axi_aclk after S_AXI_ACLK_PERIOD/2; process(m_axis_aclk) begin if (rising_edge(m_axis_aclk)) then reset_n <= reset_n(1 to 2) & '1'; if (reset_n = "111") then fifo_rd_en <= not fifo_rd_en; end if; end if; end process; reset <= not reset_n(0); -- i_pdw_wrapper_0 : entity work.pdw_wrapper -- generic map ( -- SIM_ENABLED => FALSE, -- FPGA_REVISION_DATE => x"0528_2024", -- MINOR_REV => x"01" -- ) -- port map ( -- s_axi_aclk_in => s00_axi_aclk, -- s_axi_aresetn_in => reset_n(0), -- cmd_idx_in => "010", -- cmd_send_in => cmd_send_0, -- loop_mode_en_in => x"00", -- -- mode_in => '0', -- scale_in => x"8000", -- dac_holdoff_in => dac_holdoff_0, -- -- reserv1_in => x"00000000", -- dds_phase_inc_dwell_time_in => x"00000000", -- dds_phase_inc_step_size_in => x"00000000", -- idle_samples_in => x"00000000", -- dds_samples_in => x"000004E2", -- phase_inc_in => x"0624DD2F", -- phase_off_in => x"00000000", -- swap_sf_in => x"00008000", -- latch_en_in => '0', -- -- reserv1_out => open, -- dds_phase_inc_dwell_time_out => open, -- dds_phase_inc_step_size_out => open, -- idle_samples_out => open, -- dds_samples_out => open, -- phase_inc_out => open, -- phase_off_out => open, -- swap_sf_out => open, -- -- m_axis_aclk_in => m_axis_aclk, -- dds_pulse_data_out => dds_pulse_data_0, -- dds_pulse_dval_out => dds_pulse_dval_0, -- -- cmd_send_cnt_out => open, -- pipe_in_ch1_fifo_rden_cnt_out => open, -- dds_pulse_data_cnt_out => open, -- dds_done_out => open, -- -- trigger_mode_in => "00", -- 00 = internal, 01 = external, 10 = internal -- ext_trigger_in => '0', -- prog_us_tick_in => x"0000_0100", -- duration_ms_cnt_in => x"0000_0064", -- -- reset_in => reset -- ); i_fifo_0 : entity work.axis_data_fifo_32x32 port map ( s_axis_aclk => m_axis_aclk, s_axis_aresetn => reset_n(0), s_axis_tdata => dds_pulse_data_0, s_axis_tvalid => dds_pulse_dval_0, s_axis_tready => s_axis_tready_0, m_axis_tdata => m_axis_tdata_0, m_axis_tvalid => m_axis_tvalid_0, m_axis_tready => dds_pulse_data_word_tready_valid ); i_fifo_1 : entity work.axis_data_fifo_32x32 port map ( s_axis_aclk => m_axis_aclk, s_axis_aresetn => reset_n(0), s_axis_tdata => dds_pulse_data_1, s_axis_tvalid => dds_pulse_dval_1, s_axis_tready => s_axis_tready_1, m_axis_tdata => m_axis_tdata_1, m_axis_tvalid => m_axis_tvalid_1, m_axis_tready => dds_pulse_data_word_tready_valid ); i_fifo_2 : entity work.axis_data_fifo_32x32 port map ( s_axis_aclk => m_axis_aclk, s_axis_aresetn => reset_n(0), s_axis_tdata => dds_pulse_data_2, s_axis_tvalid => dds_pulse_dval_2, s_axis_tready => s_axis_tready_2, m_axis_tdata => m_axis_tdata_2, m_axis_tvalid => m_axis_tvalid_2, m_axis_tready => dds_pulse_data_word_tready_valid ); i_fifo_3 : entity work.axis_data_fifo_32x32 port map ( s_axis_aclk => m_axis_aclk, s_axis_aresetn => reset_n(0), s_axis_tdata => dds_pulse_data_3, s_axis_tvalid => dds_pulse_dval_3, s_axis_tready => s_axis_tready_3, m_axis_tdata => m_axis_tdata_3, m_axis_tvalid => m_axis_tvalid_3, m_axis_tready => dds_pulse_data_word_tready_valid ); dds_pulse_data_word <= m_axis_tdata_3 & m_axis_tdata_2 & m_axis_tdata_1 & m_axis_tdata_0; dds_pulse_data_word_dval <= m_axis_tvalid_3 and m_axis_tvalid_2 and m_axis_tvalid_1 and m_axis_tvalid_0; dds_pulse_data_word_tready_valid <= '1' when dds_pulse_data_word_dval = '1' and dds_pulse_data_word_tready = '1' else '0'; -- this FIFO is actually 32K by 128 i_fifo_out : entity work.axis_data_fifo_512x128 port map ( s_axis_aclk => m_axis_aclk, s_axis_aresetn => reset_n(0), s_axis_tdata => dds_pulse_data_word, s_axis_tvalid => dds_pulse_data_word_dval, s_axis_tready => dds_pulse_data_word_tready, m_axis_tdata => m_axis_tdata_i, m_axis_tvalid => m_axis_tvalid_i, m_axis_tready => m_axis_tready_i ); i_util_upack2 : entity work.util_upack2 generic map ( NUM_OF_CHANNELS => 8, SAMPLES_PER_CHANNEL => 1, SAMPLE_DATA_WIDTH => 16 ) port map ( clk => m_axis_aclk, --input reset => reset, -- input enable_0 => fifo_en, -- input enable_1 => fifo_en, -- input enable_2 => fifo_en, -- input enable_3 => fifo_en, -- input enable_4 => fifo_en, -- input enable_5 => fifo_en, -- input enable_6 => fifo_en, -- input enable_7 => fifo_en, -- input enable_8 => '0', -- input enable_9 => '0', -- input enable_10 => '0', -- input enable_11 => '0', -- input enable_12 => '0', -- input enable_13 => '0', -- input enable_14 => '0', -- input enable_15 => '0', -- input enable_16 => '0', -- input enable_17 => '0', -- input enable_18 => '0', -- input enable_19 => '0', -- input enable_20 => '0', -- input enable_21 => '0', -- input enable_22 => '0', -- input enable_23 => '0', -- input enable_24 => '0', -- input enable_25 => '0', -- input enable_26 => '0', -- input enable_27 => '0', -- input enable_28 => '0', -- input enable_29 => '0', -- input enable_30 => '0', -- input enable_31 => '0', -- input enable_32 => '0', -- input enable_33 => '0', -- input enable_34 => '0', -- input enable_35 => '0', -- input enable_36 => '0', -- input enable_37 => '0', -- input enable_38 => '0', -- input enable_39 => '0', -- input enable_40 => '0', -- input enable_41 => '0', -- input enable_42 => '0', -- input enable_43 => '0', -- input enable_44 => '0', -- input enable_45 => '0', -- input enable_46 => '0', -- input enable_47 => '0', -- input enable_48 => '0', -- input enable_49 => '0', -- input enable_50 => '0', -- input enable_51 => '0', -- input enable_52 => '0', -- input enable_53 => '0', -- input enable_54 => '0', -- input enable_55 => '0', -- input enable_56 => '0', -- input enable_57 => '0', -- input enable_58 => '0', -- input enable_59 => '0', -- input enable_60 => '0', -- input enable_61 => '0', -- input enable_62 => '0', -- input enable_63 => '0', -- input fifo_rd_en => fifo_rd_en,-- input fifo_rd_valid => fifo_rd_valid , -- output fifo_rd_underflow => fifo_rd_underflow, -- output fifo_rd_data_0 => fifo_rd_data_0, -- fifo_rd_data_1 => fifo_rd_data_1, -- fifo_rd_data_2 => fifo_rd_data_2, -- fifo_rd_data_3 => fifo_rd_data_3, -- fifo_rd_data_4 => fifo_rd_data_4, -- fifo_rd_data_5 => fifo_rd_data_5, -- fifo_rd_data_6 => fifo_rd_data_6, -- fifo_rd_data_7 => fifo_rd_data_7, -- fifo_rd_data_8 => fifo_rd_data_8 , -- fifo_rd_data_9 => fifo_rd_data_9 , -- fifo_rd_data_10 => fifo_rd_data_10, -- fifo_rd_data_11 => fifo_rd_data_11, -- fifo_rd_data_12 => fifo_rd_data_12, -- fifo_rd_data_13 => fifo_rd_data_13, -- fifo_rd_data_14 => fifo_rd_data_14, -- fifo_rd_data_15 => fifo_rd_data_15, -- fifo_rd_data_16 => fifo_rd_data_16, -- fifo_rd_data_17 => fifo_rd_data_17, -- fifo_rd_data_18 => fifo_rd_data_18, -- fifo_rd_data_19 => fifo_rd_data_19, -- fifo_rd_data_20 => fifo_rd_data_20, -- fifo_rd_data_21 => fifo_rd_data_21, -- fifo_rd_data_22 => fifo_rd_data_22, -- fifo_rd_data_23 => fifo_rd_data_23, -- fifo_rd_data_24 => fifo_rd_data_24, -- fifo_rd_data_25 => fifo_rd_data_25, -- fifo_rd_data_26 => fifo_rd_data_26, -- fifo_rd_data_27 => fifo_rd_data_27, -- fifo_rd_data_28 => fifo_rd_data_28, -- fifo_rd_data_29 => fifo_rd_data_29, -- fifo_rd_data_30 => fifo_rd_data_30, -- fifo_rd_data_31 => fifo_rd_data_31, -- fifo_rd_data_32 => fifo_rd_data_32, -- fifo_rd_data_33 => fifo_rd_data_33, -- fifo_rd_data_34 => fifo_rd_data_34, -- fifo_rd_data_35 => fifo_rd_data_35, -- fifo_rd_data_36 => fifo_rd_data_36, -- fifo_rd_data_37 => fifo_rd_data_37, -- fifo_rd_data_38 => fifo_rd_data_38, -- fifo_rd_data_39 => fifo_rd_data_39, -- fifo_rd_data_40 => fifo_rd_data_40, -- fifo_rd_data_41 => fifo_rd_data_41, -- fifo_rd_data_42 => fifo_rd_data_42, -- fifo_rd_data_43 => fifo_rd_data_43, -- fifo_rd_data_44 => fifo_rd_data_44, -- fifo_rd_data_45 => fifo_rd_data_45, -- fifo_rd_data_46 => fifo_rd_data_46, -- fifo_rd_data_47 => fifo_rd_data_47, -- fifo_rd_data_48 => fifo_rd_data_48, -- fifo_rd_data_49 => fifo_rd_data_49, -- fifo_rd_data_50 => fifo_rd_data_50, -- fifo_rd_data_51 => fifo_rd_data_51, -- fifo_rd_data_52 => fifo_rd_data_52, -- fifo_rd_data_53 => fifo_rd_data_53, -- fifo_rd_data_54 => fifo_rd_data_54, -- fifo_rd_data_55 => fifo_rd_data_55, -- fifo_rd_data_56 => fifo_rd_data_56, -- fifo_rd_data_57 => fifo_rd_data_57, -- fifo_rd_data_58 => fifo_rd_data_58, -- fifo_rd_data_59 => fifo_rd_data_59, -- fifo_rd_data_60 => fifo_rd_data_60, -- fifo_rd_data_61 => fifo_rd_data_61, -- fifo_rd_data_62 => fifo_rd_data_62, -- fifo_rd_data_63 => fifo_rd_data_63, -- s_axis_valid => m_axis_tvalid_i,-- input , s_axis_ready => m_axis_tready_i,-- output , s_axis_data => m_axis_tdata_i -- output ); process begin wait for 200 ns; -- cmd_send_0 <= '1'; -- wait for 500 ns; -- dac_holdoff_0 <= '0'; wait until rising_edge(m_axis_aclk); dds_pulse_data_0 <= x"1111_2222"; dds_pulse_dval_0 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_0 <= x"3333_4444"; dds_pulse_dval_0 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_0 <= x"5555_6666"; dds_pulse_dval_0 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_0 <= x"7777_8888"; dds_pulse_dval_0 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_0 <= (others => '0'); dds_pulse_dval_0 <= '0'; wait until rising_edge(m_axis_aclk); dds_pulse_data_1 <= x"9999_aaaa"; dds_pulse_dval_1 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_1 <= x"bbbb_cccc"; dds_pulse_dval_1 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_1 <= x"dddd_eeee"; dds_pulse_dval_1 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_1 <= x"ffff_1234"; dds_pulse_dval_1 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_1 <= (others => '0'); dds_pulse_dval_1 <= '0'; wait until rising_edge(m_axis_aclk); dds_pulse_data_2 <= x"1122_3344"; dds_pulse_dval_2 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_2 <= x"5566_7788"; dds_pulse_dval_2 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_2 <= x"99aa_bbcc"; dds_pulse_dval_2 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_2 <= x"ddee_ff00"; dds_pulse_dval_2 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_2 <= (others => '0'); dds_pulse_dval_2 <= '0'; wait until rising_edge(m_axis_aclk); dds_pulse_data_3 <= x"0123_4567"; dds_pulse_dval_3 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_3 <= x"89ab_cdef"; dds_pulse_dval_3 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_3 <= x"fedc_ba98"; dds_pulse_dval_3 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_3 <= x"7654_3210"; dds_pulse_dval_3 <= '1'; wait until rising_edge(m_axis_aclk); dds_pulse_data_3 <= (others => '0'); dds_pulse_dval_3 <= '0'; wait for 500 ns; wait until rising_edge(m_axis_aclk); -- m_axis_tready_i <= '1'; wait; end process; end architecture behavior;