library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use std.textio.all; use ieee.std_logic_textio.all; Library xpm; use xpm.vcomponents.all; library unisim; use unisim.vcomponents.all; library work; entity axi_lite_traffic_gen is generic ( C_M_AXI_ADDR_WIDTH : integer := 32; C_M_AXI_DATA_WIDTH : integer := 32 ); port ( m_axi_aclk : in std_logic; m_axi_aresetn : in std_logic; -- Master Interface Write Address m_axi_awaddr : out std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0); m_axi_awprot : out std_logic_vector (2 downto 0); m_axi_awvalid : out std_logic; m_axi_awready : in std_logic; -- master interface write data m_axi_wdata : out std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0); m_axi_wstrb : out std_logic_vector (C_M_AXI_DATA_WIDTH/8-1 downto 0); m_axi_wvalid : out std_logic; m_axi_wready : in std_logic; -- master interface write response m_axi_bresp : in std_logic_vector (1 downto 0); m_axi_bvalid : in std_logic; m_axi_bready : out std_logic; -- master interface read address m_axi_araddr : out std_logic_vector (C_M_AXI_ADDR_WIDTH-1 downto 0); m_axi_arprot : out std_logic_vector (2 downto 0); m_axi_arvalid : out std_logic; m_axi_arready : in std_logic; -- master interface read data m_axi_rdata : in std_logic_vector (C_M_AXI_DATA_WIDTH-1 downto 0); m_axi_rresp : in std_logic_vector (1 downto 0); m_axi_rvalid : in std_logic; m_axi_rready : out std_logic; num_burst_cnt_out : out std_logic_vector(7 downto 0); xfer_en_out : out std_logic; xfer_done_in : in std_logic; dma_xfer_done_in : in std_logic; buffer_rdy_intr_in : in std_logic ); end entity axi_lite_traffic_gen; architecture impl of axi_lite_traffic_gen is procedure writeReg ( addr : in std_logic_vector(31 downto 0); wr_data : in std_logic_vector(31 downto 0); signal m_axi_aclk : in std_logic; signal awaddr : out std_logic_vector(31 downto 0); signal wdata : out std_logic_vector(31 downto 0); signal wstrb : out std_logic_vector( 3 downto 0); signal awvalid : out std_logic; signal wvalid : out std_logic; signal bready : out std_logic; signal awready : in std_logic; signal wready : in std_logic; signal bvalid : in std_logic; signal done : out std_logic ) is begin wait until rising_edge(m_axi_aclk); done <= '0'; awaddr <= addr; wdata <= wr_data; wstrb <= x"F"; wait until rising_edge(m_axi_aclk); awvalid <= '1'; wvalid <= '1'; bready <= '1'; wait until rising_edge(m_axi_aclk); wait until wready = '1' and awready = '1'; awvalid <= '0'; wvalid <= '0'; wait until bvalid = '1'; wait until rising_edge(m_axi_aclk); done <= '1'; wait until rising_edge(m_axi_aclk); done <= '0'; wait until rising_edge(m_axi_aclk); wait until rising_edge(m_axi_aclk); wait until rising_edge(m_axi_aclk); wait until rising_edge(m_axi_aclk); end procedure writeReg; procedure readReg ( addr : in std_logic_vector(31 downto 0); signal m_axi_aclk : in std_logic; signal araddr : out std_logic_vector(31 downto 0); signal rready : out std_logic; signal arvalid : out std_logic; signal arready : in std_logic; signal rvalid : in std_logic; signal rdata : in std_logic_vector(31 downto 0); signal rd_data : out std_logic_vector(31 downto 0); signal done : out std_logic ) is begin wait until rising_edge(m_axi_aclk); done <= '0'; araddr <= addr; wait until rising_edge(m_axi_aclk); rready <= '1'; arvalid <= '1'; wait until rising_edge(m_axi_aclk); wait until arready = '1'; wait until rising_edge(m_axi_aclk); arvalid <= '0'; -- wait until rising_edge(m_axi_aclk); wait until rvalid = '1'; wait until rising_edge(m_axi_aclk); rready <= '0'; rd_data <= rdata; done <= '1'; wait until rising_edge(m_axi_aclk); done <= '0'; wait until rising_edge(m_axi_aclk); wait until rising_edge(m_axi_aclk); wait until rising_edge(m_axi_aclk); wait until rising_edge(m_axi_aclk); end procedure readReg; signal m_axi_awaddr_i : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal m_axi_awvalid_i : std_logic := '0'; signal m_axi_wdata_i : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axi_wstrb_i : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal m_axi_wvalid_i : std_logic := '0'; signal m_axi_bready_i : std_logic := '0'; signal m_axi_araddr_i : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal m_axi_arvalid_i : std_logic := '0'; signal m_axi_rready_i : std_logic := '0'; signal read_complete : std_logic := '0'; signal read_complete_r : std_logic := '0'; signal rd_data : std_logic_vector(31 downto 0); signal write_complete : std_logic := '0'; signal write_complete_r : std_logic := '0'; signal num_burst_cnt : std_logic_vector(7 downto 0) := (others => '0'); signal xfer_en : std_logic := '0'; signal buffer_rdy_intr_r : std_logic; signal m_axi_awaddr_ii : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal m_axi_awvalid_ii : std_logic := '0'; signal m_axi_wdata_ii : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axi_wstrb_ii : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal m_axi_wvalid_ii : std_logic := '0'; signal m_axi_bready_ii : std_logic := '0'; signal s2mm_cmd_en : std_logic := '0'; begin m_axi_awaddr <= m_axi_awaddr_i when s2mm_cmd_en = '0' else m_axi_awaddr_ii; m_axi_awvalid <= m_axi_awvalid_i when s2mm_cmd_en = '0' else m_axi_awvalid_ii; m_axi_wdata <= m_axi_wdata_i when s2mm_cmd_en = '0' else m_axi_wdata_ii; m_axi_wstrb <= m_axi_wstrb_i when s2mm_cmd_en = '0' else m_axi_wstrb_ii; m_axi_wvalid <= m_axi_wvalid_i when s2mm_cmd_en = '0' else m_axi_wvalid_ii; m_axi_bready <= m_axi_bready_i when s2mm_cmd_en = '0' else m_axi_bready_ii; m_axi_araddr <= m_axi_araddr_i; m_axi_arvalid <= m_axi_arvalid_i; m_axi_rready <= m_axi_rready_i; m_axi_awprot <= "000"; m_axi_arprot <= "000"; num_burst_cnt_out <= num_burst_cnt; xfer_en_out <= xfer_en; process variable my_line : line; begin wait for 10 us; ---------------------- write(my_line, string'("reading REG_VERSION at 0x00")); -- read REG_VERSION writeline(output, my_line); readReg(x"0000_0000", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); write(my_line, string'("reading REG_CONFIG at 0x0C")); -- read REG_CONFIG writeline(output, my_line); readReg(x"0000_000C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); write(my_line, string'("reading REG_PPS_IRQ_MASK at 0x10")); -- read REG_PPS_IRQ_MASK writeline(output, my_line); readReg(x"0000_0010", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); write(my_line, string'("reading REG_FPGA_INFO at 0x1C")); -- read REG_FPGA_INFO writeline(output, my_line); readReg(x"0000_001C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); wait for 5 us; write(my_line, string'("reading REG_STATUS1 at 0x54")); -- read REG_STATUS1 writeline(output, my_line); readReg(x"0000_0054", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); write(my_line, string'("reading REG_STATUS2 at 0x58")); -- read REG_STATUS2 writeline(output, my_line); readReg(x"0000_0058", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); write(my_line, string'("reading REG_STATUS3 at 0x5C")); -- read REG_STATUS3 writeline(output, my_line); readReg(x"0000_005C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); wait for 10 us; write(my_line, string'("writing REG_RSTN at 0x040")); -- write REG_RSTN writeline(output, my_line); writeReg(x"0000_0040", x"0000_0003", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); wait for 5 us; write(my_line, string'("writing REG_TPL_DESCRIPTOR_1 at 0x240")); -- write REG_TPL_DESCRIPTOR_1 writeline(output, my_line); writeReg(x"0000_0240", x"0401_0408", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); write(my_line, string'("writing REG_TPL_DESCRIPTOR_2 at 0x244")); -- write REG_TPL_DESCRIPTOR_2 writeline(output, my_line); writeReg(x"0000_0244", x"0000_1010", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); ----sending user data wait for 1 us; write(my_line, string'("writing REG_USR_CNTRL_3 at 0x420")); -- write REG_USR_CNTRL_3 writeline(output, my_line); writeReg(x"0000_0420", x"0200_8010", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); wait for 1 us; write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write CHAN 0 - REG_CHAN_CNTRL_7 -- input data (DMA) writeline(output, my_line); writeReg(x"0000_0418", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x458")); -- write CHAN 1 - write REG_CHAN_CNTRL_7 -- input data (DMA) writeline(output, my_line); writeReg(x"0000_0458", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x498")); -- write CHAN 2 - write REG_CHAN_CNTRL_7 -- input data (DMA) writeline(output, my_line); writeReg(x"0000_0498", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x4D8")); -- write CHAN 3 - write REG_CHAN_CNTRL_7 -- input data (DMA) writeline(output, my_line); writeReg(x"0000_04D8", x"0000_0002", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- wait for 1 us; -- -- write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write REG_CHAN_CNTRL_7 - inverted pn15 -- writeline(output, my_line); -- writeReg(x"0000_0418", x"0000_0005", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- write(my_line, string'("writing REG_CHAN_CNTRL_5 at 0x410")); -- write REG_CHAN_CNTRL_5 -- writeline(output, my_line); -- writeReg(x"0000_0410", x"DEAD_BEEF", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- wait for 1 us; -- -- write(my_line, string'("writing REG_CHAN_CNTRL_7 at 0x418")); -- write REG_CHAN_CNTRL_7 -- pattern (SED) -- writeline(output, my_line); -- writeReg(x"0000_0418", x"0000_0001", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- write(my_line, string'("reading TDFV at 0x0C")); -- read Transmit Data FIFO Vacancy -- writeline(output, my_line); -- readReg(x"0003_000C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); -- -- write(my_line, string'("reading RDFO at 0x1C")); -- Receive Data FIFO Occupancy -- writeline(output, my_line); -- readReg(x"0003_001C", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); -- -- write(my_line, string'("reading RLR at 0x24")); -- Receive Length Register -- writeline(output, my_line); -- readReg(x"0003_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); -- -- -- -- wait for 1 us; -- write(my_line, string'("writing (TDFR) at 0x8")); --Transmit Data FIFO Reset -- writeline(output, my_line); -- writeReg(x"0000_0008", x"0000_00A5", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- -- -- wait for 1 us; -- write(my_line, string'("-----------------------------------")); -- writeline(output, my_line); -- write(my_line, string'("writing TDFD at 0x10")); -- Transmit Data FIFO 32-bit Wide Data Write Port -- writeline(output, my_line); -- writeReg(x"0000_0010", x"dead_beef", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- write(my_line, string'("writing TLR at 0x14")); --MM2S Source Address. Lower 32 bits of address. -- writeline(output, my_line); -- writeReg(x"0000_0014", x"0000_0001", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- wait for 1 us; -- write(my_line, string'("reading ISR at 0x00")); -- read Interrupt Status Register -- writeline(output, my_line); -- readReg(x"0003_0000", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); -- -- wait for 500 ns; -- write(my_line, string'("reading RLR at 0x24")); -- read Receive Length Register -- writeline(output, my_line); -- readReg(x"0000_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); -- -- write(my_line, string'("reading RLR at 0x20")); -- read Receive Data FIFO 32-bit Wide Data Read Port -- writeline(output, my_line); -- readReg(x"0000_0020", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); -- -- write(my_line, string'("reading RLR at 0x24")); -- read Receive Length Register -- writeline(output, my_line); -- readReg(x"0000_0024", m_axi_aclk, m_axi_araddr_i, m_axi_rready_i, m_axi_arvalid_i, m_axi_arready, m_axi_rvalid, m_axi_rdata, rd_data, read_complete); -- -- write(my_line, string'("writing MM2S_SA_MSB at 0x1C")); -- MM2S Source Address. Upper 32 bits of address. -- writeline(output, my_line); -- writeReg(x"0000_001C", x"0000_0000", m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- -- dma transfer starts here (1) -- write(my_line, string'("writing MM2S_LENGTH at 0x28")); -- MM2S Transfer Length (Bytes) -- writeline(output, my_line); -- writeReg(x"0000_0028", conv_std_logic_vector(16, 32), m_axi_aclk, m_axi_awaddr_i, m_axi_wdata_i, m_axi_wstrb_i, m_axi_awvalid_i, m_axi_wvalid_i, m_axi_bready_i, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- 2048+8 ==> 8 is packet length -- -- wait until dma_xfer_done_in = '1'; -- wait for 50 us; wait; -- wait here forever end process; -- process -- variable my_line : line; -- begin ---- if(rising_edge(m_axi_aclk)) then ---- buffer_rdy_intr_r <= buffer_rdy_intr_in; ---- if(buffer_rdy_intr_in = '1' and buffer_rdy_intr_r = '0') then -- -- -- -- dma the data **********From Stream to Memory **************** -- wait until buffer_rdy_intr_in = '1'; -- s2mm_cmd_en <= '1'; -- wait for 100 ns; -- write(my_line, string'("-----------------------------------")); -- writeline(output, my_line); -- -- -- 0x34 S2MM DMA Status register -- -- -- write(my_line, string'("writing S2MM_DMACR at 0x30")); -- S2MM DMA Control register -- writeline(output, my_line); -- writeReg(x"0000_0030", x"0000_7001", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- write(my_line, string'("writing S2MM_DA at 0x48")); -- S2MM Destination Address. Lower 32 bit address. -- writeline(output, my_line); -- writeReg(x"0000_0048", x"0000_0000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- write(my_line, string'("writing S2MM_DA_MSB at 0x4C")); -- S2MM Destination Address. Upper 32 bit address. -- writeline(output, my_line); -- writeReg(x"0000_004C", x"0000_0000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- -- dma transfer starts here -- write(my_line, string'("writing S2MM_LENGTH at 0x58")); -- S2MM Buffer Length (Bytes) -- writeline(output, my_line); -- writeReg(x"0000_0058", x"0000_0800", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- wait for 100 ns; -- -- dma transfer starts here -- write(my_line, string'("writing S2MM_LENGTH at 0x58")); -- writeline(output, my_line); -- writeReg(x"0000_0058", x"0000_1000", m_axi_aclk, m_axi_awaddr_ii, m_axi_wdata_ii, m_axi_wstrb_ii, m_axi_awvalid_ii, m_axi_wvalid_ii, m_axi_bready_ii, m_axi_awready, m_axi_wready, m_axi_bvalid, write_complete); -- -- -- wait for 100 ns; -- s2mm_cmd_en <= '0'; -- -- wait; -- wait here forever -- end process; process(m_axi_aclk) variable my_line : line; begin read_complete_r <= read_complete; write_complete_r <= write_complete; if(read_complete = '1' and read_complete_r = '0') then write(my_line, string'("Read Complete: ")); hwrite(my_line, rd_data); writeline(output, my_line); end if; if(write_complete = '1' and write_complete_r = '0') then write(my_line, string'("Write Complete: ")); writeline(output, my_line); end if; end process; end architecture impl;