library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity dds_cmd_gen is generic ( SIM_ENABLED : boolean := FALSE ); port( clk_in : in std_logic; cmd_idx_in : in std_logic_vector( 2 downto 0); cmd_send_in : in std_logic; vio_reserv1_in : in std_logic_vector(31 downto 0); vio_dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0); vio_dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0); vio_idle_samples_in : in std_logic_vector(31 downto 0); vio_dds_samples_in : in std_logic_vector(31 downto 0); vio_phase_inc_in : in std_logic_vector(31 downto 0); vio_phase_off_in : in std_logic_vector(31 downto 0); vio_swap_sf_in : in std_logic_vector(31 downto 0); fifo_rd_clk_in : in std_logic; fifo_rd_data_out : out std_logic_vector(31 downto 0); fifo_rd_dval_out : out std_logic; fifo_rd_rd_en_in : in std_logic; fifo_rd_empty_out : out std_logic; rst_in : in std_logic ); end entity dds_cmd_gen; architecture imp of dds_cmd_gen is signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0'); signal fifo_wr_en_r : std_logic := '0'; signal cmd_idx_r : integer range 0 to 4 := 0; signal cmd_send_r : std_logic := '0'; type fsm_state is (IDLE, SEND, DONE); signal state_r : fsm_state := IDLE; signal state_cnt_r : integer := 0; type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0); type dds_command_list is array (integer range <>) of array_32b_type; signal dds_command_set : dds_command_list(0 to 4) := ( -- WFM 0 -- FREQUENCY SWEEP (UP-SWEEP) 0 => (x"00000000", --RESERVED1 x"00000000", --DDS_PHASE_INC_DWELL_TIME x"00010C6F", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) = 68719 = 0x00010C6F x"00000000", --IDLE_SAMPLES x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2 x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD x"00000000", --PHASE_OFF x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 ), -- WFM 1 -- FREQUENCY SWEEP (DOWN-SWEEP) 1 => (x"00000000", --RESERVED1 x"00000000", --DDS_PHASE_INC_DWELL_TIME x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) x"00000000", --IDLE_SAMPLES x"000004E2", --DDS_SAMPLES (~5 us) x"0624DD2F", --PHASE_INC (~6 MHz) x"00000000", --PHASE_OFF x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 ), -- WFM 2 -- CW TONE 2 => (x"00000000", --RESERVED1 x"00000000", --DDS_PHASE_INC_DWELL_TIME x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone) x"00000000", --IDLE_SAMPLES x"000004E2", --DDS_SAMPLES (~5 us) -- x"000FFFFF", --DDS_SAMPLES (~5 us) x"0624DD2F", --PHASE_INC (~6 MHz) x"00000000", --PHASE_OFF x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 ), -- WFM 3 -- FREQUENCY SWEEP (DOWN-SWEEP) 3 => (x"00000000", --RESERVED1 x"00000000", --DDS_PHASE_INC_DWELL_TIME x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) x"00000000", --IDLE_SAMPLES x"000004E2", --DDS_SAMPLES (~5 us) x"0624DD2F", --PHASE_INC (~6 MHz) x"00000000", --PHASE_OFF x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 ), -- WFM 4 -- ?????? 4 => (x"00000000", --RESERVED1 x"00000000", --DDS_PHASE_INC_DWELL_TIME x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) x"00000000", --IDLE_SAMPLES x"00000000", --DDS_SAMPLES (~5 us) x"00000000", --PHASE_INC (~6 MHz) x"00000000", --PHASE_OFF x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0 ) ); signal test_state_r : std_logic_vector(1 downto 0) := (others => '0'); begin dds_command_set(4)(0) <= vio_reserv1_in; dds_command_set(4)(1) <= vio_dds_phase_inc_dwell_time_in; dds_command_set(4)(2) <= vio_dds_phase_inc_step_size_in; dds_command_set(4)(3) <= vio_idle_samples_in; dds_command_set(4)(4) <= vio_dds_samples_in; dds_command_set(4)(5) <= vio_phase_inc_in; dds_command_set(4)(6) <= vio_phase_off_in; dds_command_set(4)(7) <= vio_swap_sf_in; process(clk_in) begin if (rising_edge(clk_in)) then if (rst_in = '1') then cmd_idx_r <= 0; cmd_send_r <= '0'; fifo_wr_en_r <= '0'; state_cnt_r <= 0; state_r <= IDLE; else cmd_send_r <= cmd_send_in; fifo_wr_en_r <= '0'; case (state_r) is when IDLE => if (cmd_send_in = '1' and cmd_send_r = '0') then cmd_idx_r <= conv_integer(unsigned(cmd_idx_in)); state_cnt_r <= 0; state_r <= SEND; else state_r <= IDLE; end if; when SEND => if (state_cnt_r = 8) then state_r <= DONE; else fifo_wr_data_r <= dds_command_set(cmd_idx_r)(state_cnt_r); fifo_wr_en_r <= '1'; state_cnt_r <= state_cnt_r + 1; state_r <= SEND; end if; when DONE => state_r <= IDLE; when others => state_r <= IDLE; end case; end if; end if; end process; test_state_r <= "00" when state_r = IDLE else "01" when state_r = SEND else "10" when state_r = DONE else "11"; sim_false : if (SIM_ENABLED = FALSE) generate i_ila_1 : entity work.ila_2 port map ( clk => clk_in, probe0 => test_state_r, -- 2 probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4 probe2 => fifo_wr_data_r, -- 32 probe3(0) => fifo_wr_en_r, -- 1 probe4(0) => cmd_send_in, -- 1 probe5(0) => cmd_send_r -- 1 ); end generate sim_false; i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1 port map( wr_clk => clk_in, din => fifo_wr_data_r, wr_en => fifo_wr_en_r, full => open, overflow => open, rd_clk => fifo_rd_clk_in, dout => fifo_rd_data_out, valid => fifo_rd_dval_out, rd_en => fifo_rd_rd_en_in, empty => fifo_rd_empty_out, underflow => open, prog_full => open, wr_rst_busy => open, rd_rst_busy => open, srst => rst_in ); end architecture imp;