xilinx.com user dds_pulse_wrapper 1.0 m_axis_out TDATA m_axis_tdata_out TVALID m_axis_tvalid_out TREADY m_axis_tready_in xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL dds_pulse_wrapper xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 4288e600 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL dds_pulse_wrapper xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 4288e600 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c12c7cc7 clk_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aclk_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tdata_out out 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rst_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation SIM_ENABLED Sim Enabled FALSE FPGA_REVISION_DATE Fpga Revision Date 0x09162023 xilinx_anylanguagesynthesis_view_fileset ../ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci xci CELL_NAME_i_dds_pulse_2x_top/i_pulse_adder1 ../ip/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci xci CELL_NAME_i_dds_pulse_2x_top/i_pulse1_fifo ../ip/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci xci CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1 ../ip/dds_latency10/dds_latency10.xci xci CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds ../ip/addsub/addsub.xci xci CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_addsub src/ila_0/ila_0.xci xci CELL_NAME_sim_false3.i_ila_2 ../ip/axis_data_fifo_512x128/axis_data_fifo_512x128.xci xci CELL_NAME_i_fifo src/ila_3/ila_3.xci xci CELL_NAME_sim_false2.i_ila_3 src/ila_4/ila_4.xci xci CELL_NAME_sim_false1.i_ila_4 src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci xci CELL_NAME_i_dds_cmd_gen/i_pipe_in_ch1_fifo src/ila_2/ila_2.xci xci CELL_NAME_i_dds_cmd_gen/sim_false.i_ila_1 ../ip/vio_0/vio_0.xci xci CELL_NAME_sim_false.i_vio_0 dds_cmd_gen.vhd vhdlSource dds_pulse_2x_top.vhd vhdlSource dds_pulse_gen.vhd vhdlSource dds_pulse_wrapper.vhd vhdlSource CHECKSUM_bb6db1b1 xilinx_anylanguagesynthesis_xilinx_com_ip_c_addsub_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../ip/adder_16signed_16signed_latency2/adder_16signed_16signed_latency2.xci xci CELL_NAME_i_dds_pulse_2x_top/i_pulse_adder1 ../ip/sfifo_32b_1024_pf992_latency1/sfifo_32b_1024_pf992_latency1.xci xci CELL_NAME_i_dds_pulse_2x_top/i_pulse1_fifo ../ip/mult_16signed_x_16unsigned_latency3/mult_16signed_x_16unsigned_latency3.xci xci CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_mult1 ../ip/dds_latency10/dds_latency10.xci xci CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_dds ../ip/addsub/addsub.xci xci CELL_NAME_i_dds_pulse_2x_top/i_dds_pulse1_gen/i_addsub src/ila_0/ila_0.xci xci CELL_NAME_sim_false3.i_ila_2 ../ip/axis_data_fifo_512x128/axis_data_fifo_512x128.xci xci CELL_NAME_i_fifo src/ila_3/ila_3.xci xci CELL_NAME_sim_false2.i_ila_3 src/ila_4/ila_4.xci xci CELL_NAME_sim_false1.i_ila_4 src/afifo_32b_1024_pf512_latency1/afifo_32b_1024_pf512_latency1.xci xci CELL_NAME_i_dds_cmd_gen/i_pipe_in_ch1_fifo src/ila_2/ila_2.xci xci CELL_NAME_i_dds_cmd_gen/sim_false.i_ila_1 ../ip/vio_0/vio_0.xci xci CELL_NAME_sim_false.i_vio_0 dds_cmd_gen.vhd vhdlSource dds_pulse_2x_top.vhd vhdlSource dds_pulse_gen.vhd vhdlSource dds_pulse_wrapper.vhd vhdlSource xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_c_addsub_12_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fifo_generator_13_2__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dds_compiler_6_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_mult_gen_12_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset xilinx_xpgui_view_fileset xgui/dds_pulse_wrapper_v1_0.tcl tclSource CHECKSUM_c12c7cc7 XGUI_VERSION_2 dds_pulse_wrapper_v1_0 SIM_ENABLED Sim Enabled FALSE Component_Name dds_pulse_wrapper_v1_0 FPGA_REVISION_DATE Fpga Revision Date 0x09162023 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /UserIP dds_pulse_wrapper_v1_0 package_project XPM_CDC XPM_FIFO XPM_MEMORY 15 2023-09-17T19:46:14Z 2022.2