library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity axis_mux_chan_sel is
  port ( 
    aselect_in                : in std_logic_vector(   1 downto 0);

    cmac_0_tdata_in           : in  std_logic_vector(127 downto 0);
    cmac_0_tvalid_in          : in  std_logic;
    cmac_0_tready_out         : out std_logic;

    cmac_4_tdata_in           : in  std_logic_vector(127 downto 0);
    cmac_4_tvalid_in          : in  std_logic;
    cmac_4_tready_out         : out std_logic;

    m_axis_tdata_out          : out std_logic_vector(255 downto 0);
    m_axis_tvalid_out         : out std_logic;
    m_axis_tready_in          : in  std_logic
    );
end entity axis_mux_chan_sel;

architecture imp of axis_mux_chan_sel is

begin

--                                        adc_chan1_s3                  adc_chan0_s3                 adc_chan1_s2                    adc_chan0_s2               adc_chan1_s1                     adc_chan0_s1            adc_chan1_s0                  adc_chan0_s0
  m_axis_tdata_out  <= cmac_4_tdata_in(127 downto 96) & cmac_0_tdata_in(127 downto 96) & cmac_4_tdata_in(95 downto 64) & cmac_0_tdata_in(95 downto 64) & cmac_4_tdata_in(63 downto 32) & cmac_0_tdata_in(63 downto 32) & cmac_4_tdata_in(31 downto 0) & cmac_0_tdata_in(31 downto 0) when aselect_in = "00" else   
                       x"FFFF_0000"                   & cmac_0_tdata_in(127 downto 96) & x"FFFF_0000"                  & cmac_0_tdata_in(95 downto 64) & x"FFFF_0000"                  & cmac_0_tdata_in(63 downto 32) & x"FFFF_0000"                 & cmac_0_tdata_in(31 downto 0) when aselect_in = "01" else    
                       cmac_4_tdata_in(127 downto 96) & x"FFFF_0000"                   & cmac_4_tdata_in(95 downto 64) & x"FFFF_0000"                  & cmac_4_tdata_in(63 downto 32) & x"FFFF_0000"                  & cmac_4_tdata_in(31 downto 0) & x"FFFF_0000";   
     
 
  m_axis_tvalid_out <= cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else 
                       cmac_0_tvalid_in                      when aselect_in = "01" else
                       cmac_4_tvalid_in                      when aselect_in = "10" else
                       '0';
    
  cmac_0_tready_out  <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else 
                        m_axis_tready_in and cmac_0_tvalid_in                      when aselect_in = "01" else '0';
                        
  cmac_4_tready_out  <= m_axis_tready_in and cmac_0_tvalid_in and cmac_4_tvalid_in when aselect_in = "00" else 
                        m_axis_tready_in and cmac_4_tvalid_in                      when aselect_in = "10" else '0';

end imp;