xilinx.com user dig_iq_decoder 1.0 m_axis TDATA m_axis_tdata TVALID m_axis_tvalid s_axis TDATA s_axis_tdata TVALID s_axis_tvalid aresetn RST aresetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF m_axis:s_axis ASSOCIATED_RESET aresetn xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL dig_iq_decoder xilinx_anylanguagesynthesis_view_fileset viewChecksum a3fc45a8 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL dig_iq_decoder xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum b952dd62 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f64a5dae aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation select_12b in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 239 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tdata out 319 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset dig_iq_decoder_ooc.xdc xdc USED_IN_out_of_context dig_iq_decoder.vhd vhdlSource CHECKSUM_b952dd62 xilinx_anylanguagebehavioralsimulation_view_fileset dig_iq_decoder.vhd vhdlSource xilinx_xpgui_view_fileset xgui/dig_iq_decoder_v1_0.tcl tclSource CHECKSUM_f64a5dae XGUI_VERSION_2 dig_iq_decoder_v1_0 Component_Name dig_iq_decoder_v1_0 versal zynq virtexuplus virtexuplusHBM zynquplus kintexu /UserIP dig_iq_decoder_v1_0 package_project 2 2021-06-22T17:47:25Z c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_decoder 2020.2