----------------------------------------------------------------------------------
-- Company: 
-- Engineer:    Jason M Blevins
-- 
-- Create Date: 01/05/2026 11:59:12 AM
-- Design Name: 
-- Module Name: eth_flowctrl_rx - behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;

entity eth_flowctrl_rx is
  Port (
    clk                 : in STD_LOGIC;
    resetn              : in STD_LOGIC;
    rx_pause            : in STD_LOGIC;
    rx_pause_quanta8    : in STD_LOGIC_VECTOR(15 downto 0);
    rx_pause_cnt        : out std_logic_vector(31 downto 0);
    pause               : out STD_LOGIC
    );
end eth_flowctrl_rx;

architecture behavioral of eth_flowctrl_rx is

  signal pause_r          : std_logic := '0';
  signal cnt_r            : unsigned(15 downto 0) := (others => '0');
  signal rx_pause_cnt_r   : unsigned(31 downto 0) := (others => '0');

begin

  pause         <= pause_r;
  rx_pause_cnt  <= std_logic_vector(rx_pause_cnt_r);

  process(clk)
  begin
    if(rising_edge(clk))then 
      if(resetn = '0')then
        cnt_r           <= (others => '0');
        pause_r         <= '0';
        rx_pause_cnt_r  <= (others => '0');
      else
        if(rx_pause = '1')then
          rx_pause_cnt_r  <= rx_pause_cnt_r +1;
          cnt_r           <= unsigned(rx_pause_quanta8);
          if(unsigned(rx_pause_quanta8) = 0)then
            pause_r <= '0';
          else
            pause_r <= '1';
          end if;
        else
          if(cnt_r > 0)then
            cnt_r <= cnt_r -1;
          end if;
          if(cnt_r = 1)then
            pause_r <= '0';
          end if;
        end if;         
      end if;
    end if;
  end process;


end behavioral;