xilinx.com user iq_240b_to_512b 1.0 s_axis TDATA s_axis_tdata 239 0 TVALID s_axis_tvalid TDATA_NUM_BYTES 30 TDEST_WIDTH 0 TID_WIDTH 0 TUSER_WIDTH 0 HAS_TREADY 0 HAS_TSTRB 0 HAS_TKEEP 0 HAS_TLAST 0 FREQ_HZ 195312500 PHASE 0.0 LAYERED_METADATA undef m_axis TVALID m_axis_tvalid TREADY m_axis_tready TDATA m_axis_tdata 511 0 TDATA_NUM_BYTES 64 TDEST_WIDTH 0 TID_WIDTH 0 TUSER_WIDTH 0 HAS_TREADY 1 HAS_TSTRB 0 HAS_TKEEP 0 HAS_TLAST 0 FREQ_HZ 195312500 PHASE 0.0 LAYERED_METADATA undef CLK.ACLK CLK aclk FREQ_HZ 195312500 FREQ_TOLERANCE_HZ 0 PHASE 0.0 ASSOCIATED_BUSIF s_axis:m_axis ASSOCIATED_RESET aresetn RST.ARESETN RST aresetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL iq_240b_to_512b xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_axis_demux_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_axis_mux_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum caff039b xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL iq_240b_to_512b xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_axis_demux_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_axis_mux_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 79335991 xilinx_implementation Implementation :vivado.xilinx.com:implementation iq_240b_to_512b xilinx_implementation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_implementation_xilinx_com_user_axis_demux_1_0__ref_view_fileset xilinx_implementation_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_implementation_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset xilinx_implementation_xilinx_com_user_axis_mux_1_0__ref_view_fileset xilinx_implementation_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset xilinx_implementation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_implementation_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset xilinx_implementation_view_fileset viewChecksum dfd0a51f xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 141a36c4 aclk in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tdata out 511 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation overflow out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 239 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tvalid in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sel_12b_16bn in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset src/iq_240b_to_512b_axis_data_fifo_0_0/iq_240b_to_512b_axis_data_fifo_0_0.xci xci IMPORTED_FILE CELL_NAME_axis_data_fifo_0 src/iq_240b_to_512b_axis_demux_16b_12b_iq_0/iq_240b_to_512b_axis_demux_16b_12b_iq_0.xci xci IMPORTED_FILE CELL_NAME_axis_demux_16b_12b_iq src/iq_240b_to_512b_xlslice_0_0/iq_240b_to_512b_xlslice_0_0.xci xci IMPORTED_FILE CELL_NAME_xlslice_0 src/iq_240b_to_512b_iq_decoder_12b_16b_0/iq_240b_to_512b_iq_decoder_12b_16b_0.xci xci IMPORTED_FILE CELL_NAME_iq_decoder_12b_16b src/iq_240b_to_512b_axis_mux_16b_12b_iq_0/iq_240b_to_512b_axis_mux_16b_12b_iq_0.xci xci IMPORTED_FILE CELL_NAME_axis_mux_16b_12b_iq src/iq_240b_to_512b_axis_register_slice_28B_0/iq_240b_to_512b_axis_register_slice_28B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_28B src/iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0/iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0.xci xci IMPORTED_FILE CELL_NAME_axis_dwidth_conv_40B_to_64B src/iq_240b_to_512b_overflow_detect_0/iq_240b_to_512b_overflow_detect_0.xci xci IMPORTED_FILE CELL_NAME_overflow_detect src/iq_240b_to_512b_axis_register_slice_40B_0/iq_240b_to_512b_axis_register_slice_40B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_40B src/iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0/iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0.xci xci IMPORTED_FILE CELL_NAME_axis_dwidth_conv_28B_to_64B src/iq_240b_to_512b_axis_register_slice_64B_0/iq_240b_to_512b_axis_register_slice_64B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_64B src/iq_240b_to_512b_ooc.xdc xdc IMPORTED_FILE SCOPED_TO_REF_iq_240b_to_512b USED_IN_out_of_context src/iq_240b_to_512b.vhd vhdlSource CHECKSUM_9f90b0d1 IMPORTED_FILE xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_axis_demux_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_axis_mux_1_0__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset src/iq_240b_to_512b_axis_data_fifo_0_0/iq_240b_to_512b_axis_data_fifo_0_0.xci xci IMPORTED_FILE CELL_NAME_axis_data_fifo_0 src/iq_240b_to_512b_axis_demux_16b_12b_iq_0/iq_240b_to_512b_axis_demux_16b_12b_iq_0.xci xci IMPORTED_FILE CELL_NAME_axis_demux_16b_12b_iq src/iq_240b_to_512b_xlslice_0_0/iq_240b_to_512b_xlslice_0_0.xci xci IMPORTED_FILE CELL_NAME_xlslice_0 src/iq_240b_to_512b_iq_decoder_12b_16b_0/iq_240b_to_512b_iq_decoder_12b_16b_0.xci xci IMPORTED_FILE CELL_NAME_iq_decoder_12b_16b src/iq_240b_to_512b_axis_mux_16b_12b_iq_0/iq_240b_to_512b_axis_mux_16b_12b_iq_0.xci xci IMPORTED_FILE CELL_NAME_axis_mux_16b_12b_iq src/iq_240b_to_512b_axis_register_slice_28B_0/iq_240b_to_512b_axis_register_slice_28B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_28B src/iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0/iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0.xci xci IMPORTED_FILE CELL_NAME_axis_dwidth_conv_40B_to_64B src/iq_240b_to_512b_overflow_detect_0/iq_240b_to_512b_overflow_detect_0.xci xci IMPORTED_FILE CELL_NAME_overflow_detect src/iq_240b_to_512b_axis_register_slice_40B_0/iq_240b_to_512b_axis_register_slice_40B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_40B src/iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0/iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0.xci xci IMPORTED_FILE CELL_NAME_axis_dwidth_conv_28B_to_64B src/iq_240b_to_512b_axis_register_slice_64B_0/iq_240b_to_512b_axis_register_slice_64B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_64B sim/iq_240b_to_512b.vhd vhdlSource IMPORTED_FILE xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_axis_demux_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_axis_mux_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset xilinx_implementation_view_fileset src/iq_240b_to_512b_axis_register_slice_28B_0/iq_240b_to_512b_axis_register_slice_28B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_28B src/iq_240b_to_512b_axis_register_slice_40B_0/iq_240b_to_512b_axis_register_slice_40B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_40B src/iq_240b_to_512b_axis_register_slice_64B_0/iq_240b_to_512b_axis_register_slice_64B_0.xci xci IMPORTED_FILE CELL_NAME_axis_register_slice_64B xilinx_implementation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset xilinx_implementation_xilinx_com_user_axis_demux_1_0__ref_view_fileset xilinx_implementation_xilinx_com_ip_xlslice_1_0__ref_view_fileset xilinx_implementation_xilinx_com_user_dig_iq_decoder_1_0__ref_view_fileset xilinx_implementation_xilinx_com_user_axis_mux_1_0__ref_view_fileset xilinx_implementation_xilinx_com_ip_axis_register_slice_1_1__ref_view_fileset xilinx_implementation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_implementation_xilinx_com_ip_axis_subset_converter_1_1__ref_view_fileset xilinx_xpgui_view_fileset xgui/iq_240b_to_512b_v1_0.tcl tclSource CHECKSUM_141a36c4 XGUI_VERSION_2 iq_240b_to_512b Component_Name iq_240b_to_512b_v1_0 virtexuplus zynquplus /UserIP iq_240b_to_512b IPI 2 2024-01-24T16:35:31Z 2023.1