xilinx.com user dig_iq_encoder 1.0 m_axis TDATA m_axis_tdata TVALID m_axis_tvalid TREADY m_axis_tready s_axis TDATA s_axis_tdata TVALID s_axis_tvalid TREADY s_axis_tready aresetn RST aresetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF m_axis:s_axis ASSOCIATED_RESET aresetn FREQ_HZ xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL dig_iq_encoder xilinx_anylanguagesynthesis_view_fileset viewChecksum b68be7df xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL dig_iq_encoder xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 5aaee39c xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f64a5dae aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 223 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tdata out 239 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset dig_iq_encoder_ooc.xdc xdc USED_IN_out_of_context dig_iq_encoder.vhd vhdlSource CHECKSUM_5aaee39c xilinx_anylanguagebehavioralsimulation_view_fileset dig_iq_encoder.vhd vhdlSource xilinx_xpgui_view_fileset xgui/dig_iq_encoder_v1_0.tcl tclSource CHECKSUM_f64a5dae XGUI_VERSION_2 dig_iq_encoder_v1_0 Component_Name dig_iq_encoder_v1_0 versal zynq virtexuplus virtexuplusHBM zynquplus kintexu /UserIP dig_iq_encoder_v1_0 package_project 3 2024-06-11T17:48:40Z c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder c:/Projects/dig_iq_2x_u200/ip_repo/dig_iq_encoder 2023.1