xilinx.com user axis_demux 1.0 m0_axis TDATA m0_axis_tdata TVALID m0_axis_tvalid TREADY m0_axis_tready m1_axis TDATA m1_axis_tdata TVALID m1_axis_tvalid TREADY m1_axis_tready s_axis TDATA s_axis_tdata TVALID s_axis_tvalid TREADY s_axis_tready aresetn RST aresetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF m0_axis:m1_axis:s_axis ASSOCIATED_RESET aresetn xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axis_demux xilinx_anylanguagesynthesis_view_fileset viewChecksum 57ba02cc xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axis_demux xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 16ec46fd xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c6faabd4 aclk in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aselect in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m0_axis_tdata out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m0_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m0_axis_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 m1_axis_tdata out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m1_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m1_axis_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 DWIDTH Dwidth 512 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axis_demux_ooc.xdc xdc USED_IN_out_of_context axis_demux.vhd vhdlSource CHECKSUM_16ec46fd xilinx_anylanguagebehavioralsimulation_view_fileset axis_demux.vhd vhdlSource xilinx_xpgui_view_fileset xgui/axis_demux_v1_0.tcl tclSource CHECKSUM_c6faabd4 XGUI_VERSION_2 axis_demux_v1_0 DWIDTH DWIDTH 512 Component_Name axis_demux_v1_0 versal zynq virtexuplus virtexuplusHBM zynquplus kintexu /UserIP axis_demux_v1_0 package_project 2 2021-06-22T18:00:02Z c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux c:/Projects/dig_iq_2x_u200/ip_repo/axis_demux 2020.2