###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# Primary clock definitions
create_clock -name refclk         -period  1.29 [get_ports fpga_refclk_in_p];  # 775.194 MHz  ????

# device clock
create_clock -name tx_device_clk     -period  2.66 [get_ports clkin6_p];#  2.58   2.66 ns = 375MHz
create_clock -name rx_device_clk     -period  2.66 [get_ports clkin10_p];#
create_clock -name clkin8            -period  2.0 [get_ports clkin8_p]

# Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
set_input_delay -clock [get_clocks tx_device_clk] \
  [get_property PERIOD [get_clocks tx_device_clk]] \
  [get_ports {sysref2_*}]

# For transceiver output clocks use reference clock divided by two
# This will help autoderive the clocks correcly
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]]
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]]

set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]]
set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]]
set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]

# Define SPI clock
create_clock -name spi0_clk      -period 40   [get_pins -hier */EMIOSPI0SCLKO]
create_clock -name spi1_clk      -period 40   [get_pins -hier */EMIOSPI1SCLKO]

set_false_path -from [get_clocks QSFP2_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP2_SI570_CLOCK_P]

set_false_path -from [get_clocks QSFP3_SI570_CLOCK_P] -to [get_clocks clk_pl_0]
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks QSFP3_SI570_CLOCK_P]

set_false_path -from [get_clocks clk_pl_0] -to [get_clocks rx_device_clk]
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk_pl_0]

set_false_path -from [get_clocks clk_pl_0] -to [get_clocks tx_device_clk]
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk_pl_0]

set_false_path -from [get_clocks clk_pl_2] -to [get_clocks rx_device_clk]
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks tx_device_clk]

set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks clk_pl_0]

set_false_path -from [get_clocks clk_pl_0] -to [get_clocks clk_pl_1]
set_false_path -from [get_clocks clk_pl_1] -to [get_clocks clk_pl_0]

set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]

set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]

set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]

set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]

set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]

set_false_path -from [get_clocks clkin8] -to [get_clocks clk_pl_0]
set_false_path -from [get_clocks refclk] -to [get_clocks clk_pl_0]
set_false_path -from [get_clocks refclk] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks clk_pl_2]

set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks tx_device_clk] -to [get_clocks clk_pl_2]

set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]

set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]


set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]


set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_false_path -from [get_clocks clk_pl_0] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_false_path -from [get_clocks rx_device_clk] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]

set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_0]

set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]


set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
set_false_path -from [get_clocks clk_pl_2] -to [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/RXOUTCLK}]]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[1].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]
set_false_path -from [get_clocks -of_objects [get_pins {i_qsfp_intfc_v1_0/i_dig_iq_x2_1/GEN_0[0].i_dig_iq/cell536086663/inst/dig_iq_40g_aurora_core_i/dig_iq_40g_aurora_wrapper_i/dig_iq_40g_aurora_multi_gt_i/dig_iq_40g_aurora_gt_i/inst/gen_gtwizard_gtye4_top.dig_iq_40g_aurora_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[29].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLKPCS}]] -to [get_clocks clk_pl_2]