chan0_i[15:0] chan0_i[15:0] STYLE_ANALOG 100 SIGNEDDECRADIX chan1_i[15:0] chan1_i[15:0] STYLE_ANALOG 100 SIGNEDDECRADIX chan2_i[15:0] chan2_i[15:0] STYLE_ANALOG 100 SIGNEDDECRADIX chan3_i[15:0] chan3_i[15:0] STYLE_ANALOG SIGNEDDECRADIX 100 chan0_q[15:0] chan0_q[15:0] SIGNEDDECRADIX STYLE_ANALOG 100 chan1_q[15:0] chan1_q[15:0] chan2_q[15:0] chan2_q[15:0] chan3_q[15:0] chan3_q[15:0] dac_r[15:0] dac_r[15:0] STYLE_ANALOG 100 SIGNEDDECRADIX dac_i[15:0] dac_i[15:0] SIGNEDDECRADIX dac_idx_r[1:0] dac_idx_r[1:0] clk_in clk_in state_r state_r clk_375 clk_375 phase_acc_addsub[31:0] phase_acc_addsub[31:0] phase_acc[31:0] phase_acc[31:0] phase_acc_r[31:0] phase_acc_r[31:0] phase_inc_r[31:0] phase_inc_r[31:0] phase_offset[31:0] phase_offset[31:0] phase_offset[31:0] phase_offset[31:0] phase_offset[31:0] phase_offset[31:0] phase_offset[31:0] phase_offset[31:0] cnt4_r[31:0] cnt4_r[31:0] phase_inc[31:0] phase_inc[31:0] phase_inc_r[31:0] phase_inc_r[31:0] phase_inc_update_en phase_inc_update_en phase_inc_r1[15:0] phase_inc_r1[15:0] s_axis_phase_tvalid s_axis_phase_tvalid s_axis_phase_tdata[15:0] s_axis_phase_tdata[15:0] s_axis_phase_tdata[15:0] s_axis_phase_tdata[15:0] s_axis_phase_tdata[15:0] s_axis_phase_tdata[15:0] s_axis_phase_tdata[15:0] s_axis_phase_tdata[15:0] phase_inc_r[31:0] phase_inc_r[31:0] phase_inc_r[31:0] phase_inc_r[31:0] phase_offset[31:0] phase_offset[31:0] swap_r swap_r clk_in clk_in phase_acc[31:0] phase_acc[31:0] phase_acc_r[31:0] phase_acc_r[31:0] phase_acc_addsub[31:0] phase_acc_addsub[31:0] phase2_32[31:0] phase2_32[31:0] phase3_32[31:0] phase3_32[31:0] phase_step_eff1[31:0] phase_step_eff1[31:0]