xilinx.com user iq_512b_to_240b 1.0 s_axis TVALID s_axis_tvalid TREADY s_axis_tready TDATA s_axis_tdata 511 0 TDATA_NUM_BYTES 64 TDEST_WIDTH 0 TID_WIDTH 0 TUSER_WIDTH 0 HAS_TREADY 1 HAS_TSTRB 0 HAS_TKEEP 0 HAS_TLAST 0 FREQ_HZ 195312500 PHASE 0.0 LAYERED_METADATA undef m_axis TDATA m_axis_tdata 239 0 TVALID m_axis_tvalid TREADY m_axis_tready TDATA_NUM_BYTES 30 TDEST_WIDTH 0 TID_WIDTH 0 TUSER_WIDTH 0 HAS_TREADY 1 HAS_TSTRB 0 HAS_TKEEP 0 HAS_TLAST 0 FREQ_HZ 195312500 PHASE 0.0 LAYERED_METADATA undef RST.ARESETN RST aresetn POLARITY ACTIVE_LOW CLK.ACLK CLK aclk FREQ_HZ 195312500 FREQ_TOLERANCE_HZ 0 PHASE 0.0 ASSOCIATED_BUSIF s_axis:m_axis ASSOCIATED_RESET aresetn xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL iq_512b_to_240b xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 083caf21 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL iq_512b_to_240b xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum b25fa64d xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f64a5dae aclk in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tdata out 239 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tdata in 511 0 STD_LOGIC_VECTOR xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tready out STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_tvalid in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation xilinx_anylanguagesynthesis_view_fileset src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci xci IMPORTED_FILE CELL_NAME_axis_dwidth_converter_0 src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci xci IMPORTED_FILE CELL_NAME_dig_iq_encoder_0 src/iq_512b_to_240b_ooc.xdc xdc IMPORTED_FILE SCOPED_TO_REF_iq_512b_to_240b USED_IN_out_of_context src/iq_512b_to_240b.vhd vhdlSource CHECKSUM_3d51e471 IMPORTED_FILE xilinx_anylanguagesynthesis_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagesynthesis_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset src/iq_512b_to_240b_axis_dwidth_converter_0_0/iq_512b_to_240b_axis_dwidth_converter_0_0.xci xci IMPORTED_FILE CELL_NAME_axis_dwidth_converter_0 src/iq_512b_to_240b_dig_iq_encoder_0_0/iq_512b_to_240b_dig_iq_encoder_0_0.xci xci IMPORTED_FILE CELL_NAME_dig_iq_encoder_0 sim/iq_512b_to_240b.vhd vhdlSource IMPORTED_FILE xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_dwidth_converter_1_1__ref_view_fileset xilinx_anylanguagebehavioralsimulation_xilinx_com_user_dig_iq_encoder_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/iq_512b_to_240b_v1_0.tcl tclSource CHECKSUM_f64a5dae XGUI_VERSION_2 iq_512b_to_240b Component_Name iq_512b_to_240b_v1_0 virtexuplus zynquplus /UserIP iq_512b_to_240b IPI 2 2024-01-24T16:38:16Z 2023.1