xilinx.com user axis_mux 1.0 m_axis TDATA m_axis_tdata TVALID m_axis_tvalid TREADY m_axis_tready s0_axis TDATA s0_axis_tdata TVALID s0_axis_tvalid TREADY s0_axis_tready s1_axis TDATA s1_axis_tdata TVALID s1_axis_tvalid TREADY s1_axis_tready aresetn RST aresetn POLARITY ACTIVE_LOW aclk CLK aclk ASSOCIATED_BUSIF m_axis:s0_axis:s1_axis ASSOCIATED_RESET aresetn xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axis_mux xilinx_anylanguagesynthesis_view_fileset viewChecksum 555c46b8 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axis_mux xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 925c6e32 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum c6faabd4 aclk in STD_LOGIC xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation aselect in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_axis_tdata in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s0_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s0_axis_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_axis_tdata in 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s1_axis_tvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_axis_tready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tdata out 511 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_tready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 DWIDTH Dwidth 512 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axis_mux_ooc.xdc xdc USED_IN_out_of_context axis_mux.vhd vhdlSource CHECKSUM_925c6e32 xilinx_anylanguagebehavioralsimulation_view_fileset axis_mux.vhd vhdlSource xilinx_xpgui_view_fileset xgui/axis_mux_v1_0.tcl tclSource CHECKSUM_c6faabd4 XGUI_VERSION_2 axis_mux_v1_0 Component_Name axis_mux_v1_0 DWIDTH DWIDTH 512 versal zynq virtexuplus virtexuplusHBM zynquplus kintexu /UserIP axis_mux_v1_0 package_project XPM_COMP_DECL 6 2021-06-22T19:14:43Z c:/Users/TempUser/Desktop/dig_iq_2x_u200/dig_iq_2x_u200/ip_repo/axis_mux c:/Users/TempUser/Desktop/dig_iq_2x_u200/dig_iq_2x_u200/ip_repo/axis_mux c:/Users/TempUser/Desktop/dig_iq_2x_u200/dig_iq_2x_u200/ip_repo/axis_mux c:/Users/TempUser/Desktop/dig_iq_2x_u200/dig_iq_2x_u200/ip_repo/axis_mux c:/Users/TempUser/Desktop/dig_iq_2x_u200/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/alveo/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux c:/Projects/dig_iq_2x_u200/ip_repo/axis_mux 2020.2