user user axi_regs_32 1.0 S_AXI AWADDR S_AXI_AWADDR AWPROT S_AXI_AWPROT AWVALID S_AXI_AWVALID AWREADY S_AXI_AWREADY WDATA S_AXI_WDATA WSTRB S_AXI_WSTRB WVALID S_AXI_WVALID WREADY S_AXI_WREADY BRESP S_AXI_BRESP BVALID S_AXI_BVALID BREADY S_AXI_BREADY ARADDR S_AXI_ARADDR ARPROT S_AXI_ARPROT ARVALID S_AXI_ARVALID ARREADY S_AXI_ARREADY RDATA S_AXI_RDATA RRESP S_AXI_RRESP RVALID S_AXI_RVALID RREADY S_AXI_RREADY S_AXI_ARESETN RST S_AXI_ARESETN POLARITY ACTIVE_LOW S_AXI_ACLK CLK S_AXI_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_AXI_ARESETN FREQ_TOLERANCE_HZ -1 S_AXI S_AXI reg0 reg0 0x0 4096 32 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axi_regs_32 xilinx_anylanguagesynthesis_view_fileset viewChecksum 9264ff2f xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axi_regs_32 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum d16affe2 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 6ac409a3 reg0_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg1_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg2_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg3_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg4_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg5_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg6_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg7_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg8_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg9_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg10_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg11_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg12_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg13_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg14_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg15_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg16_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg17_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg18_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg19_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg20_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg21_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg22_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg23_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg24_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg25_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg26_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg27_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg28_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg29_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg30_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg31_out out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg0_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg1_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg2_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg3_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg4_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg5_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg6_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg7_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg8_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg9_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg10_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg11_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg12_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg13_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg14_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg15_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg16_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg17_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg18_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg19_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg20_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg21_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg22_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg23_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg24_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg25_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg26_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg27_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg28_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg29_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg30_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reg31_in in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_ARESETN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_AWADDR in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_AWPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_WDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_WSTRB in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 S_AXI_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARADDR in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARPROT in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 C_S_AXI_DATA_WIDTH C S Axi Data Width 32 C_S_AXI_ADDR_WIDTH C S Axi Addr Width 7 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_regs_32_ooc.xdc xdc USED_IN_out_of_context axi_regs_32.vhd vhdlSource CHECKSUM_d16affe2 xilinx_anylanguagebehavioralsimulation_view_fileset axi_regs_32.vhd vhdlSource xilinx_xpgui_view_fileset xgui/axi_regs_32_v1_0.tcl tclSource CHECKSUM_6ac409a3 XGUI_VERSION_2 axi_regs_32 C_S_AXI_DATA_WIDTH C S Axi Data Width 32 false C_S_AXI_ADDR_WIDTH C S Axi Addr Width 7 false Component_Name axi_regs_32_v1_0 versal zynq virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus artixuplus kintexu /UserIP axi_regs_32 package_project 3 tridsys.com:user:axi_regs_32:1.0 2023-07-06T15:45:59Z 2022.2