diff --git a/readme.md b/readme.md
index 3914179..b3ac6ff 100644
--- a/readme.md
+++ b/readme.md
@@ -156,7 +156,24 @@
 |0xFC		    | 31:0	 |  reg63	    |  reserved    |    |     R/W       |
 |  |  | | | ||
 
-## CMAC Ethernet Interface Registers Base Address: 0x81000_0000
+## CMAC_1 Ethernet Core Registers Base Address: 0x8101_0000
+
+| Address<br>Offset		|  Bit   |  Register Name      |  Bit(s) Name   |Description          	        |  Read/Write |
+| :---  | :----: | :-------: 	|	:--------  |	:--------                       | :----:        |
+|0x00		    | 31:1<br>0	 |  reg0	    |  gt_reset_reg | Reserved<br>1 = Reset, self-clearing  |     R/W       |
+|  |  | | | ||
+|0x04		    | 31:0	 |  reg1	    |  reset_reg |   |     R/W       |
+|  |  | | | ||
+|0x0C		    | 31:1<br>0	 |  reg2	    |  configuration_tx_reg1 | Reserved1<br>0 = Disable, 1 = Enable  |     R/W       |
+|  |  | | | ||
+|0x14		    | 31:1<br>0	 |  reg4	    |  configuration_rx_reg1 | Reserved1<br>0 = Disable, 1 = Enable   |     R/W       |
+|  |  | | | ||
+|0x24		    | 31:16<br>15:8<br>7:0	 |  reg5	    | core_version_reg   | Reserved<br>Major Version<br>Minor Version  |     R/W       |
+|  |  | | | ||
+|0x90		    | 31:1<br>0	 |  reg6	    |  gt_loopback | Reserved<br> 0 = Normal,<br>Near End PMA Loopback  |     R/W       |
+|  |  | | | ||
+
+## CMAC_1 Ethernet Interface Registers Base Address: 0x8100_0000
 
 | Address<br>Offset		|  Bit   |  Register Name      |  Bit(s) Name   |Description          	        |  Read/Write |
 | :---  | :----: | :-------: 	|	:--------  |	:--------                       | :----:        |
@@ -172,11 +189,78 @@
 |  |  | | | ||
 |0x14		    | 31:1<br>0	 |  reg5	    |  Reserved<br>prog_full_man | <br>Programable Full Manual Control, For Debug Only   |     R/W       |
 |  |  | | | ||
-|0x18		    | 31:0	 |  reg6	    | ?????   | ?????  |     R/W       |
+|0x18		    | 31:0	 |  reg6	    | prog_full_on   | Programable Full On Threshold  |     R/W       |
 |  |  | | | ||
-|0x1C		    | 31:0	 |  reg7	    |  prog_full_on | Programable Full On Threshold  |     R/W       |
+|0x1C		    | 31:0	 |  reg7	    |  prog_full_off | Programable Full Off Threshold  |     R/W       |
 |  |  | | | ||
-|0x20		    | 31:0	 |  reg8	    |  prog_full_off | Programable Full Off Threshold  |     R/W       |
+|   		    |   	 |   	    |    |    |     R/W       |
+|  |  | | | ||
+|0x40		    | 31:0	 |  reg16	    |  tx_frame_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x44		    | 31:0	 |  reg17	    |  tx_frame_underrun_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x48		    | 31:0	 |  reg18	    |  tx_pause_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x4C		    | 31:0	 |  reg19	    |  rx_frame_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x50		    | 31:0	 |  reg20	    |  rx_frame_err_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x54		    | 31:0	 |  reg21	    |  rx_pause_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x58		    | 31:0	 |  reg22	    |  rx_fifo_overflow_cnt | ?????  |     R       |
+|  |  | | | ||
+
+## CMAC_4 Ethernet Core Registers Base Address: 0x8201_0000
+
+| Address<br>Offset		|  Bit   |  Register Name      |  Bit(s) Name   |Description          	        |  Read/Write |
+| :---  | :----: | :-------: 	|	:--------  |	:--------                       | :----:        |
+|0x00		    | 31:1<br>0	 |  reg0	    |  gt_reset_reg | Reserved<br>1 = Reset, self-clearing  |     R/W       |
+|  |  | | | ||
+|0x04		    | 31:0	 |  reg1	    |  reset_reg |   |     R/W       |
+|  |  | | | ||
+|0x0C		    | 31:1<br>0	 |  reg2	    |  configuration_tx_reg1 | Reserved1<br>0 = Disable, 1 = Enable  |     R/W       |
+|  |  | | | ||
+|0x14		    | 31:1<br>0	 |  reg4	    |  configuration_rx_reg1 | Reserved1<br>0 = Disable, 1 = Enable   |     R/W       |
+|  |  | | | ||
+|0x24		    | 31:16<br>15:8<br>7:0	 |  reg5	    | core_version_reg   | Reserved<br>Major Version<br>Minor Version  |     R/W       |
+|  |  | | | ||
+|0x90		    | 31:1<br>0	 |  reg6	    |  gt_loopback | Reserved<br> 0 = Normal,<br>Near End PMA Loopback  |     R/W       |
+|  |  | | | ||
+## CMAC_4 Ethernet Interface Registers Base Address: 0x8200_0000
+
+| Address<br>Offset		|  Bit   |  Register Name      |  Bit(s) Name   |Description          	        |  Read/Write |
+| :---  | :----: | :-------: 	|	:--------  |	:--------                       | :----:        |
+|0x00		    | 31:0	 |  reg0	    |  dest_mac_addr_lo | Destination MAC address (lower 32-bit)  |     R/W       |
+|  |  | | | ||
+|0x04		    | 31:0	 |  reg1	    |  dest_mac_addr_hi | Destination MAC address (upper 16-bit)  |     R/W       |
+|  |  | | | ||
+|0x08		    | 31:0	 |  reg2	    |  src_mac_addr_lo | Source MAC address (lower 32-bit)  |     R/W       |
+|  |  | | | ||
+|0x0C		    | 31:0	 |  reg3	    |  src_mac_addr_hi | Source MAC address (upper 16-bit)  |     R/W       |
+|  |  | | | ||
+|0x10		    | 31:16<br>30:0	 |  reg4	    |  Reserved<br>ether_type | <br>Ethernet Type   |     R/W       |
+|  |  | | | ||
+|0x14		    | 31:1<br>0	 |  reg5	    |  Reserved<br>prog_full_man | <br>Programable Full Manual Control, For Debug Only   |     R/W       |
+|  |  | | | ||
+|0x18		    | 31:0	 |  reg6	    | prog_full_on   | Programable Full On Threshold  |     R/W       |
+|  |  | | | ||
+|0x1C		    | 31:0	 |  reg7	    |  prog_full_off | Programable Full Off Threshold  |     R/W       |
+|  |  | | | ||
+|   		    |   	 |   	    |    |    |     R/W       |
+|  |  | | | ||
+|0x40		    | 31:0	 |  reg16	    |  tx_frame_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x44		    | 31:0	 |  reg17	    |  tx_frame_underrun_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x48		    | 31:0	 |  reg18	    |  tx_pause_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x4C		    | 31:0	 |  reg19	    |  rx_frame_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x50		    | 31:0	 |  reg20	    |  rx_frame_err_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x54		    | 31:0	 |  reg21	    |  rx_pause_cnt | ?????  |     R       |
+|  |  | | | ||
+|0x58		    | 31:0	 |  reg22	    |  rx_fifo_overflow_cnt | ?????  |     R       |
 |  |  | | | ||
 
 # How to re-create Project in Vivado