Added DDS Interface
This commit is contained in:
@@ -0,0 +1,192 @@
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{
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"schema": "xilinx.com:schema:json_instance:1.0",
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"ip_inst": {
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"xci_name": "axis_afifo_64x512",
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"component_reference": "xilinx.com:ip:axis_data_fifo:2.0",
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"ip_revision": "11",
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"gen_directory": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_afifo_64x512",
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"parameters": {
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"component_parameters": {
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"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"TUSER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"FIFO_DEPTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"FIFO_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"IS_ACLK_ASYNC": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_TREADY": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"HAS_TSTRB": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_TKEEP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_TLAST": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_RD_DATA_COUNT": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_AEMPTY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_PROG_EMPTY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"PROG_EMPTY_THRESH": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"HAS_AFULL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_PROG_FULL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"ENABLE_ECC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HAS_ECC_ERR_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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"FIFO_MEMORY_TYPE": [ { "value": "block", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
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"Component_Name": [ { "value": "axis_data_fifo_64x128", "resolve_type": "user", "usage": "all" } ]
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},
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"model_parameters": {
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"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
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"C_AXIS_TDATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_AXIS_SIGNAL_SET": [ { "value": "0b00000000000000000000000000000011", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
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"C_FIFO_DEPTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_FIFO_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_SYNCHRONIZER_STAGE": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_ACLKEN_CONV_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_ECC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_FIFO_MEMORY_TYPE": [ { "value": "block", "resolve_type": "generated", "usage": "all" } ],
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"C_USE_ADV_FEATURES": [ { "value": "825241648", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_PROG_EMPTY_THRESH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_PROG_FULL_THRESH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ]
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},
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"project_parameters": {
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"ARCHITECTURE": [ { "value": "zynquplus" } ],
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"BASE_BOARD_PART": [ { "value": "" } ],
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"BOARD_CONNECTIONS": [ { "value": "" } ],
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"DEVICE": [ { "value": "xczu19eg" } ],
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"PACKAGE": [ { "value": "ffvc1760" } ],
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"PREFHDL": [ { "value": "VERILOG" } ],
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"SILICON_REVISION": [ { "value": "" } ],
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"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
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"SPEEDGRADE": [ { "value": "-2" } ],
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"STATIC_POWER": [ { "value": "" } ],
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"TEMPERATURE_GRADE": [ { "value": "I" } ]
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},
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"runtime_parameters": {
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"IPCONTEXT": [ { "value": "IP_Flow" } ],
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"IPREVISION": [ { "value": "11" } ],
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"MANAGED": [ { "value": "TRUE" } ],
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"OUTPUTDIR": [ { "value": "../../ad9082_fmca_ebz_alinx_z19/ad9082_fmca_ebz_alinx_z19.gen/sources_1/ip/axis_afifo_64x512" } ],
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"SELECTEDSIMMODEL": [ { "value": "" } ],
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"SHAREDDIR": [ { "value": "." } ],
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"SWVERSION": [ { "value": "2023.2" } ],
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"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
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}
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},
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"boundary": {
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"ports": {
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"s_axis_aresetn": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axis_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axis_tready": [ { "direction": "out" } ],
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"s_axis_tdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ],
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"m_axis_aclk": [ { "direction": "in", "driver_value": "0x0" } ],
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"m_axis_tvalid": [ { "direction": "out" } ],
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"m_axis_tready": [ { "direction": "in", "driver_value": "0x1" } ],
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"m_axis_tdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ]
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},
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"interfaces": {
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"S_AXIS": {
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"vlnv": "xilinx.com:interface:axis:1.0",
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"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"TDATA": [ { "physical_name": "s_axis_tdata" } ],
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"TREADY": [ { "physical_name": "s_axis_tready" } ],
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"TVALID": [ { "physical_name": "s_axis_tvalid" } ]
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}
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},
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"M_AXIS": {
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"vlnv": "xilinx.com:interface:axis:1.0",
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"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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"mode": "master",
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"parameters": {
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"TDATA_NUM_BYTES": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"TDATA": [ { "physical_name": "m_axis_tdata" } ],
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"TREADY": [ { "physical_name": "m_axis_tready" } ],
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"TVALID": [ { "physical_name": "m_axis_tvalid" } ]
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}
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},
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"S_RSTIF": {
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"vlnv": "xilinx.com:signal:reset:1.0",
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"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"POLARITY": [ { "value": "ACTIVE_LOW", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"RST": [ { "physical_name": "s_axis_aresetn" } ]
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}
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},
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"S_CLKIF": {
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"vlnv": "xilinx.com:signal:clock:1.0",
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"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"ASSOCIATED_BUSIF": [ { "value": "S_AXIS", "value_src": "constant", "usage": "all" } ],
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"CLK": [ { "physical_name": "s_axis_aclk" } ]
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}
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},
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"M_CLKIF": {
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"vlnv": "xilinx.com:signal:clock:1.0",
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"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"ASSOCIATED_BUSIF": [ { "value": "M_AXIS", "value_src": "constant", "usage": "all" } ],
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"CLK": [ { "physical_name": "m_axis_aclk" } ]
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}
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}
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}
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}
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}
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}
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@@ -0,0 +1,360 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dds_pulse_intfc_v1_0 is
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generic (
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-- Users to add parameters here
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-- User parameters ends
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-- Do not modify the parameters beyond this line
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-- Parameters of Axi Slave Bus Interface S00_AXI
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C_S00_AXI_DATA_WIDTH : integer := 32;
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C_S00_AXI_ADDR_WIDTH : integer := 8
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);
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port (
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-- Users to add ports here
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m_axis_aclk_in : in std_logic;
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m_axis_aresetn_in : in std_logic;
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m0_axis_tdata_out : out std_logic_vector(127 downto 0);
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m0_axis_tvalid_out : out std_logic;
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m0_axis_tready_in : in std_logic;
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m1_axis_tdata_out : out std_logic_vector(127 downto 0);
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m1_axis_tvalid_out : out std_logic;
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m1_axis_tready_in : in std_logic;
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dac_holdoff_ext_en_in : in std_logic;
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dac_holdoff_ext_in : in std_logic;
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dac_holdoff_ext_out : out std_logic;
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-- User ports ends
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||||
-- Do not modify the ports beyond this line
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-- Ports of Axi Slave Bus Interface S00_AXI
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s00_axi_aclk_in : in std_logic;
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s00_axi_aresetn_in : in std_logic;
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s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
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s00_axi_awprot : in std_logic_vector(2 downto 0);
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s00_axi_awvalid : in std_logic;
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s00_axi_awready : out std_logic;
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s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
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s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
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s00_axi_wvalid : in std_logic;
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s00_axi_wready : out std_logic;
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s00_axi_bresp : out std_logic_vector(1 downto 0);
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s00_axi_bvalid : out std_logic;
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s00_axi_bready : in std_logic;
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s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
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s00_axi_arprot : in std_logic_vector(2 downto 0);
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s00_axi_arvalid : in std_logic;
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||||
s00_axi_arready : out std_logic;
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s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
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s00_axi_rresp : out std_logic_vector(1 downto 0);
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s00_axi_rvalid : out std_logic;
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s00_axi_rready : in std_logic
|
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);
|
||||
end dds_pulse_intfc_v1_0;
|
||||
|
||||
architecture arch_imp of dds_pulse_intfc_v1_0 is
|
||||
|
||||
signal cmd_send_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
|
||||
signal dac_holdoff : std_logic;
|
||||
signal dac_holdoff_i : std_logic;
|
||||
|
||||
signal m0_axis_tvalid_cnt : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_pulse_data_cnt : std_logic_vector(31 downto 0);
|
||||
|
||||
signal m1_axis_tvalid_cnt : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_pulse_data_cnt : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_0 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_0 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_0 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_0 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_0 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_0 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_0 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_0 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_1 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_1 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_1 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_1 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_1 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_1 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_1 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_2 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_2 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_2 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_2 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_2 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_2 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_2 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_2 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal scale_3 : std_logic_vector(15 downto 0);
|
||||
signal dds_phase_inc_dwell_time_3 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size_3 : std_logic_vector(31 downto 0);
|
||||
signal idle_samples_3 : std_logic_vector(31 downto 0);
|
||||
signal dds_samples_3 : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_3 : std_logic_vector(31 downto 0);
|
||||
signal phase_off_3 : std_logic_vector(31 downto 0);
|
||||
signal swap_sf_3 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal slv_reg0 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg1 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg2 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg3 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg4 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg5 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg6 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg7 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg8 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg9 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg10 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg11 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg12 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg13 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg14 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg15 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg16 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg17 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg18 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg19 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg20 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg21 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg22 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg23 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg24 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg25 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg26 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg27 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg28 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg29 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg30 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg31 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg32 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg33 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg34 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg35 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg36 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg37 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg38 : std_logic_vector(31 downto 0);
|
||||
signal slv_reg39 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal cnt_reset : std_logic;
|
||||
|
||||
signal dds_enable : std_logic;
|
||||
signal dds_reset_n : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Instantiation of Axi Bus Interface S00_AXI
|
||||
dds_pulse_intfc_v1_0_S00_AXI_inst : entity work.dds_pulse_intfc_v1_0_S00_AXI
|
||||
generic map (
|
||||
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
|
||||
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
|
||||
)
|
||||
port map (
|
||||
slv_reg0_out => slv_reg0,
|
||||
slv_reg1_out => slv_reg1,
|
||||
slv_reg2_out => slv_reg2,
|
||||
slv_reg3_out => slv_reg3,
|
||||
slv_reg4_out => slv_reg4,
|
||||
slv_reg5_out => slv_reg5,
|
||||
slv_reg6_out => slv_reg6,
|
||||
slv_reg7_out => slv_reg7,
|
||||
slv_reg8_out => slv_reg8,
|
||||
slv_reg9_out => slv_reg9,
|
||||
slv_reg10_out => slv_reg10,
|
||||
slv_reg11_out => slv_reg11,
|
||||
slv_reg12_out => slv_reg12,
|
||||
slv_reg13_out => slv_reg13,
|
||||
slv_reg14_out => slv_reg14,
|
||||
slv_reg15_out => slv_reg15,
|
||||
slv_reg16_out => slv_reg16,
|
||||
slv_reg17_out => slv_reg17,
|
||||
slv_reg18_out => slv_reg18,
|
||||
slv_reg19_out => slv_reg19,
|
||||
slv_reg20_out => slv_reg20,
|
||||
slv_reg21_out => slv_reg21,
|
||||
slv_reg22_out => slv_reg22,
|
||||
slv_reg23_out => slv_reg23,
|
||||
slv_reg24_out => slv_reg24,
|
||||
slv_reg25_out => slv_reg25,
|
||||
slv_reg26_out => slv_reg26,
|
||||
slv_reg27_out => slv_reg27,
|
||||
slv_reg28_out => slv_reg28,
|
||||
slv_reg29_out => slv_reg29,
|
||||
slv_reg30_out => slv_reg30,
|
||||
slv_reg31_out => slv_reg31,
|
||||
slv_reg32_out => slv_reg32,
|
||||
slv_reg33_out => slv_reg33,
|
||||
slv_reg34_out => slv_reg34,
|
||||
slv_reg35_out => slv_reg35,
|
||||
slv_reg36_in => slv_reg36,
|
||||
slv_reg37_in => slv_reg37,
|
||||
slv_reg38_in => slv_reg38,
|
||||
slv_reg39_in => slv_reg39,
|
||||
|
||||
S_AXI_ACLK => s00_axi_aclk_in,
|
||||
S_AXI_ARESETN => s00_axi_aresetn_in,
|
||||
S_AXI_AWADDR => s00_axi_awaddr,
|
||||
S_AXI_AWPROT => s00_axi_awprot,
|
||||
S_AXI_AWVALID => s00_axi_awvalid,
|
||||
S_AXI_AWREADY => s00_axi_awready,
|
||||
S_AXI_WDATA => s00_axi_wdata,
|
||||
S_AXI_WSTRB => s00_axi_wstrb,
|
||||
S_AXI_WVALID => s00_axi_wvalid,
|
||||
S_AXI_WREADY => s00_axi_wready,
|
||||
S_AXI_BRESP => s00_axi_bresp,
|
||||
S_AXI_BVALID => s00_axi_bvalid,
|
||||
S_AXI_BREADY => s00_axi_bready,
|
||||
S_AXI_ARADDR => s00_axi_araddr,
|
||||
S_AXI_ARPROT => s00_axi_arprot,
|
||||
S_AXI_ARVALID => s00_axi_arvalid,
|
||||
S_AXI_ARREADY => s00_axi_arready,
|
||||
S_AXI_RDATA => s00_axi_rdata,
|
||||
S_AXI_RRESP => s00_axi_rresp,
|
||||
S_AXI_RVALID => s00_axi_rvalid,
|
||||
S_AXI_RREADY => s00_axi_rready
|
||||
);
|
||||
|
||||
-- Add user logic here
|
||||
|
||||
--slv_reg0 --0x8300_0000
|
||||
process (s00_axi_aclk_in)
|
||||
begin
|
||||
if rising_edge(s00_axi_aclk_in) then
|
||||
if (slv_reg0(0) = '1') then
|
||||
cmd_send_r <= "111";
|
||||
else
|
||||
cmd_send_r <= cmd_send_r(1 to 2) & '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dac_holdoff <= slv_reg1(0); --0x8300_0004
|
||||
dac_holdoff_i <= dac_holdoff_ext_in when dac_holdoff_ext_en_in = '1' else dac_holdoff;
|
||||
dac_holdoff_ext_out <= dac_holdoff_i;
|
||||
|
||||
-- <= slv_reg2(3 downto 0); --0x8300_0008
|
||||
|
||||
cnt_reset <= slv_reg3(0); --0x8300_000C
|
||||
dds_enable <= slv_reg3(31);
|
||||
|
||||
scale_0 <= slv_reg4(15 downto 0); --0x8300_0010
|
||||
dds_phase_inc_dwell_time_0 <= slv_reg5; --0x8300_0014
|
||||
dds_phase_inc_step_size_0 <= slv_reg6; --0x8300_0018
|
||||
idle_samples_0 <= slv_reg7; --0x8300_001C
|
||||
dds_samples_0 <= slv_reg8; --0x8300_0020
|
||||
phase_inc_0 <= slv_reg9; --0x8300_0024
|
||||
phase_off_0 <= slv_reg10; --0x8300_0028
|
||||
swap_sf_0 <= slv_reg11; --0x8300_002C
|
||||
|
||||
scale_1 <= slv_reg12(15 downto 0); --0x8300_0030
|
||||
dds_phase_inc_dwell_time_1 <= slv_reg13; --0x8300_0034
|
||||
dds_phase_inc_step_size_1 <= slv_reg14; --0x8300_0038
|
||||
idle_samples_1 <= slv_reg15; --0x8300_003C
|
||||
dds_samples_1 <= slv_reg16; --0x8300_0040
|
||||
phase_inc_1 <= slv_reg17; --0x8300_0044
|
||||
phase_off_1 <= slv_reg18; --0x8300_0048
|
||||
swap_sf_1 <= slv_reg19; --0x8300_004C
|
||||
|
||||
scale_2 <= slv_reg20(15 downto 0); --0x8300_0050
|
||||
dds_phase_inc_dwell_time_2 <= slv_reg21; --0x8300_0054
|
||||
dds_phase_inc_step_size_2 <= slv_reg22; --0x8300_0058
|
||||
idle_samples_2 <= slv_reg23; --0x8300_005C
|
||||
dds_samples_2 <= slv_reg24; --0x8300_0060
|
||||
phase_inc_2 <= slv_reg25; --0x8300_0064
|
||||
phase_off_2 <= slv_reg26; --0x8300_0068
|
||||
swap_sf_2 <= slv_reg27; --0x8300_006C
|
||||
|
||||
scale_3 <= slv_reg28(15 downto 0); --0x8300_0070
|
||||
dds_phase_inc_dwell_time_3 <= slv_reg29; --0x8300_0074
|
||||
dds_phase_inc_step_size_3 <= slv_reg30; --0x8300_0078
|
||||
idle_samples_3 <= slv_reg31; --0x8300_007C
|
||||
dds_samples_3 <= slv_reg32; --0x8300_0080
|
||||
phase_inc_3 <= slv_reg33; --0x8300_0084
|
||||
phase_off_3 <= slv_reg34; --0x8300_0088
|
||||
swap_sf_3 <= slv_reg35; --0x8300_008C
|
||||
|
||||
slv_reg36 <= m0_dds_pulse_data_cnt; --0x8300_0090
|
||||
slv_reg37 <= m0_axis_tvalid_cnt; --0x8300_0094
|
||||
slv_reg38 <= m1_dds_pulse_data_cnt; --0x8300_0098
|
||||
slv_reg39 <= m1_axis_tvalid_cnt; --0x8300_009C
|
||||
|
||||
|
||||
dds_reset_n <= '0' when m_axis_aresetn_in = '0' or dds_enable = '0' else '1';
|
||||
|
||||
i_dds_pulse_intfc_x4 : entity work.dds_pulse_intfc_x4
|
||||
port map (
|
||||
s_axi_aclk_in => s00_axi_aclk_in,
|
||||
s_axi_aresetn_in => s00_axi_aresetn_in,
|
||||
|
||||
cmd_idx_in => "000",
|
||||
dac_holdoff_in => dac_holdoff_i,
|
||||
cmd_send_in => cmd_send_r(0),
|
||||
|
||||
scale_0_in => scale_0,
|
||||
dds_phase_inc_dwell_time_0_in => dds_phase_inc_dwell_time_0,
|
||||
dds_phase_inc_step_size_0_in => dds_phase_inc_step_size_0,
|
||||
idle_samples_0_in => idle_samples_0,
|
||||
dds_samples_0_in => dds_samples_0,
|
||||
phase_inc_0_in => phase_inc_0,
|
||||
phase_off_0_in => phase_off_0,
|
||||
swap_sf_0_in => swap_sf_0,
|
||||
|
||||
scale_1_in => scale_0,
|
||||
dds_phase_inc_dwell_time_1_in => dds_phase_inc_dwell_time_0,
|
||||
dds_phase_inc_step_size_1_in => dds_phase_inc_step_size_0,
|
||||
idle_samples_1_in => idle_samples_0,
|
||||
dds_samples_1_in => dds_samples_0,
|
||||
phase_inc_1_in => phase_inc_0,
|
||||
phase_off_1_in => phase_off_1,
|
||||
swap_sf_1_in => swap_sf_0,
|
||||
|
||||
scale_2_in => scale_0,
|
||||
dds_phase_inc_dwell_time_2_in => dds_phase_inc_dwell_time_0,
|
||||
dds_phase_inc_step_size_2_in => dds_phase_inc_step_size_0,
|
||||
idle_samples_2_in => idle_samples_0,
|
||||
dds_samples_2_in => dds_samples_0,
|
||||
phase_inc_2_in => phase_inc_0,
|
||||
phase_off_2_in => phase_off_2,
|
||||
swap_sf_2_in => swap_sf_0,
|
||||
|
||||
scale_3_in => scale_0,
|
||||
dds_phase_inc_dwell_time_3_in => dds_phase_inc_dwell_time_0,
|
||||
dds_phase_inc_step_size_3_in => dds_phase_inc_step_size_0,
|
||||
idle_samples_3_in => idle_samples_0,
|
||||
dds_samples_3_in => dds_samples_0,
|
||||
phase_inc_3_in => phase_inc_0,
|
||||
phase_off_3_in => phase_off_3,
|
||||
swap_sf_3_in => swap_sf_0,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => dds_reset_n, ---m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_axis_tdata_out,
|
||||
m0_axis_tvalid_out => m0_axis_tvalid_out,
|
||||
m0_axis_tready_in => m0_axis_tready_in,
|
||||
|
||||
m1_axis_tdata_out => m1_axis_tdata_out,
|
||||
m1_axis_tvalid_out => m1_axis_tvalid_out,
|
||||
m1_axis_tready_in => m1_axis_tready_in,
|
||||
|
||||
cnt_reset_in => cnt_reset,
|
||||
m0_axis_tvalid_cnt_out => m0_axis_tvalid_cnt,
|
||||
m0_dds_pulse_data_cnt_out => m0_dds_pulse_data_cnt,
|
||||
m1_axis_tvalid_cnt_out => m1_axis_tvalid_cnt,
|
||||
m1_dds_pulse_data_cnt_out => m1_dds_pulse_data_cnt
|
||||
);
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,943 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dds_pulse_intfc_v1_0_S00_AXI is
|
||||
generic (
|
||||
-- Users to add parameters here
|
||||
|
||||
-- User parameters ends
|
||||
-- Do not modify the parameters beyond this line
|
||||
|
||||
-- Width of S_AXI data bus
|
||||
C_S_AXI_DATA_WIDTH : integer := 32;
|
||||
-- Width of S_AXI address bus
|
||||
C_S_AXI_ADDR_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
-- Users to add ports here
|
||||
slv_reg0_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg1_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg2_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg3_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg4_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg5_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg6_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg7_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg8_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg9_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg10_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg11_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg12_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg13_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg14_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg15_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg16_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg17_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg18_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg19_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg20_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg21_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg22_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg23_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg24_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg25_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg26_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg27_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg28_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg29_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg30_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg31_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg32_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg33_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg34_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg35_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg36_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg37_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg38_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
slv_reg39_in : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- User ports ends
|
||||
-- Do not modify the ports beyond this line
|
||||
|
||||
-- Global Clock Signal
|
||||
S_AXI_ACLK : in std_logic;
|
||||
-- Global Reset Signal. This Signal is Active LOW
|
||||
S_AXI_ARESETN : in std_logic;
|
||||
-- Write address (issued by master, acceped by Slave)
|
||||
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Write channel Protection type. This signal indicates the
|
||||
-- privilege and security level of the transaction, and whether
|
||||
-- the transaction is a data access or an instruction access.
|
||||
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
|
||||
-- Write address valid. This signal indicates that the master signaling
|
||||
-- valid write address and control information.
|
||||
S_AXI_AWVALID : in std_logic;
|
||||
-- Write address ready. This signal indicates that the slave is ready
|
||||
-- to accept an address and associated control signals.
|
||||
S_AXI_AWREADY : out std_logic;
|
||||
-- Write data (issued by master, acceped by Slave)
|
||||
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Write strobes. This signal indicates which byte lanes hold
|
||||
-- valid data. There is one write strobe bit for each eight
|
||||
-- bits of the write data bus.
|
||||
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
|
||||
-- Write valid. This signal indicates that valid write
|
||||
-- data and strobes are available.
|
||||
S_AXI_WVALID : in std_logic;
|
||||
-- Write ready. This signal indicates that the slave
|
||||
-- can accept the write data.
|
||||
S_AXI_WREADY : out std_logic;
|
||||
-- Write response. This signal indicates the status
|
||||
-- of the write transaction.
|
||||
S_AXI_BRESP : out std_logic_vector(1 downto 0);
|
||||
-- Write response valid. This signal indicates that the channel
|
||||
-- is signaling a valid write response.
|
||||
S_AXI_BVALID : out std_logic;
|
||||
-- Response ready. This signal indicates that the master
|
||||
-- can accept a write response.
|
||||
S_AXI_BREADY : in std_logic;
|
||||
-- Read address (issued by master, acceped by Slave)
|
||||
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
-- Protection type. This signal indicates the privilege
|
||||
-- and security level of the transaction, and whether the
|
||||
-- transaction is a data access or an instruction access.
|
||||
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
|
||||
-- Read address valid. This signal indicates that the channel
|
||||
-- is signaling valid read address and control information.
|
||||
S_AXI_ARVALID : in std_logic;
|
||||
-- Read address ready. This signal indicates that the slave is
|
||||
-- ready to accept an address and associated control signals.
|
||||
S_AXI_ARREADY : out std_logic;
|
||||
-- Read data (issued by slave)
|
||||
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
-- Read response. This signal indicates the status of the
|
||||
-- read transfer.
|
||||
S_AXI_RRESP : out std_logic_vector(1 downto 0);
|
||||
-- Read valid. This signal indicates that the channel is
|
||||
-- signaling the required read data.
|
||||
S_AXI_RVALID : out std_logic;
|
||||
-- Read ready. This signal indicates that the master can
|
||||
-- accept the read data and response information.
|
||||
S_AXI_RREADY : in std_logic
|
||||
);
|
||||
end dds_pulse_intfc_v1_0_S00_AXI;
|
||||
|
||||
architecture arch_imp of dds_pulse_intfc_v1_0_S00_AXI is
|
||||
|
||||
-- AXI4LITE signals
|
||||
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_awready : std_logic;
|
||||
signal axi_wready : std_logic;
|
||||
signal axi_bresp : std_logic_vector(1 downto 0);
|
||||
signal axi_bvalid : std_logic;
|
||||
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
|
||||
signal axi_arready : std_logic;
|
||||
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal axi_rresp : std_logic_vector(1 downto 0);
|
||||
signal axi_rvalid : std_logic;
|
||||
|
||||
-- Example-specific design signals
|
||||
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
|
||||
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
|
||||
-- ADDR_LSB = 2 for 32 bits (n downto 2)
|
||||
-- ADDR_LSB = 3 for 64 bits (n downto 3)
|
||||
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
|
||||
constant OPT_MEM_ADDR_BITS : integer := 5;
|
||||
------------------------------------------------
|
||||
---- Signals for user logic register space example
|
||||
--------------------------------------------------
|
||||
---- Number of Slave Registers 40
|
||||
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg32 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg33 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg34 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg35 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg36 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg37 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg38 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg39 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal slv_reg_rden : std_logic;
|
||||
signal slv_reg_wren : std_logic;
|
||||
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
|
||||
signal byte_index : integer;
|
||||
signal aw_en : std_logic;
|
||||
|
||||
begin
|
||||
-- I/O Connections assignments
|
||||
|
||||
S_AXI_AWREADY <= axi_awready;
|
||||
S_AXI_WREADY <= axi_wready;
|
||||
S_AXI_BRESP <= axi_bresp;
|
||||
S_AXI_BVALID <= axi_bvalid;
|
||||
S_AXI_ARREADY <= axi_arready;
|
||||
S_AXI_RDATA <= axi_rdata;
|
||||
S_AXI_RRESP <= axi_rresp;
|
||||
S_AXI_RVALID <= axi_rvalid;
|
||||
-- Implement axi_awready generation
|
||||
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awready <= '0';
|
||||
aw_en <= '1';
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write address when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_awready <= '1';
|
||||
aw_en <= '0';
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
|
||||
aw_en <= '1';
|
||||
axi_awready <= '0';
|
||||
else
|
||||
axi_awready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_awaddr latching
|
||||
-- This process is used to latch the address when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_awaddr <= (others => '0');
|
||||
else
|
||||
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and aw_en = '1') then
|
||||
-- Write Address latching
|
||||
axi_awaddr <= S_AXI_AWADDR;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_wready generation
|
||||
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
|
||||
-- de-asserted when reset is low.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_wready <= '0';
|
||||
else
|
||||
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1' and aw_en = '1') then
|
||||
-- slave is ready to accept write data when
|
||||
-- there is a valid write address and write data
|
||||
-- on the write address and data bus. This design
|
||||
-- expects no outstanding transactions.
|
||||
axi_wready <= '1';
|
||||
else
|
||||
axi_wready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and write logic generation
|
||||
-- The write data is accepted and written to memory mapped registers when
|
||||
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
|
||||
-- select byte enables of slave registers while writing.
|
||||
-- These registers are cleared when reset (active low) is applied.
|
||||
-- Slave register write enable is asserted when valid address and data are available
|
||||
-- and the slave is ready to accept the write address and write data.
|
||||
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
slv_reg0 <= (others => '0');
|
||||
slv_reg1 <= x"0000_0001";
|
||||
slv_reg2 <= x"0000_000F";
|
||||
slv_reg3 <= x"8000_0000";
|
||||
slv_reg4 <= x"0000_8000";
|
||||
slv_reg5 <= x"0000_0000";
|
||||
slv_reg6 <= x"0000_D6BF";
|
||||
slv_reg7 <= x"0000_0000";
|
||||
slv_reg8 <= x"0000_04E2";
|
||||
slv_reg9 <= x"0106_24DD";
|
||||
slv_reg10 <= x"0000_0000";
|
||||
slv_reg11 <= x"0000_8000";
|
||||
slv_reg12 <= x"0000_8000";
|
||||
slv_reg13 <= x"0000_0000";
|
||||
slv_reg14 <= x"0000_D6BF";
|
||||
slv_reg15 <= x"0000_0000";
|
||||
slv_reg16 <= x"0000_04E2";
|
||||
slv_reg17 <= x"0106_24DD";
|
||||
slv_reg18 <= x"0000_0000";
|
||||
slv_reg19 <= x"0000_8000";
|
||||
slv_reg20 <= x"0000_8000";
|
||||
slv_reg21 <= x"0000_0000";
|
||||
slv_reg22 <= x"0000_D6BF";
|
||||
slv_reg23 <= x"0000_0000";
|
||||
slv_reg24 <= x"0000_04E2";
|
||||
slv_reg25 <= x"0106_24DD";
|
||||
slv_reg26 <= x"0000_0000";
|
||||
slv_reg27 <= x"0000_8000";
|
||||
slv_reg28 <= x"0000_8000";
|
||||
slv_reg29 <= x"0000_0000";
|
||||
slv_reg30 <= x"0000_D6BF";
|
||||
slv_reg31 <= x"0000_0000";
|
||||
slv_reg32 <= x"0000_04E2";
|
||||
slv_reg33 <= x"0106_24DD";
|
||||
slv_reg34 <= x"0000_0000";
|
||||
slv_reg35 <= x"0000_8000";
|
||||
slv_reg36 <= (others => '0');
|
||||
slv_reg37 <= (others => '0');
|
||||
slv_reg38 <= (others => '0');
|
||||
slv_reg39 <= (others => '0');
|
||||
else
|
||||
slv_reg0(0) <= '0'; -- self clear bit 0
|
||||
slv_reg0(4) <= '0'; -- self clear bit 0
|
||||
slv_reg0(8) <= '0'; -- self clear bit 0
|
||||
slv_reg0(12) <= '0'; -- self clear bit 0
|
||||
slv_reg3(0) <= '0'; -- self clear bit 0
|
||||
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
if (slv_reg_wren = '1') then
|
||||
case loc_addr is
|
||||
when b"000000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 0
|
||||
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 1
|
||||
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 2
|
||||
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 3
|
||||
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 4
|
||||
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 5
|
||||
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 6
|
||||
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"000111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 7
|
||||
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 8
|
||||
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 9
|
||||
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 10
|
||||
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 11
|
||||
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 12
|
||||
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 13
|
||||
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 14
|
||||
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"001111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 15
|
||||
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 16
|
||||
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 17
|
||||
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 18
|
||||
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 19
|
||||
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 20
|
||||
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 21
|
||||
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 22
|
||||
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"010111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 23
|
||||
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 24
|
||||
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 25
|
||||
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 26
|
||||
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 27
|
||||
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 28
|
||||
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 29
|
||||
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 30
|
||||
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"011111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 31
|
||||
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100000" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 32
|
||||
slv_reg32(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100001" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 33
|
||||
slv_reg33(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100010" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 34
|
||||
slv_reg34(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100011" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 35
|
||||
slv_reg35(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100100" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 36
|
||||
slv_reg36(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100101" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 37
|
||||
slv_reg37(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100110" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 38
|
||||
slv_reg38(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when b"100111" =>
|
||||
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
|
||||
if ( S_AXI_WSTRB(byte_index) = '1' ) then
|
||||
-- Respective byte enables are asserted as per write strobes
|
||||
-- slave registor 39
|
||||
slv_reg39(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
|
||||
end if;
|
||||
end loop;
|
||||
when others =>
|
||||
slv_reg0 <= slv_reg0;
|
||||
slv_reg1 <= slv_reg1;
|
||||
slv_reg2 <= slv_reg2;
|
||||
slv_reg3 <= slv_reg3;
|
||||
slv_reg4 <= slv_reg4;
|
||||
slv_reg5 <= slv_reg5;
|
||||
slv_reg6 <= slv_reg6;
|
||||
slv_reg7 <= slv_reg7;
|
||||
slv_reg8 <= slv_reg8;
|
||||
slv_reg9 <= slv_reg9;
|
||||
slv_reg10 <= slv_reg10;
|
||||
slv_reg11 <= slv_reg11;
|
||||
slv_reg12 <= slv_reg12;
|
||||
slv_reg13 <= slv_reg13;
|
||||
slv_reg14 <= slv_reg14;
|
||||
slv_reg15 <= slv_reg15;
|
||||
slv_reg16 <= slv_reg16;
|
||||
slv_reg17 <= slv_reg17;
|
||||
slv_reg18 <= slv_reg18;
|
||||
slv_reg19 <= slv_reg19;
|
||||
slv_reg20 <= slv_reg20;
|
||||
slv_reg21 <= slv_reg21;
|
||||
slv_reg22 <= slv_reg22;
|
||||
slv_reg23 <= slv_reg23;
|
||||
slv_reg24 <= slv_reg24;
|
||||
slv_reg25 <= slv_reg25;
|
||||
slv_reg26 <= slv_reg26;
|
||||
slv_reg27 <= slv_reg27;
|
||||
slv_reg28 <= slv_reg28;
|
||||
slv_reg29 <= slv_reg29;
|
||||
slv_reg30 <= slv_reg30;
|
||||
slv_reg31 <= slv_reg31;
|
||||
slv_reg32 <= slv_reg32;
|
||||
slv_reg33 <= slv_reg33;
|
||||
slv_reg34 <= slv_reg34;
|
||||
slv_reg35 <= slv_reg35;
|
||||
slv_reg36 <= slv_reg36;
|
||||
slv_reg37 <= slv_reg37;
|
||||
slv_reg38 <= slv_reg38;
|
||||
slv_reg39 <= slv_reg39;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement write response logic generation
|
||||
-- The write response and response valid signals are asserted by the slave
|
||||
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
|
||||
-- This marks the acceptance of address and indicates the status of
|
||||
-- write transaction.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_bvalid <= '0';
|
||||
axi_bresp <= "00"; --need to work more on the responses
|
||||
else
|
||||
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
|
||||
axi_bvalid <= '1';
|
||||
axi_bresp <= "00";
|
||||
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
|
||||
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arready generation
|
||||
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
|
||||
-- S_AXI_ARVALID is asserted. axi_awready is
|
||||
-- de-asserted when reset (active low) is asserted.
|
||||
-- The read address is also latched when S_AXI_ARVALID is
|
||||
-- asserted. axi_araddr is reset to zero on reset assertion.
|
||||
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_arready <= '0';
|
||||
axi_araddr <= (others => '1');
|
||||
else
|
||||
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
|
||||
-- indicates that the slave has acceped the valid read address
|
||||
axi_arready <= '1';
|
||||
-- Read Address latching
|
||||
axi_araddr <= S_AXI_ARADDR;
|
||||
else
|
||||
axi_arready <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement axi_arvalid generation
|
||||
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
|
||||
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
|
||||
-- data are available on the axi_rdata bus at this instance. The
|
||||
-- assertion of axi_rvalid marks the validity of read data on the
|
||||
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
|
||||
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
|
||||
-- cleared to zero on reset (active low).
|
||||
process (S_AXI_ACLK)
|
||||
begin
|
||||
if rising_edge(S_AXI_ACLK) then
|
||||
if S_AXI_ARESETN = '0' then
|
||||
axi_rvalid <= '0';
|
||||
axi_rresp <= "00";
|
||||
else
|
||||
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
|
||||
-- Valid read data is available at the read data bus
|
||||
axi_rvalid <= '1';
|
||||
axi_rresp <= "00"; -- 'OKAY' response
|
||||
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
|
||||
-- Read data is accepted by the master
|
||||
axi_rvalid <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Implement memory mapped register select and read logic generation
|
||||
-- Slave register read enable is asserted when valid address is available
|
||||
-- and the slave is ready to accept the read address.
|
||||
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
|
||||
|
||||
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
|
||||
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
|
||||
begin
|
||||
-- Address decoding for reading registers
|
||||
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
|
||||
case loc_addr is
|
||||
when b"000000" =>
|
||||
reg_data_out <= slv_reg0;
|
||||
when b"000001" =>
|
||||
reg_data_out <= slv_reg1;
|
||||
when b"000010" =>
|
||||
reg_data_out <= slv_reg2;
|
||||
when b"000011" =>
|
||||
reg_data_out <= slv_reg3;
|
||||
when b"000100" =>
|
||||
reg_data_out <= slv_reg4;
|
||||
when b"000101" =>
|
||||
reg_data_out <= slv_reg5;
|
||||
when b"000110" =>
|
||||
reg_data_out <= slv_reg6;
|
||||
when b"000111" =>
|
||||
reg_data_out <= slv_reg7;
|
||||
when b"001000" =>
|
||||
reg_data_out <= slv_reg8;
|
||||
when b"001001" =>
|
||||
reg_data_out <= slv_reg9;
|
||||
when b"001010" =>
|
||||
reg_data_out <= slv_reg10;
|
||||
when b"001011" =>
|
||||
reg_data_out <= slv_reg11;
|
||||
when b"001100" =>
|
||||
reg_data_out <= slv_reg12;
|
||||
when b"001101" =>
|
||||
reg_data_out <= slv_reg13;
|
||||
when b"001110" =>
|
||||
reg_data_out <= slv_reg14;
|
||||
when b"001111" =>
|
||||
reg_data_out <= slv_reg15;
|
||||
when b"010000" =>
|
||||
reg_data_out <= slv_reg16;
|
||||
when b"010001" =>
|
||||
reg_data_out <= slv_reg17;
|
||||
when b"010010" =>
|
||||
reg_data_out <= slv_reg18;
|
||||
when b"010011" =>
|
||||
reg_data_out <= slv_reg19;
|
||||
when b"010100" =>
|
||||
reg_data_out <= slv_reg20;
|
||||
when b"010101" =>
|
||||
reg_data_out <= slv_reg21;
|
||||
when b"010110" =>
|
||||
reg_data_out <= slv_reg22;
|
||||
when b"010111" =>
|
||||
reg_data_out <= slv_reg23;
|
||||
when b"011000" =>
|
||||
reg_data_out <= slv_reg24;
|
||||
when b"011001" =>
|
||||
reg_data_out <= slv_reg25;
|
||||
when b"011010" =>
|
||||
reg_data_out <= slv_reg26;
|
||||
when b"011011" =>
|
||||
reg_data_out <= slv_reg27;
|
||||
when b"011100" =>
|
||||
reg_data_out <= slv_reg28;
|
||||
when b"011101" =>
|
||||
reg_data_out <= slv_reg29;
|
||||
when b"011110" =>
|
||||
reg_data_out <= slv_reg30;
|
||||
when b"011111" =>
|
||||
reg_data_out <= slv_reg31;
|
||||
when b"100000" =>
|
||||
reg_data_out <= slv_reg32;
|
||||
when b"100001" =>
|
||||
reg_data_out <= slv_reg33;
|
||||
when b"100010" =>
|
||||
reg_data_out <= slv_reg34;
|
||||
when b"100011" =>
|
||||
reg_data_out <= slv_reg35;
|
||||
when b"100100" =>
|
||||
reg_data_out <= slv_reg36_in; --slv_reg36;
|
||||
when b"100101" =>
|
||||
reg_data_out <= slv_reg37_in; --slv_reg37;
|
||||
when b"100110" =>
|
||||
reg_data_out <= slv_reg38_in; --slv_reg38;
|
||||
when b"100111" =>
|
||||
reg_data_out <= slv_reg39_in; --slv_reg39;
|
||||
when others =>
|
||||
reg_data_out <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
-- Output register or memory read data
|
||||
process( S_AXI_ACLK ) is
|
||||
begin
|
||||
if (rising_edge (S_AXI_ACLK)) then
|
||||
if ( S_AXI_ARESETN = '0' ) then
|
||||
axi_rdata <= (others => '0');
|
||||
else
|
||||
if (slv_reg_rden = '1') then
|
||||
-- When there is a valid read address (S_AXI_ARVALID) with
|
||||
-- acceptance of read address by the slave (axi_arready),
|
||||
-- output the read dada
|
||||
-- Read address mux
|
||||
axi_rdata <= reg_data_out; -- register read data
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-- Add user logic here
|
||||
slv_reg0_out <= slv_reg0;
|
||||
slv_reg1_out <= slv_reg1;
|
||||
slv_reg2_out <= slv_reg2;
|
||||
slv_reg3_out <= slv_reg3;
|
||||
slv_reg4_out <= slv_reg4;
|
||||
slv_reg5_out <= slv_reg5;
|
||||
slv_reg6_out <= slv_reg6;
|
||||
slv_reg7_out <= slv_reg7;
|
||||
slv_reg8_out <= slv_reg8;
|
||||
slv_reg9_out <= slv_reg9;
|
||||
slv_reg10_out <= slv_reg10;
|
||||
slv_reg11_out <= slv_reg11;
|
||||
slv_reg12_out <= slv_reg12;
|
||||
slv_reg13_out <= slv_reg13;
|
||||
slv_reg14_out <= slv_reg14;
|
||||
slv_reg15_out <= slv_reg15;
|
||||
slv_reg16_out <= slv_reg16;
|
||||
slv_reg17_out <= slv_reg17;
|
||||
slv_reg18_out <= slv_reg18;
|
||||
slv_reg19_out <= slv_reg19;
|
||||
slv_reg20_out <= slv_reg20;
|
||||
slv_reg21_out <= slv_reg21;
|
||||
slv_reg22_out <= slv_reg22;
|
||||
slv_reg23_out <= slv_reg23;
|
||||
slv_reg24_out <= slv_reg24;
|
||||
slv_reg25_out <= slv_reg25;
|
||||
slv_reg26_out <= slv_reg26;
|
||||
slv_reg27_out <= slv_reg27;
|
||||
slv_reg28_out <= slv_reg28;
|
||||
slv_reg29_out <= slv_reg29;
|
||||
slv_reg30_out <= slv_reg30;
|
||||
slv_reg31_out <= slv_reg31;
|
||||
slv_reg32_out <= slv_reg32;
|
||||
slv_reg33_out <= slv_reg33;
|
||||
slv_reg34_out <= slv_reg34;
|
||||
slv_reg35_out <= slv_reg35;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- User logic ends
|
||||
|
||||
end arch_imp;
|
||||
+227
@@ -0,0 +1,227 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "adder_16signed_16signed_latency2",
|
||||
"component_reference": "xilinx.com:ip:c_addsub:12.0",
|
||||
"ip_revision": "16",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/adder_16signed_16signed_latency2",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "adder_16signed_16signed_latency2", "resolve_type": "user", "usage": "all" } ],
|
||||
"Implementation": [ { "value": "Fabric", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"B_Type": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"A_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Add_Mode": [ { "value": "Add", "resolve_type": "user", "usage": "all" } ],
|
||||
"Out_Width": [ { "value": "17", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Automatic", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"B_Constant": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"B_Value": [ { "value": "0000000000000000", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"CE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_In": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"C_Out": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Borrow_Sense": [ { "value": "Active_Low", "resolve_type": "user", "usage": "all" } ],
|
||||
"SCLR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SSET": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SINIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Bypass": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Bypass_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Sync_Ctrl_Priority": [ { "value": "Reset_Overrides_Set", "resolve_type": "user", "usage": "all" } ],
|
||||
"Sync_CE_Priority": [ { "value": "Sync_Overrides_CE", "resolve_type": "user", "usage": "all" } ],
|
||||
"Bypass_CE_Priority": [ { "value": "CE_Overrides_Bypass", "resolve_type": "user", "usage": "all" } ],
|
||||
"AINIT_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_WIDTH": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ADD_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_CONSTANT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "0000000000000000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_AINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SINIT_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BYPASS_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SCLR_OVERRIDES_SSET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_C_IN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_C_OUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_BORROW_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BYPASS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SSET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SINIT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "16" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/adder_16signed_16signed_latency2" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"A": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"CE": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"BYPASS": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
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|
||||
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Synchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Valid_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "Single_Programmable_Full_Threshold_Constant", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "512", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "511", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
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|
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||||
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|
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|
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|
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|
||||
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|
||||
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|
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|
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|
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|
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|
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+152
@@ -0,0 +1,152 @@
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||||
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|
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|
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|
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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+152
@@ -0,0 +1,152 @@
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "s_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "s_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "s_axis_tdata" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TVALID": [ { "physical_name": "m_axis_tvalid" } ],
|
||||
"TREADY": [ { "physical_name": "m_axis_tready" } ],
|
||||
"TDATA": [ { "physical_name": "m_axis_tdata" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,216 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity dds_cmd_gen is
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
fifo_rd_clk_in : in std_logic;
|
||||
fifo_rd_data_out : out std_logic_vector(31 downto 0);
|
||||
fifo_rd_dval_out : out std_logic;
|
||||
fifo_rd_rd_en_in : in std_logic;
|
||||
fifo_rd_empty_out : out std_logic;
|
||||
|
||||
rst_in : in std_logic
|
||||
);
|
||||
end entity dds_cmd_gen;
|
||||
|
||||
architecture imp of dds_cmd_gen is
|
||||
|
||||
signal fifo_wr_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal fifo_wr_en_r : std_logic := '0';
|
||||
|
||||
signal cmd_idx_r : integer range 0 to 4 := 0;
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
|
||||
type fsm_state is (IDLE, SEND, DONE);
|
||||
signal state_r : fsm_state := IDLE;
|
||||
signal state_cnt_r : integer := 0;
|
||||
|
||||
type array_32b_type is array (0 to 7) of std_logic_vector(31 downto 0);
|
||||
type dds_command_list is array (integer range <>) of array_32b_type;
|
||||
|
||||
-- **EXAMPLE SWEEP** Sweep from 1 MHz to 11 MHz in 100us using a 250MSps DAC rate. Then sweep backwards from 11 MHz to 1 MHz
|
||||
--
|
||||
-- Phase Inc Start = 2^32 * (1/250) = 17179869
|
||||
-- -- We will stop at 11 MHz, which corresponds to a Phase Inc Stop = 2^32 * (11/250) = 188978561
|
||||
-- -- Phase Inc Stop - Phase Inc Start = 188978561 - 17179869 = 171,798,692
|
||||
-- -- Thus, 171,798,692 is the TOTAL amount that must get added to the Phase Inc Start over the entire duration of the pulse.
|
||||
-- -- Number of Pulse Samples = 100us / 4ns = 25,000.
|
||||
-- -- Thus, we must linearly increase our initial phase increment (Phase Inc Start) by a total of 171,798,692 during the 25,000 sample pulse.
|
||||
-- -- Easiest solution is to update the Phase Increment every sample (DDS PHASE INC DWELL CNT = 0).
|
||||
-- -- DDS PHASE INCREMENT STEP = 171,798,692 / 25,000 = 6871.94768. We have to round this up/down so lets use 6872.
|
||||
--
|
||||
|
||||
|
||||
signal dds_command_set : dds_command_list(0 to 0) :=
|
||||
(
|
||||
-- WFM 0
|
||||
-- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 5MHz in 5uS -- = 2^32 * (desired freq / sample rate) = 2^32 * (5/250) = 85,899,345
|
||||
0 => (x"00000000", --RESERVED1
|
||||
x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
x"0000D6BF", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 85899345 - 17179869 = 68719476/1250 = 54,975 = 0x0000_D6BF
|
||||
x"00000000", --IDLE_SAMPLES
|
||||
x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
x"00000000", --PHASE_OFF
|
||||
x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
)
|
||||
-- -- WFM 1
|
||||
-- -- FREQUENCY SWEEP (DOWN-SWEEP) - sweep down from 6MHz to 1MHz in 5uS
|
||||
-- 1 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"00FEF391", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Stop - Phase Inc Start)/duration = 17179869 - 103079215 = -85899346/1250 = -68719 = 0x00FE_F391
|
||||
-- x"00000000", --IDLE_SAMPLES
|
||||
-- x"000004E2", --DDS_SAMPLES (~5 us) = duration / sample_rate = 5us/4ns = 1250 = 0x4e2
|
||||
-- x"0624DD2F", --PHASE_INC (~6 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (6/250) = 103079215 = 0x0624DD2F
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- ),
|
||||
-- -- WFM 2
|
||||
-- -- CW TONE
|
||||
-- 2 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"00000000", --DDS_PHASE_INC_STEP_SIZE (No step, continuous tone)
|
||||
-- x"00000000", --IDLE_SAMPLES
|
||||
-- x"000004E2", --DDS_SAMPLES (~5 us) - 0x4e2 = 1250 * 4nS = 5 uS
|
||||
---- x"000FFFFF", --DDS_SAMPLES (~5 us) - 0xFFFFF = 1048575 * 4nS = 4.1943 mSec
|
||||
---- x"00000E00", --DDS_SAMPLES (~5 us) - 0x00000E00 = 3584 * 4nS = 14.336 uSec
|
||||
---- x"000FFFFF", --DDS_SAMPLES (~5 us)
|
||||
-- x"0624DD2F", --PHASE_INC (~6 MHz)
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- ),
|
||||
-- -- WFM 3
|
||||
-- -- FREQUENCY SWEEP (UP-SWEEP) - sweep up from 1MHz to 10MHz in 10uS
|
||||
-- 3 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"0000F197", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us) (Phase Inc Start - Phase Inc Stop)/duration = 171798692 - 17179869 = 154618823/2500 = 61848 = 0x0000_F197
|
||||
-- x"000000FF", --IDLE_SAMPLES
|
||||
-- x"000009C4", --DDS_SAMPLES (~10 us) = duration / sample_rate = 10us/4ns = 2500 = 0x9C4
|
||||
-- x"010624DD", --PHASE_INC (~1 MHz) = 2^32 * (desired freq / sample rate) = 2^32 * (1/250) = 17179869 = 0x010624DD
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- ),
|
||||
-- -- WFM 4
|
||||
-- -- ??????
|
||||
-- 4 => (x"00000000", --RESERVED1
|
||||
-- x"00000000", --DDS_PHASE_INC_DWELL_TIME
|
||||
-- x"00000000", --DDS_PHASE_INC_STEP_SIZE (~1 MHz/us)
|
||||
-- x"00000000", --IDLE_SAMPLES
|
||||
-- x"00000000", --DDS_SAMPLES (~5 us)
|
||||
-- x"00000000", --PHASE_INC (~6 MHz)
|
||||
-- x"00000000", --PHASE_OFF
|
||||
-- x"00008000" --RESERVED_SWAP_SF -- Scale Factor = 1.0
|
||||
-- )
|
||||
);
|
||||
|
||||
|
||||
signal test_state_r : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
dds_command_set(0)(0) <= reserv1_in;
|
||||
dds_command_set(0)(1) <= dds_phase_inc_dwell_time_in;
|
||||
dds_command_set(0)(2) <= dds_phase_inc_step_size_in;
|
||||
dds_command_set(0)(3) <= idle_samples_in;
|
||||
dds_command_set(0)(4) <= dds_samples_in;
|
||||
dds_command_set(0)(5) <= phase_inc_in;
|
||||
dds_command_set(0)(6) <= phase_off_in;
|
||||
dds_command_set(0)(7) <= swap_sf_in;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if (rising_edge(clk_in)) then
|
||||
-- if (rst_in = '1') then
|
||||
-- cmd_idx_r <= 0;
|
||||
-- cmd_send_r <= '0';
|
||||
-- fifo_wr_en_r <= '0';
|
||||
-- state_cnt_r <= 0;
|
||||
-- state_r <= IDLE;
|
||||
-- else
|
||||
cmd_send_r <= cmd_send_in;
|
||||
fifo_wr_en_r <= '0';
|
||||
|
||||
case (state_r) is
|
||||
when IDLE =>
|
||||
if (cmd_send_in = '1' and cmd_send_r = '0') then
|
||||
cmd_idx_r <= 0;--conv_integer(unsigned(cmd_idx_in));
|
||||
state_cnt_r <= 0;
|
||||
state_r <= SEND;
|
||||
else
|
||||
state_r <= IDLE;
|
||||
end if;
|
||||
|
||||
when SEND =>
|
||||
if (state_cnt_r = 8) then
|
||||
state_r <= DONE;
|
||||
else
|
||||
fifo_wr_data_r <= dds_command_set(0)(state_cnt_r);
|
||||
fifo_wr_en_r <= '1';
|
||||
state_cnt_r <= state_cnt_r + 1;
|
||||
state_r <= SEND;
|
||||
end if;
|
||||
|
||||
when DONE =>
|
||||
state_r <= IDLE;
|
||||
|
||||
when others =>
|
||||
state_r <= IDLE;
|
||||
|
||||
end case;
|
||||
-- end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
test_state_r <= "00" when state_r = IDLE else
|
||||
"01" when state_r = SEND else
|
||||
"10" when state_r = DONE else
|
||||
"11";
|
||||
|
||||
-- i_ila_1 : entity work.ila_2
|
||||
-- port map (
|
||||
-- clk => clk_in,
|
||||
-- probe0 => test_state_r, -- 2
|
||||
-- probe1 => conv_std_logic_vector(state_cnt_r, 4), -- 4
|
||||
-- probe2 => fifo_wr_data_r, -- 32
|
||||
-- probe3(0) => fifo_wr_en_r, -- 1
|
||||
-- probe4(0) => cmd_send_in, -- 1
|
||||
-- probe5(0) => cmd_send_r -- 1
|
||||
-- );
|
||||
|
||||
i_pipe_in_ch1_fifo : entity work.afifo_32b_1024_pf512_latency1
|
||||
port map(
|
||||
wr_clk => clk_in,
|
||||
din => fifo_wr_data_r,
|
||||
wr_en => fifo_wr_en_r,
|
||||
full => open,
|
||||
overflow => open,
|
||||
|
||||
rd_clk => fifo_rd_clk_in,
|
||||
dout => fifo_rd_data_out,
|
||||
valid => fifo_rd_dval_out,
|
||||
rd_en => fifo_rd_rd_en_in,
|
||||
empty => fifo_rd_empty_out,
|
||||
|
||||
underflow => open,
|
||||
prog_full => open,
|
||||
wr_rst_busy => open,
|
||||
rd_rst_busy => open,
|
||||
srst => rst_in
|
||||
);
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,365 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "dds_latency10",
|
||||
"component_reference": "xilinx.com:ip:dds_compiler:6.0",
|
||||
"ip_revision": "23",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/dds_latency10",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "dds_latency10", "resolve_type": "user", "usage": "all" } ],
|
||||
"PartsPresent": [ { "value": "SIN_COS_LUT_only", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"DDS_Clock_Rate": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Channels": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Mode_of_Operation": [ { "value": "Standard", "resolve_type": "user", "usage": "all" } ],
|
||||
"Modulus": [ { "value": "9", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Parameter_Entry": [ { "value": "Hardware_Parameters", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Spurious_Free_Dynamic_Range": [ { "value": "45", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Frequency_Resolution": [ { "value": "0.4", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"Noise_Shaping": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Output_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Phase_Increment": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Resync": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Phase_offset": [ { "value": "Streaming", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Selection": [ { "value": "Sine_and_Cosine", "resolve_type": "user", "usage": "all" } ],
|
||||
"Negative_Sine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Negative_Cosine": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Amplitude_Mode": [ { "value": "Full_Range", "resolve_type": "user", "usage": "all" } ],
|
||||
"Memory_Type": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"Optimization_Goal": [ { "value": "Auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"DSP48_Use": [ { "value": "Minimal", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_Phase_Out": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"DATA_Has_TLAST": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_TREADY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"S_PHASE_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_PHASE_TUSER_Width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M_DATA_Has_TUSER": [ { "value": "Not_Required", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"M_PHASE_Has_TUSER": [ { "value": "Not_Required", "resolve_type": "user", "usage": "all" } ],
|
||||
"S_CONFIG_Sync_Mode": [ { "value": "On_Vector", "resolve_type": "user", "usage": "all" } ],
|
||||
"OUTPUT_FORM": [ { "value": "Twos_Complement", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency_Configuration": [ { "value": "Configurable", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Latency": [ { "value": "10", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Has_ARESETn": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Has_ACLKEN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Output_Frequency1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles1": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"POFF1": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Frequency2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PINC2": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"Phase_Offset_Angles2": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
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|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
|
||||
}
|
||||
},
|
||||
"aclk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"aresetn_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
},
|
||||
"aclken_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "aclken" } ]
|
||||
}
|
||||
},
|
||||
"M_AXIS_DATA": {
|
||||
"vlnv": "xilinx.com:interface:axis:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,414 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_2x_top - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- Supports single channel mode or dual channel (summed) mode.
|
||||
-- When using dual channel mode, the module hangs after the shortest of the
|
||||
-- two pulse streams completes. Ideally, both streams will be equal length.
|
||||
--
|
||||
-- For each channel:
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_2x_top is
|
||||
generic (
|
||||
DDS_POSITION : integer := 8
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
mode_in : in std_logic; -- 0=single, 1=dual
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
fifo1_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo1_dval_in : in std_logic;
|
||||
fifo1_empty_in : in std_logic;
|
||||
fifo1_rden_out : out std_logic;
|
||||
fifo2_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo2_dval_in : in std_logic;
|
||||
fifo2_empty_in : in std_logic;
|
||||
fifo2_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
overflow_out : out std_logic_vector(1 downto 0);
|
||||
underflow_out : out std_logic_vector(1 downto 0);
|
||||
i_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
q_max_abs_out : out std_logic_vector(15 downto 0);
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_2x_top is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component sfifo_32b_1024_pf992_latency1
|
||||
port(
|
||||
clk : in std_logic;
|
||||
srst : in std_logic;
|
||||
din : in std_logic_vector(31 downto 0);
|
||||
wr_en : in std_logic;
|
||||
rd_en : in std_logic;
|
||||
dout : out std_logic_vector(31 downto 0);
|
||||
full : out std_logic;
|
||||
overflow : out std_logic;
|
||||
empty : out std_logic;
|
||||
underflow : out std_logic;
|
||||
prog_full : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component adder_16signed_16signed_latency2
|
||||
port(
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
clk : in std_logic;
|
||||
ce : in std_logic;
|
||||
bypass : in std_logic;
|
||||
s : out std_logic_vector(16 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal rst_r : std_logic := '1';
|
||||
signal mode_n_r : std_logic := '1'; -- 1=single, 0=dual
|
||||
signal scale_r : std_logic_vector(15 downto 0) := x"8000";
|
||||
signal pulse_fifo_dval_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse_adder_dval_r : std_logic := '0';
|
||||
signal pulse_adder_ce : std_logic;
|
||||
signal pulse_data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pulse_dval_r : std_logic := '0';
|
||||
signal adder_dval_r : std_logic := '0';
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
signal pulse1_mult_dval_r : std_logic := '0';
|
||||
signal pulse1_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse1_mult_ce : std_logic;
|
||||
signal pulse1_data : std_logic_vector(31 downto 0);
|
||||
signal pulse1_dval : std_logic;
|
||||
signal pulse1_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_overflow : std_logic;
|
||||
signal pulse1_fifo_empty : std_logic;
|
||||
signal pulse1_fifo_underflow : std_logic;
|
||||
signal pulse1_fifo_progfull : std_logic;
|
||||
signal pulse1_fifo_rden : std_logic;
|
||||
signal pulse1_fifo_rden_r : std_logic := '0';
|
||||
signal pulse1_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse1_fifo_dout_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal adder1_s : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder1_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal i_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo1_underflow_r : std_logic := '0';
|
||||
signal fifo1_overflow_r : std_logic := '0';
|
||||
|
||||
signal pulse2_mult_dval_r : std_logic := '0';
|
||||
signal pulse2_mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal pulse2_mult_ce : std_logic;
|
||||
signal pulse2_data : std_logic_vector(31 downto 0);
|
||||
signal pulse2_dval : std_logic;
|
||||
signal pulse2_data_scaled : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_overflow : std_logic;
|
||||
signal pulse2_fifo_empty : std_logic;
|
||||
signal pulse2_fifo_underflow : std_logic;
|
||||
signal pulse2_fifo_progfull : std_logic;
|
||||
signal pulse2_fifo_rden : std_logic;
|
||||
signal pulse2_fifo_dout : std_logic_vector(31 downto 0);
|
||||
signal pulse2_fifo_dout_r : std_logic_vector(31 downto 0);
|
||||
signal adder2_s : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r : std_logic_vector(16 downto 0);
|
||||
signal adder2_s_r1 : std_logic_vector(15 downto 0);
|
||||
signal q_abs_max_r : unsigned(15 downto 0);
|
||||
signal fifo2_underflow_r : std_logic := '0';
|
||||
signal fifo2_overflow_r : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
data_out <= pulse_data_r;
|
||||
dval_out <= pulse_dval_r;
|
||||
i_max_abs_out <= std_logic_vector(i_abs_max_r);
|
||||
q_max_abs_out <= std_logic_vector(q_abs_max_r);
|
||||
overflow_out <= fifo2_overflow_r & fifo1_overflow_r;
|
||||
underflow_out <= fifo2_underflow_r & fifo1_underflow_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
rst_r <= rst_in;
|
||||
scale_r <= scale_in;
|
||||
mode_n_r <= not(mode_in);
|
||||
holdoff_r <= holdoff_in;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
pulse1_mult_dval_r <= pulse1_mult_ce_pipe_r(1);
|
||||
pulse1_mult_ce_pipe_r(1 downto 0) <= pulse1_mult_ce_pipe_r(0) & pulse1_dval;
|
||||
pulse2_mult_dval_r <= pulse2_mult_ce_pipe_r(1);
|
||||
pulse2_mult_ce_pipe_r(1 downto 0) <= pulse2_mult_ce_pipe_r(0) & pulse2_dval;
|
||||
pulse_fifo_dval_r(1 downto 0) <= pulse_fifo_dval_r(0) & pulse1_fifo_rden_r;
|
||||
pulse_adder_dval_r <= pulse_fifo_dval_r(1);
|
||||
pulse1_fifo_rden_r <= pulse1_fifo_rden;
|
||||
pulse1_fifo_dout_r <= pulse1_fifo_dout;
|
||||
pulse2_fifo_dout_r <= pulse2_fifo_dout;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
pulse1_mult_ce <= pulse1_mult_ce_pipe_r(1) or pulse1_mult_ce_pipe_r(0) or pulse1_dval;
|
||||
pulse2_mult_ce <= pulse2_mult_ce_pipe_r(1) or pulse2_mult_ce_pipe_r(0) or pulse2_dval;
|
||||
|
||||
pulse1_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
not(pulse1_fifo_empty) and not(holdoff_r);
|
||||
|
||||
pulse2_fifo_rden <= not(pulse1_fifo_empty) and not(pulse2_fifo_empty) and not(holdoff_r) when mode_n_r = '0' else
|
||||
'0';
|
||||
|
||||
pulse_adder_ce <= pulse_fifo_dval_r(1) or pulse_fifo_dval_r(0);
|
||||
|
||||
i_dds_pulse1_gen : entity work.dds_pulse_gen
|
||||
generic map (
|
||||
DDS_POSITION => DDS_POSITION
|
||||
)
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo1_data_in,
|
||||
fifo_dval_in => fifo1_dval_in,
|
||||
fifo_empty_in => fifo1_empty_in,
|
||||
fifo_rden_out => fifo1_rden_out,
|
||||
holdoff_in => pulse1_fifo_progfull,
|
||||
data_out => pulse1_data,
|
||||
dval_out => pulse1_dval
|
||||
);
|
||||
|
||||
i_pulse1_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse1_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse1_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse1_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse1_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse1_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse1_data_scaled,
|
||||
wr_en => pulse1_mult_dval_r,
|
||||
rd_en => pulse1_fifo_rden,
|
||||
dout => pulse1_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse1_fifo_overflow,
|
||||
empty => pulse1_fifo_empty,
|
||||
underflow => pulse1_fifo_underflow,
|
||||
prog_full => pulse1_fifo_progfull
|
||||
);
|
||||
|
||||
i_dds_pulse2_gen : entity work.dds_pulse_gen
|
||||
generic map (
|
||||
DDS_POSITION => DDS_POSITION
|
||||
)
|
||||
port map(
|
||||
clk_in => clk_in,
|
||||
rst_in => rst_r,
|
||||
fifo_data_in => fifo2_data_in,
|
||||
fifo_dval_in => fifo2_dval_in,
|
||||
fifo_empty_in => fifo2_empty_in,
|
||||
fifo_rden_out => fifo2_rden_out,
|
||||
holdoff_in => pulse2_fifo_progfull,
|
||||
data_out => pulse2_data,
|
||||
dval_out => pulse2_dval
|
||||
);
|
||||
|
||||
i_pulse2_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_pulse2_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => pulse2_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => pulse2_mult_ce,
|
||||
sclr => '0',
|
||||
p => pulse2_data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
i_pulse2_fifo : sfifo_32b_1024_pf992_latency1
|
||||
port map(
|
||||
clk => clk_in,
|
||||
srst => rst_r,
|
||||
din => pulse2_data_scaled,
|
||||
wr_en => pulse2_mult_dval_r,
|
||||
rd_en => pulse2_fifo_rden,
|
||||
dout => pulse2_fifo_dout,
|
||||
full => open,
|
||||
overflow => pulse2_fifo_overflow,
|
||||
empty => pulse2_fifo_empty,
|
||||
underflow => pulse2_fifo_underflow,
|
||||
prog_full => pulse2_fifo_progfull
|
||||
);
|
||||
|
||||
i_pulse_adder1 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(15 downto 0),
|
||||
b => pulse1_fifo_dout_r(15 downto 0),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder1_s
|
||||
);
|
||||
|
||||
i_pulse_adder2 : adder_16signed_16signed_latency2
|
||||
port map(
|
||||
a => pulse2_fifo_dout_r(31 downto 16),
|
||||
b => pulse1_fifo_dout_r(31 downto 16),
|
||||
clk => clk_in,
|
||||
ce => pulse_adder_ce,
|
||||
bypass => mode_n_r, -- when set to '1', b input proceeds to s output
|
||||
s => adder2_s
|
||||
);
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
adder1_s_r <= adder1_s;
|
||||
adder2_s_r <= adder2_s;
|
||||
adder_dval_r <= pulse_adder_dval_r;
|
||||
pulse_dval_r <= adder_dval_r;
|
||||
if(adder_dval_r = '1')then
|
||||
case adder1_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(15 downto 0) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(15 downto 0) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(15 downto 0) <= adder1_s_r(16) & adder1_s_r(14 downto 0);
|
||||
end case;
|
||||
case adder2_s_r(16 downto 15) is
|
||||
when "01" => --positive overflow
|
||||
pulse_data_r(31 downto 16) <= x"7FFF";
|
||||
when "10" => --negative overflow
|
||||
pulse_data_r(31 downto 16) <= x"8000";
|
||||
when others =>
|
||||
pulse_data_r(31 downto 16) <= adder2_s_r(16) & adder2_s_r(14 downto 0);
|
||||
end case;
|
||||
end if;
|
||||
if(rst_r = '1')then
|
||||
--adder_dval_r <= '0';
|
||||
--pulse_dval_r <= '0';
|
||||
i_abs_max_r <= (others => '0');
|
||||
q_abs_max_r <= (others => '0');
|
||||
fifo1_overflow_r <= '0';
|
||||
fifo1_underflow_r <= '0';
|
||||
fifo2_overflow_r <= '0';
|
||||
fifo2_underflow_r <= '0';
|
||||
else
|
||||
--adder_dval_r <= pulse_adder_dval_r;
|
||||
--pulse_dval_r <= adder_dval_r;
|
||||
if(pulse1_fifo_overflow = '1')then
|
||||
fifo1_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse1_fifo_underflow = '1')then
|
||||
fifo1_underflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_overflow = '1')then
|
||||
fifo2_overflow_r <= '1';
|
||||
end if;
|
||||
if(pulse2_fifo_underflow = '1')then
|
||||
fifo2_underflow_r <= '1';
|
||||
end if;
|
||||
if(adder_dval_r = '1')then
|
||||
-- if(abs(signed(adder1_s_r)) > i_abs_max_r)then
|
||||
-- i_abs_max_r <= abs(signed(adder1_s_r));
|
||||
-- end if;
|
||||
if(adder1_s_r(16) = '0')then
|
||||
adder1_s_r1 <= adder1_s_r(15 downto 0);
|
||||
else
|
||||
adder1_s_r1 <= not(adder1_s_r(15 downto 0));
|
||||
end if;
|
||||
|
||||
-- if(abs(signed(adder2_s_r)) > q_abs_max_r)then
|
||||
-- q_abs_max_r <= abs(signed(adder2_s_r));
|
||||
-- end if;
|
||||
if(adder2_s_r(16) = '0')then
|
||||
adder2_s_r1 <= adder2_s_r(15 downto 0);
|
||||
else
|
||||
adder2_s_r1 <= not(adder2_s_r(15 downto 0));
|
||||
end if;
|
||||
end if;
|
||||
if(pulse_dval_r = '1')then
|
||||
if(unsigned(adder1_s_r1) > i_abs_max_r)then
|
||||
i_abs_max_r <= unsigned(adder1_s_r1);
|
||||
end if;
|
||||
if(unsigned(adder2_s_r1) > q_abs_max_r)then
|
||||
q_abs_max_r <= unsigned(adder2_s_r1);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,509 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer: Jason M. Blevins
|
||||
--
|
||||
-- Create Date: 19:38:12 11/10/2016
|
||||
-- Design Name:
|
||||
-- Module Name: dds_pulse_gen - behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Revision 0.02 - Added Sweep Functionality 10-17-2017
|
||||
-- Additional Comments:
|
||||
-- * All information is proprietary/confidential *
|
||||
--
|
||||
-- A 256-bit control word (32x8 right shifted in) is read from an external FIFO.
|
||||
-- The control word contains all information needed to create a pulse
|
||||
--
|
||||
-- RESERVED = fifo_data_r(255 downto 241) -- 15-bits
|
||||
-- SWAP IQ CHANELS = fifo_data_r(240) -- 1-bit set to '1' for negative frequencies
|
||||
-- SCALE FACTOR TO SCALE OUTPUT AMPLITUDE = fifo_data_r(239 downto 224) -- 16-bits, (0,1], full-scale = 1.000000000000000
|
||||
-- DDS PHASE OFFSET = fifo_data_r(223 downto 192) -- 32-bits, reserved, set to 0x0000_0000
|
||||
-- DDS PHASE INCREMENT = fifo_data_r(191 downto 160) -- 32-bits
|
||||
-- # DDS SAMPLES = fifo_data_r(159 downto 128) -- 32-bits
|
||||
-- # MIDPOINT SAMPLES PRIOR TO PULSE = fifo_data_r(127 downto 96) -- 32-bits
|
||||
-- RESERVED = fifo_data_r(95 downto 88) -- 8-bit
|
||||
-- DDS PHASE INCREMENT STEP = fifo_data_r(87 downto 64) -- 24-bits (2's complement SIGNED !!)
|
||||
-- RESERVED = fifo_data_r(63 downto 48) -- 16-bits
|
||||
-- DDS PHASE INCREMENT DWELL = fifo_data_r(47 downto 32) -- 16-bits
|
||||
-- RESERVED = fifo_data_r(31 downto 0) -- 32-bits
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
--Library UNIMACRO;
|
||||
--use UNIMACRO.vcomponents.all;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity dds_pulse_gen is
|
||||
generic (
|
||||
DDS_POSITION : integer := 8
|
||||
);
|
||||
port(
|
||||
clk_in : in std_logic;
|
||||
rst_in : in std_logic;
|
||||
fifo_data_in : in std_logic_vector(31 downto 0);
|
||||
fifo_dval_in : in std_logic;
|
||||
fifo_empty_in : in std_logic;
|
||||
fifo_rden_out : out std_logic;
|
||||
holdoff_in : in std_logic;
|
||||
data_out : out std_logic_vector(31 downto 0);
|
||||
dval_out : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture mixed of dds_pulse_gen is
|
||||
|
||||
component mult_16signed_x_16unsigned_latency3
|
||||
port(
|
||||
clk : in std_logic;
|
||||
a : in std_logic_vector(15 downto 0);
|
||||
b : in std_logic_vector(15 downto 0);
|
||||
ce : in std_logic;
|
||||
sclr : in std_logic;
|
||||
p : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
-- component dds_latency10
|
||||
-- port(
|
||||
-- -- ce : in std_logic;
|
||||
-- -- clk : in std_logic;
|
||||
-- -- sclr : in std_logic;
|
||||
-- -- pinc_in : in std_logic_vector(31 downto 0);
|
||||
-- -- poff_in : in std_logic_vector(31 downto 0);
|
||||
-- -- rdy : out std_logic;
|
||||
-- -- cosine : out std_logic_vector(15 downto 0);
|
||||
-- -- sine : out std_logic_vector(15 downto 0)
|
||||
-- aclk : IN STD_LOGIC;
|
||||
-- aclken : IN STD_LOGIC;
|
||||
-- aresetn : IN STD_LOGIC;
|
||||
-- s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
-- s_axis_phase_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
-- m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
-- m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
-- );
|
||||
-- end component;
|
||||
|
||||
component addsub
|
||||
port (
|
||||
a : in std_logic_vector(31 downto 0); -- unsigned
|
||||
b : in std_logic_vector(23 downto 0); -- signed
|
||||
--clk : in std_logic;
|
||||
s : out std_logic_vector(31 downto 0) -- latency=0 ?? Not practical in HW, design should be updated to allow for latency.
|
||||
);
|
||||
end component;
|
||||
|
||||
constant MIDPOINT : std_logic_vector(31 downto 0) := x"00000000";
|
||||
|
||||
type state_type is (s0, s0a, s0b, s0c, s1, s2, s3);
|
||||
signal state : state_type;
|
||||
signal state_r : state_type;
|
||||
signal rst_r : std_logic := '1';
|
||||
signal rstn_r : std_logic := '0';
|
||||
|
||||
signal cnt1_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt1 : unsigned(3 downto 0);
|
||||
signal cnt2_r : unsigned(2 downto 0) := "000";
|
||||
signal cnt2 : unsigned(2 downto 0);
|
||||
signal cnt3_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt3 : unsigned(31 downto 0);
|
||||
signal cnt4_r : unsigned(31 downto 0) := x"00000000";
|
||||
signal cnt4 : unsigned(31 downto 0);
|
||||
signal cnt5_r : unsigned(3 downto 0) := "0000";
|
||||
signal cnt5 : unsigned(3 downto 0);
|
||||
signal fifo_data_ce : std_logic;
|
||||
signal fifo_data_r : std_logic_vector(255 downto 0) := (others => '0');
|
||||
signal fifo_rden : std_logic;
|
||||
--signal fifo_rden_r : std_logic := '0';
|
||||
signal dval_r : std_logic := '0';
|
||||
signal dval : std_logic;
|
||||
signal dds_data : std_logic_vector(31 downto 0);
|
||||
signal data : std_logic_vector(31 downto 0);
|
||||
signal data_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal idle_sample_cnt_r : unsigned(31 downto 0) := (others => '0');
|
||||
signal idle_sample_cnt_r1 : unsigned(31 downto 0) := (others => '0');
|
||||
signal dds_sample_cnt_r : unsigned(31 downto 0) := (others => '0');
|
||||
signal dds_sample_cnt_r1 : unsigned(31 downto 0) := (others => '0');
|
||||
signal phase_inc_init_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal swap_r : std_logic := '0';
|
||||
signal scale_r : std_logic_vector(15 downto 0);
|
||||
signal mult_dval_r : std_logic := '0';
|
||||
signal data_swap_scaled : std_logic_vector(31 downto 0);
|
||||
signal data_scaled : std_logic_vector(31 downto 0);
|
||||
signal dds_ce : std_logic;
|
||||
signal dds_rst : std_logic;
|
||||
signal dds_rdy : std_logic;
|
||||
signal mult_ce : std_logic;
|
||||
signal mult_ce_pipe_r : std_logic_vector(1 downto 0) := "00";
|
||||
signal holdoff_r : std_logic;
|
||||
|
||||
--signal phase_inc_mux_sel : std_logic;
|
||||
signal phase_inc_update_en : std_logic;
|
||||
--signal phase_inc_mux : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_inc_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
-- signal phase_inc_r1 : std_logic_vector(63 downto 0) := (others => '0');
|
||||
signal phase_inc_r1 : std_logic_vector(15 downto 0) := (others => '0');
|
||||
|
||||
signal phase_inc_step_r : std_logic_vector(23 downto 0) := (others => '0');
|
||||
signal phase_inc_dwell_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt_r : unsigned(15 downto 0) := x"0000";
|
||||
signal phase_inc_dwell_cnt : unsigned(15 downto 0);
|
||||
signal phase_inc_addsub : std_logic_vector(31 downto 0);
|
||||
signal rstn : std_logic;
|
||||
|
||||
|
||||
signal phase_offset : std_logic_vector(31 downto 0);
|
||||
signal phase_acc_addsub : std_logic_vector(31 downto 0);
|
||||
|
||||
signal phase_acc : std_logic_vector(31 downto 0);
|
||||
signal phase_acc_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal phase_step_eff1 : std_logic_vector(31 downto 0);
|
||||
signal phase_step_eff2 : std_logic_vector(31 downto 0);
|
||||
signal phase_step_eff3 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal phase0_32 : std_logic_vector(31 downto 0);
|
||||
signal phase1_32 : std_logic_vector(31 downto 0);
|
||||
signal phase2_32 : std_logic_vector(31 downto 0);
|
||||
signal phase3_32 : std_logic_vector(31 downto 0);
|
||||
|
||||
|
||||
signal dds_phase0 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase2 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase3 : std_logic_vector(31 downto 0);
|
||||
|
||||
signal phase2_32_i : std_logic_vector(31 downto 0);
|
||||
signal phase2_32_i_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
phase_step_eff1 <= phase_inc_r(31) & phase_inc_r(31) & phase_inc_r(31 downto 2); -- phase_inc/4
|
||||
phase_step_eff2 <= phase_inc_r(31) & phase_inc_r(31 downto 1); --2*phase_inc/4
|
||||
-- phase_step_eff3 <= phase_step_eff2 + phase_step_eff1; --2*phase_inc/4 + phase_step_eff1
|
||||
|
||||
i_addsub : addsub
|
||||
port map(
|
||||
a => phase_inc_r,
|
||||
b => phase_inc_step_r,
|
||||
--clk => clk_in,
|
||||
s => phase_inc_addsub
|
||||
);
|
||||
|
||||
i_addsub_acc : entity work.addsub_32x32
|
||||
port map(
|
||||
a => phase_acc_r,
|
||||
b => phase_inc_r,
|
||||
--clk => clk_in,
|
||||
s => phase_acc_addsub
|
||||
);
|
||||
|
||||
phase0_32 <= phase_acc_r;
|
||||
|
||||
i_addsub_1 : entity work.addsub_32x32
|
||||
port map(
|
||||
a => phase_acc_r,
|
||||
b => phase_step_eff1,
|
||||
--clk => clk_in,
|
||||
s => phase1_32
|
||||
);
|
||||
|
||||
i_addsub_2 : entity work.addsub_32x32
|
||||
port map(
|
||||
a => phase_acc_r,
|
||||
b => phase_step_eff2,
|
||||
--clk => clk_in,
|
||||
s => phase2_32
|
||||
);
|
||||
|
||||
i_addsub_3 : entity work.addsub_32x32
|
||||
port map(
|
||||
a => phase2_32,
|
||||
b => phase_step_eff1,
|
||||
--clk => clk_in,
|
||||
s => phase3_32 -- phase_step_eff3
|
||||
);
|
||||
|
||||
i_generate_phase_offset_0: if DDS_POSITION = 0 generate
|
||||
phase_offset <= phase0_32;
|
||||
end generate;
|
||||
|
||||
i_generate_phase_offset_1: if DDS_POSITION = 1 generate
|
||||
phase_offset <= phase1_32;
|
||||
end generate;
|
||||
|
||||
i_generate_phase_offset_2: if DDS_POSITION = 2 generate
|
||||
phase_offset <= phase2_32;
|
||||
end generate;
|
||||
|
||||
i_generate_phase_offset_3: if DDS_POSITION = 3 generate
|
||||
phase_offset <= phase3_32;
|
||||
end generate;
|
||||
|
||||
|
||||
fifo_rden_out <= fifo_rden;--fifo_rden_r;
|
||||
data_out <= data_r;
|
||||
dval_out <= dval_r;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
if(rst_r = '1')then
|
||||
state_r <= s0;
|
||||
cnt1_r <= (others => '0');
|
||||
cnt2_r <= (others => '0');
|
||||
cnt3_r <= (others => '0');
|
||||
cnt4_r <= (others => '0');
|
||||
cnt5_r <= (others => '0');
|
||||
phase_inc_dwell_cnt_r <= (others => '0');
|
||||
else
|
||||
state_r <= state;
|
||||
cnt1_r <= cnt1;
|
||||
cnt2_r <= cnt2;
|
||||
cnt3_r <= cnt3;
|
||||
cnt4_r <= cnt4;
|
||||
cnt5_r <= cnt5;
|
||||
phase_inc_dwell_cnt_r <= phase_inc_dwell_cnt;
|
||||
end if;
|
||||
|
||||
if(fifo_data_ce = '1')then
|
||||
fifo_data_r <= fifo_data_in & fifo_data_r(255 downto 32);--fifo_data_r(223 downto 0) & fifo_data_in;
|
||||
end if;
|
||||
rst_r <= rst_in;
|
||||
rstn_r <= not(rst_in);
|
||||
dval_r <= dval;
|
||||
-- phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
dds_sample_cnt_r <= unsigned(fifo_data_r(159 downto 128));
|
||||
dds_sample_cnt_r1 <= dds_sample_cnt_r;
|
||||
swap_r <= fifo_data_r(240);
|
||||
scale_r <= fifo_data_r(239 downto 224);
|
||||
idle_sample_cnt_r <= unsigned(fifo_data_r(127 downto 96));
|
||||
idle_sample_cnt_r1 <= idle_sample_cnt_r;
|
||||
phase_inc_step_r <= fifo_data_r(87 downto 64);
|
||||
phase_inc_dwell_r <= unsigned(fifo_data_r(47 downto 32));
|
||||
data_r <= data;
|
||||
holdoff_r <= holdoff_in;
|
||||
phase_inc_r <= phase_inc;
|
||||
phase_acc_r <= phase_acc;
|
||||
phase2_32_i_r <= phase2_32_i;
|
||||
|
||||
if(phase_inc_update_en = '1')then
|
||||
-- phase_inc_r1 <= phase_offset & phase_inc_r;
|
||||
phase_inc_r1 <= phase_offset(31 downto 16);
|
||||
-- phase_inc_r1 <= x"0000" & phase_offset(31 downto 16) & phase_inc_r; --x"0" &
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
phase_inc_init_r <= fifo_data_r(191 downto 160);
|
||||
|
||||
-- FSM next-state & output process
|
||||
process(state_r, cnt1_r, cnt2_r, cnt3_r, cnt4_r, cnt5_r, holdoff_r, fifo_empty_in, fifo_dval_in, phase_inc_init_r, phase_inc_r, phase_acc_r, phase_acc_addsub, phase2_32,
|
||||
mult_dval_r, data_swap_scaled, idle_sample_cnt_r1, dds_sample_cnt_r1, phase_inc_dwell_r, phase_inc_dwell_cnt_r, phase_inc_addsub)
|
||||
begin
|
||||
--defaults
|
||||
fifo_rden <= '0';
|
||||
cnt1 <= cnt1_r;
|
||||
cnt2 <= cnt2_r;
|
||||
cnt3 <= cnt3_r;
|
||||
cnt4 <= cnt4_r;
|
||||
cnt5 <= cnt5_r;
|
||||
state <= state_r;
|
||||
dds_ce <= '0';
|
||||
dds_rst <= '1';
|
||||
dval <= mult_dval_r;
|
||||
data <= data_swap_scaled;
|
||||
fifo_data_ce <= '0';
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r;
|
||||
phase_inc <= phase_inc_r;
|
||||
phase_inc_update_en <= '0';
|
||||
phase_acc <= phase_acc_r;
|
||||
phase2_32_i <= phase2_32_i_r;
|
||||
|
||||
case state_r is
|
||||
|
||||
when s0 =>
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
if(fifo_empty_in = '0' and cnt1_r < 8)then
|
||||
fifo_rden <= '1';
|
||||
cnt1 <= cnt1_r +1;
|
||||
end if;
|
||||
if(fifo_dval_in = '1')then
|
||||
fifo_data_ce <= '1';
|
||||
if(cnt2_r < 7)then
|
||||
cnt2 <= cnt2_r +1;
|
||||
else
|
||||
cnt2 <= (others => '0');
|
||||
cnt1 <= (others => '0');
|
||||
state <= s0a;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0a =>
|
||||
state <= s0b;--s1;
|
||||
phase_inc <= phase_inc_init_r;
|
||||
phase_acc <= phase_acc_addsub;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
when s0b =>
|
||||
state <= s1;
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
phase_acc <= phase_acc_addsub;
|
||||
phase2_32_i <= phase2_32;
|
||||
|
||||
-- This state is needed to clock the input shift reg data into next set of regs.
|
||||
-- Possibly can be removed to decrease pulse param processing cycles.
|
||||
-- when s0c =>
|
||||
-- state <= s1;
|
||||
-- phase_inc_update_en <= '1';
|
||||
-- phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
|
||||
|
||||
-- Insert midpoint (idle) samples that preceed the pulse.
|
||||
when s1 =>
|
||||
data <= MIDPOINT;
|
||||
if(cnt3_r < idle_sample_cnt_r1)then
|
||||
if(holdoff_r = '0')then
|
||||
cnt3 <= cnt3_r +1;
|
||||
dval <= '1';
|
||||
end if;
|
||||
else
|
||||
cnt3 <= (others => '0');
|
||||
if(dds_sample_cnt_r1 > 0)then
|
||||
state <= s2;
|
||||
else
|
||||
state <= s0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- Turn on DDS for requested number of samples.
|
||||
when s2 =>
|
||||
dds_rst <= '0';
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
else
|
||||
phase_inc_dwell_cnt <= (others => '0');
|
||||
phase_inc_update_en <= '1';
|
||||
phase_inc <= phase_inc_addsub;--phase_inc_r + phase_inc_step_r;
|
||||
phase_acc <= phase_acc_addsub;
|
||||
phase2_32_i <= phase2_32;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
if(cnt4_r < dds_sample_cnt_r1)then
|
||||
cnt4 <= cnt4_r +1;
|
||||
else
|
||||
cnt4 <= (others => '0');
|
||||
state <= s3;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
-- phase_inc_mux_sel <= '1';
|
||||
-- --phase_inc_en <= not(holdoff_r);
|
||||
-- dds_rst <= '0';
|
||||
-- if(cnt4_r < dds_sample_cnt_r1)then
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= cnt4_r +1;
|
||||
-- if(phase_inc_dwell_cnt_r < phase_inc_dwell_r)then
|
||||
-- phase_inc_dwell_cnt <= phase_inc_dwell_cnt_r +1;
|
||||
-- else
|
||||
-- phase_inc_dwell_cnt <= x"00000";
|
||||
-- phase_inc_en <= '1';
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- else
|
||||
-- if(holdoff_r = '0')then
|
||||
-- dds_ce <= '1';
|
||||
-- cnt4 <= (others => '0');
|
||||
-- state <= s3;
|
||||
-- end if;
|
||||
-- end if;
|
||||
|
||||
-- Keep DDS enabled to overcome the latency of the core (i.e. wait for our samples to pop out).
|
||||
when s3 =>
|
||||
dds_rst <= '0';
|
||||
if(cnt5_r < 9)then
|
||||
if(holdoff_r = '0')then
|
||||
dds_ce <= '1';
|
||||
cnt5 <= cnt5_r +1;
|
||||
end if;
|
||||
else
|
||||
cnt5 <= (others => '0');
|
||||
state <= s0;
|
||||
end if;
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(clk_in)
|
||||
begin
|
||||
if(rising_edge(clk_in))then
|
||||
mult_dval_r <= mult_ce_pipe_r(1);
|
||||
mult_ce_pipe_r(1 downto 0) <= mult_ce_pipe_r(0) & (dds_rdy and dds_ce);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_swap_scaled <= data_scaled when swap_r = '0' else data_scaled(15 downto 0) & data_scaled(31 downto 16);
|
||||
mult_ce <= mult_ce_pipe_r(1) or mult_ce_pipe_r(0) or (dds_rdy and dds_ce);
|
||||
|
||||
i_dds : entity work.dds_latency10
|
||||
port map(
|
||||
-- ce => dds_ce,
|
||||
-- clk => clk_in,
|
||||
-- sclr => dds_rst,
|
||||
-- pinc_in => phase_inc_r1,
|
||||
-- poff_in => phase_offset_r,
|
||||
-- rdy => dds_rdy,
|
||||
-- cosine => dds_data(15 downto 0),
|
||||
-- sine => dds_data(31 downto 16)
|
||||
aclk => clk_in,
|
||||
aclken => dds_ce,
|
||||
aresetn => rstn_r,
|
||||
s_axis_phase_tvalid => dds_ce,
|
||||
s_axis_phase_tdata => phase_inc_r1,
|
||||
m_axis_data_tvalid => dds_rdy,
|
||||
m_axis_data_tdata => dds_data
|
||||
);
|
||||
|
||||
i_mult1 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(15 downto 0),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(15 downto 0)
|
||||
);
|
||||
|
||||
i_mult2 : mult_16signed_x_16unsigned_latency3
|
||||
port map(
|
||||
clk => clk_in,
|
||||
a => dds_data(31 downto 16),
|
||||
b => scale_r,
|
||||
ce => mult_ce,
|
||||
sclr => '0',
|
||||
p => data_scaled(31 downto 16)
|
||||
);
|
||||
|
||||
end mixed;
|
||||
|
||||
@@ -0,0 +1,350 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use IEEE.std_logic_textio.all;
|
||||
|
||||
entity dds_pulse_intfc_x4 is
|
||||
port(
|
||||
s_axi_aclk_in : in std_logic;
|
||||
s_axi_aresetn_in : in std_logic;
|
||||
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
dac_holdoff_in : in std_logic;
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
scale_0_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_0_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_0_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_0_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_0_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_0_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_0_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_0_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
scale_1_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_1_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_1_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_1_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_1_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_1_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_1_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
scale_2_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_2_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_2_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_2_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_2_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_2_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_2_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_2_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
scale_3_in : in std_logic_vector(15 downto 0);
|
||||
dds_phase_inc_dwell_time_3_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_3_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_3_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_3_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_3_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_3_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_3_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
m_axis_aresetn_in : in std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
m0_axis_tready_in : in std_logic;
|
||||
|
||||
m1_axis_tdata_out : out std_logic_vector(127 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
m1_axis_tready_in : in std_logic;
|
||||
|
||||
cnt_reset_in : in std_logic;
|
||||
m0_axis_tvalid_cnt_out : out std_logic_vector(31 downto 0);
|
||||
m0_dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0);
|
||||
m1_axis_tvalid_cnt_out : out std_logic_vector(31 downto 0);
|
||||
m1_dds_pulse_data_cnt_out : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end entity dds_pulse_intfc_x4;
|
||||
|
||||
architecture imp of dds_pulse_intfc_x4 is
|
||||
|
||||
signal m0_dds_intfc_tdata_0 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_0 : std_logic;
|
||||
signal m1_dds_intfc_tdata_0 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_0 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata_1 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_1 : std_logic;
|
||||
signal m1_dds_intfc_tdata_1 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_1 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata_2 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_2 : std_logic;
|
||||
signal m1_dds_intfc_tdata_2 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_2 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata_3 : std_logic_vector(31 downto 0);
|
||||
signal m0_dds_intfc_tvalid_3 : std_logic;
|
||||
signal m1_dds_intfc_tdata_3 : std_logic_vector(31 downto 0);
|
||||
signal m1_dds_intfc_tvalid_3 : std_logic;
|
||||
|
||||
signal m0_dds_intfc_tdata : std_logic_vector(127 downto 0);
|
||||
signal m0_dds_intfc_tvalid : std_logic;
|
||||
signal m0_dds_intfc_tready : std_logic;
|
||||
signal s0_axis_tready_pipe : std_logic;
|
||||
signal m0_axis_tvalid_pipe : std_logic;
|
||||
signal m0_axis_tvalid_data_pipe_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m0_dds_intfc_tvalid_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal m1_dds_intfc_tdata : std_logic_vector(127 downto 0);
|
||||
signal m1_dds_intfc_tvalid : std_logic;
|
||||
signal m1_dds_intfc_tready : std_logic;
|
||||
signal s1_axis_tready_pipe : std_logic;
|
||||
signal m1_axis_tvalid_pipe : std_logic;
|
||||
signal m1_axis_tvalid_data_pipe_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal m1_dds_intfc_tvalid_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
m0_axis_tvalid_cnt_out <= m0_axis_tvalid_data_pipe_cnt_r;
|
||||
m0_dds_pulse_data_cnt_out <= m0_dds_intfc_tvalid_data_cnt_r;
|
||||
m1_axis_tvalid_cnt_out <= m1_axis_tvalid_data_pipe_cnt_r;
|
||||
m1_dds_pulse_data_cnt_out <= m1_dds_intfc_tvalid_data_cnt_r;
|
||||
|
||||
i_dds_pulse_wrapper_0 : entity work.dds_pulse_wrapper
|
||||
generic map (
|
||||
DDS_POSITION => 0
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_0_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_0_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_0_in,
|
||||
idle_samples_in => idle_samples_0_in,
|
||||
dds_samples_in => dds_samples_0_in,
|
||||
phase_inc_in => phase_inc_0_in,
|
||||
phase_off_in => phase_off_0_in,
|
||||
swap_sf_in => swap_sf_0_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_0,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_0,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_0,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_0,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
i_dds_pulse_wrapper_1 : entity work.dds_pulse_wrapper
|
||||
generic map (
|
||||
DDS_POSITION => 1
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_1_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_1_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_1_in,
|
||||
idle_samples_in => idle_samples_1_in,
|
||||
dds_samples_in => dds_samples_1_in,
|
||||
phase_inc_in => phase_inc_1_in,
|
||||
phase_off_in => phase_off_1_in,
|
||||
swap_sf_in => swap_sf_1_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_1,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_1,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_1,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_1,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
i_dds_pulse_wrapper_2 : entity work.dds_pulse_wrapper
|
||||
generic map (
|
||||
DDS_POSITION => 2
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_2_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_2_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_2_in,
|
||||
idle_samples_in => idle_samples_2_in,
|
||||
dds_samples_in => dds_samples_2_in,
|
||||
phase_inc_in => phase_inc_2_in,
|
||||
phase_off_in => phase_off_2_in,
|
||||
swap_sf_in => swap_sf_2_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_2,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_2,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_2,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_2,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
i_dds_pulse_wrapper_3 : entity work.dds_pulse_wrapper
|
||||
generic map (
|
||||
DDS_POSITION => 3
|
||||
)
|
||||
port map (
|
||||
s_axi_aclk_in => s_axi_aclk_in,
|
||||
s_axi_aresetn_in => s_axi_aresetn_in,
|
||||
cmd_idx_in => cmd_idx_in,
|
||||
cmd_send_in => cmd_send_in,
|
||||
|
||||
mode_in => '0',
|
||||
scale_in => scale_3_in,
|
||||
dac_holdoff_in => dac_holdoff_in,
|
||||
|
||||
reserv1_in => x"00000000",
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time_3_in,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size_3_in,
|
||||
idle_samples_in => idle_samples_3_in,
|
||||
dds_samples_in => dds_samples_3_in,
|
||||
phase_inc_in => phase_inc_3_in,
|
||||
phase_off_in => phase_off_3_in,
|
||||
swap_sf_in => swap_sf_3_in,
|
||||
|
||||
m_axis_aclk_in => m_axis_aclk_in,
|
||||
m_axis_aresetn_in => m_axis_aresetn_in,
|
||||
m0_axis_tdata_out => m0_dds_intfc_tdata_3,
|
||||
m0_axis_tvalid_out => m0_dds_intfc_tvalid_3,
|
||||
m0_axis_tready_in => m0_dds_intfc_tready,
|
||||
m1_axis_tdata_out => m1_dds_intfc_tdata_3,
|
||||
m1_axis_tvalid_out => m1_dds_intfc_tvalid_3,
|
||||
m1_axis_tready_in => m1_dds_intfc_tready
|
||||
);
|
||||
|
||||
----------------m0
|
||||
m0_dds_intfc_tdata(31 downto 0) <= m0_dds_intfc_tdata_0; -- s0
|
||||
m0_dds_intfc_tdata(63 downto 32) <= m0_dds_intfc_tdata_1; -- s1
|
||||
m0_dds_intfc_tdata(95 downto 64) <= m0_dds_intfc_tdata_2; -- s2
|
||||
m0_dds_intfc_tdata(127 downto 96) <= m0_dds_intfc_tdata_3; -- s3
|
||||
|
||||
m0_dds_intfc_tvalid <= m0_dds_intfc_tvalid_0 and m0_dds_intfc_tvalid_1 and m0_dds_intfc_tvalid_2 and m0_dds_intfc_tvalid_3;
|
||||
|
||||
m0_dds_intfc_tready <= '1' when m0_dds_intfc_tvalid = '1' and s0_axis_tready_pipe = '1' else '0';
|
||||
|
||||
i_axis_register_slice_128b_m0 : entity work.axis_register_slice_128b
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => m0_dds_intfc_tdata, -- in
|
||||
s_axis_tvalid => m0_dds_intfc_tvalid, -- in
|
||||
s_axis_tready => s0_axis_tready_pipe, -- out
|
||||
|
||||
m_axis_tdata => m0_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m0_axis_tvalid_pipe, -- out
|
||||
m_axis_tready => m0_axis_tready_in -- in
|
||||
);
|
||||
|
||||
m0_axis_tvalid_out <= m0_axis_tvalid_pipe;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m0_axis_tvalid_data_pipe_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m0_axis_tvalid_pipe = '1' and m0_axis_tready_in = '1') then
|
||||
m0_axis_tvalid_data_pipe_cnt_r <= m0_axis_tvalid_data_pipe_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m0_dds_intfc_tvalid_data_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m0_dds_intfc_tvalid = '1' and m0_dds_intfc_tready = '1') then
|
||||
m0_dds_intfc_tvalid_data_cnt_r <= m0_dds_intfc_tvalid_data_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
----------------m1
|
||||
m1_dds_intfc_tdata(31 downto 0) <= m1_dds_intfc_tdata_0;
|
||||
m1_dds_intfc_tdata(63 downto 32) <= m1_dds_intfc_tdata_1;
|
||||
m1_dds_intfc_tdata(95 downto 64) <= m1_dds_intfc_tdata_2;
|
||||
m1_dds_intfc_tdata(127 downto 96) <= m1_dds_intfc_tdata_3;
|
||||
|
||||
m1_dds_intfc_tvalid <= m1_dds_intfc_tvalid_0 and m1_dds_intfc_tvalid_1 and m1_dds_intfc_tvalid_2 and m1_dds_intfc_tvalid_3;
|
||||
|
||||
m1_dds_intfc_tready <= '1' when m1_dds_intfc_tvalid = '1' and s1_axis_tready_pipe = '1' else '0';
|
||||
|
||||
i_axis_register_slice_128b_m1 : entity work.axis_register_slice_128b
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => m1_dds_intfc_tdata, -- in
|
||||
s_axis_tvalid => m1_dds_intfc_tvalid, -- in
|
||||
s_axis_tready => s1_axis_tready_pipe, -- out
|
||||
|
||||
m_axis_tdata => m1_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m1_axis_tvalid_pipe, -- out
|
||||
m_axis_tready => m1_axis_tready_in -- in
|
||||
);
|
||||
|
||||
m1_axis_tvalid_out <= m1_axis_tvalid_pipe;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m1_axis_tvalid_data_pipe_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m1_axis_tvalid_pipe = '1' and m1_axis_tready_in = '1') then
|
||||
m1_axis_tvalid_data_pipe_cnt_r <= m1_axis_tvalid_data_pipe_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if (m_axis_aresetn_in = '0' or cnt_reset_in = '1') then
|
||||
m1_dds_intfc_tvalid_data_cnt_r <= (others => '0');
|
||||
else
|
||||
if (m1_dds_intfc_tvalid = '1' and m1_dds_intfc_tready = '1') then
|
||||
m1_dds_intfc_tvalid_data_cnt_r <= m1_dds_intfc_tvalid_data_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
@@ -0,0 +1,300 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use std.textio.all;
|
||||
use IEEE.std_logic_textio.all;
|
||||
|
||||
entity dds_pulse_wrapper is
|
||||
generic (
|
||||
DDS_POSITION : integer := 8
|
||||
);
|
||||
port(
|
||||
s_axi_aclk_in : in std_logic;
|
||||
s_axi_aresetn_in : in std_logic;
|
||||
cmd_idx_in : in std_logic_vector( 2 downto 0);
|
||||
cmd_send_in : in std_logic;
|
||||
|
||||
mode_in : in std_logic;
|
||||
scale_in : in std_logic_vector(15 downto 0);
|
||||
dac_holdoff_in : in std_logic;
|
||||
|
||||
reserv1_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_dwell_time_in : in std_logic_vector(31 downto 0);
|
||||
dds_phase_inc_step_size_in : in std_logic_vector(31 downto 0);
|
||||
idle_samples_in : in std_logic_vector(31 downto 0);
|
||||
dds_samples_in : in std_logic_vector(31 downto 0);
|
||||
phase_inc_in : in std_logic_vector(31 downto 0);
|
||||
phase_off_in : in std_logic_vector(31 downto 0);
|
||||
swap_sf_in : in std_logic_vector(31 downto 0);
|
||||
|
||||
m_axis_aclk_in : in std_logic;
|
||||
m_axis_aresetn_in : in std_logic;
|
||||
m0_axis_tdata_out : out std_logic_vector(31 downto 0);
|
||||
m0_axis_tvalid_out : out std_logic;
|
||||
m0_axis_tready_in : in std_logic;
|
||||
m1_axis_tdata_out : out std_logic_vector(31 downto 0);
|
||||
m1_axis_tvalid_out : out std_logic;
|
||||
m1_axis_tready_in : in std_logic
|
||||
);
|
||||
end entity dds_pulse_wrapper;
|
||||
|
||||
architecture imp of dds_pulse_wrapper is
|
||||
|
||||
attribute keep : string;
|
||||
|
||||
constant ok_clk_in_period : time := 10 ns;
|
||||
|
||||
signal reset_n : std_logic;
|
||||
signal s_axi_areset : std_logic;
|
||||
signal m_axi_areset : std_logic;
|
||||
|
||||
signal s_axis_tready_0 : std_logic;
|
||||
signal s_axis_tready_1 : std_logic;
|
||||
|
||||
signal cmd_idx : std_logic_vector( 2 downto 0);
|
||||
signal cmd_send : std_logic;
|
||||
|
||||
signal mode : std_logic;
|
||||
signal scale : std_logic_vector(15 downto 0);
|
||||
signal dac_holdoff : std_logic;
|
||||
|
||||
|
||||
signal reserv1 : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_dwell_time : std_logic_vector(31 downto 0);
|
||||
signal dds_phase_inc_step_size : std_logic_vector(31 downto 0);
|
||||
signal idle_samples : std_logic_vector(31 downto 0);
|
||||
signal dds_samples : std_logic_vector(31 downto 0);
|
||||
signal phase_inc : std_logic_vector(31 downto 0);
|
||||
signal phase_off : std_logic_vector(31 downto 0);
|
||||
signal swap_sf : std_logic_vector(31 downto 0);
|
||||
|
||||
signal dds_pulse_dval : std_logic;
|
||||
signal dds_pulse_data : std_logic_vector(31 downto 0);
|
||||
signal pulse_i : std_logic_vector(15 downto 0);
|
||||
signal pulse_q : std_logic_vector(15 downto 0);
|
||||
|
||||
signal pipe_in_ch1_fifo_rden : std_logic;
|
||||
signal pipe_in_ch1_fifo_rd_data : std_logic_vector(31 downto 0);
|
||||
signal pipe_in_ch1_fifo_rd_dval : std_logic;
|
||||
signal pipe_in_ch1_fifo_empty : std_logic;
|
||||
signal pipe_in_ch2_fifo_rden : std_logic;
|
||||
|
||||
signal cmd_send_r : std_logic := '0';
|
||||
signal cmd_send_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal pipe_in_ch1_fifo_rden_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal dds_pulse_data_overflow_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
signal tick_1ms : std_logic;
|
||||
|
||||
signal s_axi_aclk_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0');
|
||||
signal s_axi_aclk_freq_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal s_axi_aclk_cnt_r : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
s_axi_areset <= not s_axi_aresetn_in; -- synchronous with s_axi_aclk_in
|
||||
m_axi_areset <= not m_axis_aresetn_in; -- synchronous with m_axis_aclk_in
|
||||
|
||||
-- i_vio_0 : entity work.vio_0
|
||||
-- port map (
|
||||
-- clk => s_axi_aclk_in,
|
||||
-- probe_in0 => cmd_send_cnt_r, -- 32
|
||||
-- probe_in1 => pipe_in_ch1_fifo_rden_cnt_r, -- 32
|
||||
-- probe_in2 => dds_pulse_data_cnt_r, -- 32
|
||||
-- probe_in3 => s_axi_aclk_freq_r, -- 32
|
||||
-- probe_in4 => s_axi_aclk_cnt_r, -- 32
|
||||
-- probe_in5 => dds_pulse_data_overflow_cnt_r, -- 32
|
||||
-- probe_in6 => m_axis_tvalid_cnt_r, -- 32
|
||||
|
||||
-- );
|
||||
|
||||
mode <= mode_in;
|
||||
scale <= scale_in;
|
||||
dac_holdoff <= dac_holdoff_in;
|
||||
cmd_idx <= cmd_idx_in;
|
||||
cmd_send <= cmd_send_in;
|
||||
|
||||
reserv1 <= reserv1_in;
|
||||
dds_phase_inc_dwell_time <= dds_phase_inc_dwell_time_in;
|
||||
dds_phase_inc_step_size <= dds_phase_inc_step_size_in;
|
||||
idle_samples <= idle_samples_in;
|
||||
dds_samples <= dds_samples_in;
|
||||
phase_inc <= phase_inc_in;
|
||||
phase_off <= phase_off_in;
|
||||
swap_sf <= swap_sf_in;
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
if (s_axi_aresetn_in = '0') then
|
||||
cmd_send_cnt_r <= (others => '0');
|
||||
cmd_send_r <= '0';
|
||||
else
|
||||
cmd_send_r <= cmd_send;
|
||||
if (cmd_send = '1' and cmd_send_r = '0') then
|
||||
cmd_send_cnt_r <= cmd_send_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_dds_cmd_gen : entity work.dds_cmd_gen
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
cmd_idx_in => cmd_idx,
|
||||
cmd_send_in => cmd_send,
|
||||
|
||||
reserv1_in => reserv1,
|
||||
dds_phase_inc_dwell_time_in => dds_phase_inc_dwell_time,
|
||||
dds_phase_inc_step_size_in => dds_phase_inc_step_size,
|
||||
idle_samples_in => idle_samples,
|
||||
dds_samples_in => dds_samples,
|
||||
phase_inc_in => phase_inc,
|
||||
phase_off_in => phase_off,
|
||||
swap_sf_in => swap_sf,
|
||||
|
||||
fifo_rd_clk_in => m_axis_aclk_in,
|
||||
fifo_rd_data_out => pipe_in_ch1_fifo_rd_data,
|
||||
fifo_rd_dval_out => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo_rd_rd_en_in => pipe_in_ch1_fifo_rden,
|
||||
fifo_rd_empty_out => pipe_in_ch1_fifo_empty,
|
||||
|
||||
rst_in => m_axi_areset
|
||||
);
|
||||
|
||||
-- i_ila_4 : entity work.ila_4
|
||||
-- port map (
|
||||
-- clk => m_axis_aclk_in,
|
||||
-- probe0 => pipe_in_ch1_fifo_rd_data, --32
|
||||
-- probe1(0) => pipe_in_ch1_fifo_rd_dval, --1
|
||||
-- probe2(0) => pipe_in_ch1_fifo_rden, --1
|
||||
-- probe3(0) => pipe_in_ch1_fifo_empty --1
|
||||
-- );
|
||||
|
||||
i_dds_pulse_2x_top : entity work.dds_pulse_2x_top
|
||||
generic map (
|
||||
DDS_POSITION => DDS_POSITION
|
||||
)
|
||||
port map(
|
||||
clk_in => m_axis_aclk_in,
|
||||
rst_in => m_axi_areset,
|
||||
mode_in => mode, -- 0=single, 1=dual
|
||||
scale_in => scale,
|
||||
fifo1_data_in => pipe_in_ch1_fifo_rd_data,
|
||||
fifo1_dval_in => pipe_in_ch1_fifo_rd_dval,
|
||||
fifo1_empty_in => pipe_in_ch1_fifo_empty,
|
||||
fifo1_rden_out => pipe_in_ch1_fifo_rden,
|
||||
fifo2_data_in => x"00000000",--pipe_in_ch2_fifo_rd_data,
|
||||
fifo2_dval_in => '0',--pipe_in_ch2_fifo_rd_dval,
|
||||
fifo2_empty_in => '1',--pipe_in_ch2_fifo_empty,
|
||||
fifo2_rden_out => pipe_in_ch2_fifo_rden,
|
||||
holdoff_in => dac_holdoff,
|
||||
overflow_out => open,
|
||||
underflow_out => open,
|
||||
i_max_abs_out => open,
|
||||
q_max_abs_out => open,
|
||||
data_out => dds_pulse_data,
|
||||
dval_out => dds_pulse_dval
|
||||
);
|
||||
|
||||
-- pulse_i <= dds_pulse_data(15 downto 0);
|
||||
-- pulse_q <= dds_pulse_data(31 downto 16);
|
||||
|
||||
|
||||
-- process(s_axi_aclk_in)
|
||||
-- variable LineOut : line;
|
||||
-- begin
|
||||
-- if (rising_edge(s_axi_aclk_in)) then
|
||||
-- if (dds_pulse_dval = '1') then
|
||||
-- hwrite(LineOut, dds_pulse_data);
|
||||
-- writeline(DataFile, LineOut);
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end process;
|
||||
|
||||
process(m_axis_aclk_in)
|
||||
begin
|
||||
if (rising_edge(m_axis_aclk_in)) then
|
||||
if(m_axis_aresetn_in = '0') then
|
||||
dds_pulse_data_cnt_r <= (others => '0');
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= (others => '0');
|
||||
dds_pulse_data_overflow_cnt_r <= (others => '0');
|
||||
else
|
||||
if (dds_pulse_dval = '1' and s_axis_tready_0 = '1') then
|
||||
dds_pulse_data_cnt_r <= dds_pulse_data_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (dds_pulse_dval = '1' and s_axis_tready_0 = '0') then
|
||||
dds_pulse_data_overflow_cnt_r <= dds_pulse_data_overflow_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
if (pipe_in_ch1_fifo_rden = '1') then
|
||||
pipe_in_ch1_fifo_rden_cnt_r <= pipe_in_ch1_fifo_rden_cnt_r + 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
i_axis_register_slice_32_0 : entity work.axis_register_slice_32
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => dds_pulse_data, -- in
|
||||
s_axis_tvalid => dds_pulse_dval, -- in
|
||||
s_axis_tready => s_axis_tready_0, -- out
|
||||
|
||||
m_axis_tdata => m0_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m0_axis_tvalid_out, -- out
|
||||
m_axis_tready => m0_axis_tready_in -- in
|
||||
);
|
||||
|
||||
i_axis_register_slice_32_1 : entity work.axis_register_slice_32
|
||||
port map (
|
||||
aclk => m_axis_aclk_in, -- in
|
||||
aresetn => m_axis_aresetn_in, -- in
|
||||
s_axis_tdata => dds_pulse_data, -- in
|
||||
s_axis_tvalid => dds_pulse_dval, -- in
|
||||
s_axis_tready => s_axis_tready_1, -- out
|
||||
|
||||
m_axis_tdata => m1_axis_tdata_out, -- out
|
||||
m_axis_tvalid => m1_axis_tvalid_out, -- out
|
||||
m_axis_tready => m1_axis_tready_in -- in
|
||||
);
|
||||
|
||||
|
||||
i_tick_gen : entity work.tick_gen
|
||||
generic map (
|
||||
CLOCK_SPEED_MHZ => 100
|
||||
)
|
||||
port map (
|
||||
clk_in => s_axi_aclk_in,
|
||||
|
||||
tick_1us_out => open,
|
||||
tick_1ms_out => tick_1ms,
|
||||
tick_500ms_out => open,
|
||||
tick_750ms_out => open,
|
||||
tick_1s_out => open,
|
||||
|
||||
prog_us_tick_rate_in => x"00000000",
|
||||
prog_us_tick_out => open,
|
||||
|
||||
reset_in => s_axi_areset
|
||||
);
|
||||
|
||||
process(s_axi_aclk_in)
|
||||
begin
|
||||
if (rising_edge(s_axi_aclk_in)) then
|
||||
s_axi_aclk_tick_1ms_r <= s_axi_aclk_tick_1ms_r(1 to 2) & tick_1ms;
|
||||
if (s_axi_aclk_tick_1ms_r(0 to 1) = "01") then
|
||||
s_axi_aclk_freq_r <= s_axi_aclk_cnt_r;
|
||||
s_axi_aclk_cnt_r <= (others => '0');
|
||||
else
|
||||
s_axi_aclk_cnt_r <= s_axi_aclk_cnt_r + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture imp;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+168
@@ -0,0 +1,168 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "mult_16signed_x_16unsigned_latency3",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "19",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "mult_16signed_x_16unsigned_latency3", "resolve_type": "user", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Parallel_Multiplier", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAType": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PortBType": [ { "value": "Unsigned", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortBWidth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
|
||||
"Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Custom_Output_Width": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OutputWidthHigh": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OutputWidthLow": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PipeStages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ClockEnable": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SyncClear": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_HIGH": [ { "value": "30", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_LOW": [ { "value": "15", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynquplus" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xczu19eg" } ],
|
||||
"PACKAGE": [ { "value": "ffvc1760" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "I" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "19" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/mult_16signed_x_16unsigned_latency3" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"A": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"CE": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"SCLR": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"P": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "SCLR" } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CE": [ { "physical_name": "CE" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+467
@@ -0,0 +1,467 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "sfifo_32b_1024_pf992_latency1",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../../../temp/aa/dds_pulse_intfc_v1_0_project/dds_pulse_intfc_v1_0_project.gen/sources_1/ip/sfifo_32b_1024_pf992_latency1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "sfifo_32b_1024_pf992_latency1", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"Full_Threshold_Assert_Value": [ { "value": "992", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "991", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
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|
||||
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|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
}
|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user