diff --git a/source/system_raw_eth_top.v b/source/system_raw_eth_top.v
index 8c3eabf..0294f19 100644
--- a/source/system_raw_eth_top.v
+++ b/source/system_raw_eth_top.v
@@ -36,7 +36,7 @@
 `timescale 1ns/100ps
 
 module system_raw_eth_top  #(
-  parameter FPGA_REVISION_DATE = 32'h06272026, 
+  parameter FPGA_REVISION_DATE = 32'h07072026, 
   parameter MINOR_REV = 8'h01,  
   parameter TX_JESD_L = 8,
   parameter TX_NUM_LINKS = 1,
@@ -488,7 +488,31 @@ module system_raw_eth_top  #(
   wire            chan1_m0_dds_pulse_tready_128b;
   
   wire            dac_holdoff_ext;
-  
+    
+  wire  [127:0]   chan0_m1_dds_pulse_tdata_128b;
+  wire            chan0_m1_dds_pulse_tvalid_128b;
+  wire            chan0_m1_dds_pulse_tready_128b;
+    
+  wire  [127:0]   chan1_m1_dds_pulse_tdata_128b;
+  wire            chan1_m1_dds_pulse_tvalid_128b;
+  wire            chan1_m1_dds_pulse_tready_128b;
+
+  wire  [511:0]   chan0_dds_pulse_tdata_512b;
+  wire            chan0_dds_pulse_tvalid_512b;
+  wire            chan0_dds_pulse_tready_512b; 
+
+  wire  [511:0]   chan1_dds_pulse_tdata_512b;
+  wire            chan1_dds_pulse_tvalid_512b;
+  wire            chan1_dds_pulse_tready_512b; 
+
+  wire  [511:0]   chan0_dds_pulse_fifo_tdata_512b;
+  wire            chan0_dds_pulse_fifo_tvalid_512b;
+  wire            chan0_dds_pulse_fifo_tready_512b;
+
+  wire  [511:0]   chan1_dds_pulse_fifo_tdata_512b;
+  wire            chan1_dds_pulse_fifo_tvalid_512b;
+  wire            chan1_dds_pulse_fifo_tready_512b;
+
 ////////////////////////////////////////////////////////////////
 
   // instantiations