----------------------------------------------------------------------------------
-- Company:     Erisys
-- Engineer:    Jason M Blevins
-- 
-- Create Date: 07/02/2023 02:07:25 PM
-- Design Name: 
-- Module Name: dig_iq_x2 - structural
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library xpm;
use xpm.vcomponents.all;
library UNISIM;
use UNISIM.VComponents.all;

entity dig_iq_x2 is
  port (
    clk_125_resetn_in               : in  std_logic;
    clk_125_in                      : in  std_logic;

    aclk_in                         : in std_logic;
    aresetn_in                      : in std_logic;
    cmd_strb_in                     : in  std_logic;
    cmd_addr_in                     : in  std_logic_vector(11 downto 0);
    cmd_write_in                    : in  std_logic;
    cmd_sel_in                      : in  std_logic_vector(2 downto 0);
    cmd_wdata_in                    : in  std_logic_vector(31 downto 0);
    cmd_ready_out                   : out std_logic;
    cmd_rdata_out                   : out std_logic_vector(31 downto 0);
    dig_iq_interface_reset_in       : in  std_logic_vector(1 downto 0);
    --dig_iq_resetn                 : in  std_logic_vector(1 downto 0);
    --dig_iq_rx_enable              : in  std_logic_vector(1 downto 0);
    --
    dig_iq_interface_ready_out      : out std_logic_vector(1 downto 0); --async
    --dig_iq_cc_overflow            : out std_logic_vector(1 downto 0); --async
    --dig_iq_tx_overflow            : out std_logic_vector(PORT_CNT-1 downto 0);
    rx_data_ready_in                : in  std_logic_vector(1 downto 0);

    axis_0_aclk_out                 : out std_logic;
    axis_0_aresetn_out              : out std_logic;
    m0_axis_tdata_out               : out std_logic_vector(239 downto 0);
    m0_axis_tvalid_out              : out std_logic;
    s0_axis_tdata_in                : in  std_logic_vector(239 downto 0);
    s0_axis_tvalid_in               : in  std_logic;
    s0_axis_tready_out              : out std_logic;

    axis_1_aclk_out                 : out std_logic;
    axis_1_aresetn_out              : out std_logic;
    m1_axis_tdata_out               : out std_logic_vector(239 downto 0);
    m1_axis_tvalid_out              : out std_logic;
    s1_axis_tdata_in                : in  std_logic_vector(239 downto 0);
    s1_axis_tvalid_in               : in  std_logic;
    s1_axis_tready_out              : out std_logic; 

    tx_data_channel_reset_in        : in std_logic;
    tx_data_clear_in                : in std_logic;

    qsfp0_ref_clk_n_in              : in  std_logic;
    qsfp0_ref_clk_p_in              : in  std_logic;
    qsfp0_rx_rxn_in                 : in  std_logic_vector(3 downto 0);
    qsfp0_rx_rxp_in                 : in  std_logic_vector(3 downto 0);
    qsfp0_tx_txn_out                : out std_logic_vector(3 downto 0);
    qsfp0_tx_txp_out                : out std_logic_vector(3 downto 0);

    qsfp1_ref_clk_n_in              : in std_logic;
    qsfp1_ref_clk_p_in              : in std_logic;
    qsfp1_rx_rxn_in                 : in  std_logic_vector(3 downto 0);
    qsfp1_rx_rxp_in                 : in  std_logic_vector(3 downto 0);
    qsfp1_tx_txn_out                : out std_logic_vector(3 downto 0);
    qsfp1_tx_txp_out                : out std_logic_vector(3 downto 0)
    );
end dig_iq_x2;

architecture structural of dig_iq_x2 is

  component DIG_IQ_HS_CUSTOM1X is
    port( 
      INIT_CLK              : in  std_logic                       := '0';
      INTERFACE_RESET       : in  std_logic                       := '1';
      IntL                  : in  std_logic                       := '1';
      MGTREFCLK_N           : in  std_logic                       := '1';
      MGTREFCLK_P           : in  std_logic                       := '0';
      ModPrsL               : in  std_logic                       := '1';
      PADDR                 : in  std_logic_vector (11 downto 0)  := (others => '0');
      PCLK                  : in  std_logic                       := '0';
      PENABLE               : in  std_logic                       := '0';
      PRESETn               : in  std_logic                       := '0';
      PSEL                  : in  std_logic                       := '0';
      PWDATA                : in  std_logic_vector (31 downto 0)  := (others => '0');
      PWRITE                : in  std_logic                       := '0';
      RXN                   : in  std_logic_vector (3 downto 0)   := (others => '1');
      RXP                   : in  std_logic_vector (3 downto 0)   := (others => '0');
      RX_DATA_READY         : in  std_logic                       := '1';
      SCL_I                 : in  std_logic                       := '0';
      SDA_I                 : in  std_logic                       := '0';
      TX_DATA_CLEAR         : in  std_logic                       := '0';
      TX_DATA_DAT           : in  std_logic_vector (239 downto 0) := (others => '0');
      TX_DATA_EN            : in  std_logic                       := '0';
      TX_DATA_CHANNEL_RESET : in  std_logic                       := '0';
      RX_DATA_CHANNEL_RESET : out std_logic;
      DATA_CLK              : out std_logic ;
      INTERFACE_READY       : out std_logic ;
      ModselL               : out std_logic ;
      PRDATA                : out std_logic_vector (31 downto 0);
      PREADY                : out std_logic ;
      RX_DATA_DAT           : out std_logic_vector (239 downto 0);
      RX_DATA_EN            : out std_logic ;
      SCL_O                 : out std_logic ;
      SCL_OE                : out std_logic ;
      SDA_O                 : out std_logic ;
      SDA_OE                : out std_logic ;
      TXN                   : out std_logic_vector (3 downto 0);
      TXP                   : out std_logic_vector (3 downto 0);
      TX_DATA_READY         : out std_logic 
      );
  end component DIG_IQ_HS_CUSTOM1X;

  component dig_iq_p_intfc is
    generic(
      SAME_CLKS           : natural range 0 to 1 := 0
      );
    port (
      reg_clk             : in std_logic;
      reg_resetn          : in std_logic;
      --
      strb_in             : in  std_logic;
      addr_in             : in  std_logic_vector(11 downto 0);
      write_in            : in  std_logic;
      sel_in              : in  std_logic_vector(2 downto 0);
      wdata_in            : in  std_logic_vector(31 downto 0);
      ready_out           : out std_logic;
      rdata_out           : out std_logic_vector(31 downto 0);    
      ----------------------------------------------------------   
      clk_125             : in std_logic;
      clk_125_resetn      : in std_logic;
      --
      p_addr              : out std_logic_vector(11 downto 0);
      p_write             : out std_logic;
      p_wdata             : out std_logic_vector(31 downto 0);
      p_enable            : out std_logic_vector(7 downto 0);
      p_ready             : in  std_logic_vector(7 downto 0);    
      p_rdata_0           : in  std_logic_vector(31 downto 0);    
      p_rdata_1           : in  std_logic_vector(31 downto 0);
      p_rdata_2           : in  std_logic_vector(31 downto 0);
      p_rdata_3           : in  std_logic_vector(31 downto 0);
      p_rdata_4           : in  std_logic_vector(31 downto 0);
      p_rdata_5           : in  std_logic_vector(31 downto 0);
      p_rdata_6           : in  std_logic_vector(31 downto 0);
      p_rdata_7           : in  std_logic_vector(31 downto 0)
      );
  end component dig_iq_p_intfc;
  
  component axis_clock_converter_0
    port (
      s_axis_aresetn  : in std_logic;
      m_axis_aresetn  : in std_logic;
      s_axis_aclk     : in std_logic;
      s_axis_tvalid   : in std_logic;
      s_axis_tready   : out std_logic;
      s_axis_tdata    : in std_logic_vector(239 downto 0);
      m_axis_aclk     : in std_logic;
      m_axis_tvalid   : out std_logic;
      m_axis_tready   : in std_logic;
      m_axis_tdata    : out std_logic_vector(239 downto 0)
      );
  end component;
  
  component axis_data_fifo_0
    port (
      s_axis_aresetn  : in std_logic;
      s_axis_aclk     : in std_logic;
      s_axis_tvalid   : in std_logic;
      s_axis_tready   : out std_logic;
      s_axis_tdata    : in std_logic_vector(239 downto 0);
      m_axis_aclk     : in std_logic;
      m_axis_tvalid   : out std_logic;
      m_axis_tready   : in std_logic;
      m_axis_tdata    : out std_logic_vector(239 downto 0)
      );
  end component; 
  
  signal  p_addr                      : std_logic_vector(11 downto 0);
  signal  p_write                     : std_logic;
  signal  p_wdata                     : std_logic_vector(31 downto 0);       
  signal  p_enable                    : std_logic_vector(7 downto 0);    
  signal  p_ready                     : std_logic_vector(7 downto 0);
  
  type SLV_32_ARRAY is array (integer range 0 to 1) of std_logic_vector(31 downto 0);
  signal  p_rdata                     : SLV_32_ARRAY;

  type SLV_4_ARRAY is array (integer range 0 to 1) of std_logic_vector(3 downto 0);
  signal  qsfp_rx_rxn                 : SLV_4_ARRAY;
  signal  qsfp_rx_rxp                 : SLV_4_ARRAY;
  signal  qsfp_tx_txn                 : SLV_4_ARRAY;
  signal  qsfp_tx_txp                 : SLV_4_ARRAY;  

  type SLV_240_ARRAY is array (integer range 0 to 1) of std_logic_vector(239 downto 0);
  --signal  tx_data_r                   : SLV_240_ARRAY; 
  --signal  rx_data_r                   : SLV_240_ARRAY;
  signal  rx_data                     : SLV_240_ARRAY;
  signal  s_axis_tdata                : SLV_240_ARRAY;
  --signal  m_axis_tdata_int            : SLV_240_ARRAY;
  --signal  tx_fifo_m_tdata             : SLV_240_ARRAY;
  
  signal  clk                         : std_logic_vector(1 downto 0);
  --signal  resetn                      : std_logic_vector(1 downto 0);
  --signal  rx_enable                   : std_logic_vector(1 downto 0);
  signal  interface_reset             : std_logic_vector(1 downto 0);
  signal  qsfp_ref_clk_n              : std_logic_vector(1 downto 0);
  signal  qsfp_ref_clk_p              : std_logic_vector(1 downto 0);
  --signal  tx_data_en_r                : std_logic_vector(1 downto 0)  := (others => '0');
  signal  rx_data_en                  : std_logic_vector(1 downto 0);
  --signal  rx_data_en_r                : std_logic_vector(1 downto 0)  := (others => '0');
  signal  tx_data_ready               : std_logic_vector(1 downto 0);
  signal  s_axis_tvalid               : std_logic_vector(1 downto 0);
  --signal  rx_data_en_int              : std_logic_vector(1 downto 0);
  --signal  tx_data_en_int              : std_logic_vector(1 downto 0); 
  --signal  m_axis_tvalid_int           : std_logic_vector(1 downto 0);        
  --signal cc_overflow_tready           : std_logic_vector(1 downto 0);
  --signal cc_overflow_int              : std_logic_vector(1 downto 0);
  --signal cc_overflow_r                : std_logic_vector(PORT_CNT-1 downto 0);
  --signal  tx_fifo_m_tvalid            : std_logic_vector(1 downto 0); 
  --signal  s_axis_tready_int           : std_logic_vector(1 downto 0);
  --signal  tx_fifo_overflow_int        : std_logic_vector(PORT_CNT-1 downto 0);

  signal dig_iq_interface_ready           : std_logic_vector(1 downto 0);  
  signal axis_0_aresetn_r                 : std_logic_vector(0 to 31) := (others => '0');
  signal axis_1_aresetn_r                 : std_logic_vector(0 to 31) := (others => '0');

  type array_32b_type                   is array (0 to 1) of std_logic_vector(0 to 31);
  signal tx_data_channel_reset_r            : array_32b_type := (others => (others => '0'));
  signal tx_data_clear_r                    : std_logic_vector(1 downto 0) := (others => '0');
  
begin
      
  p_ready(7 downto 2) <= (others => '1');
      
  i_dig_iq_p_intfc : dig_iq_p_intfc
    generic map(
      SAME_CLKS          =>  1
      )
    port map(
      reg_clk             =>  clk_125_in,
      reg_resetn          =>  clk_125_resetn_in,
      --
      strb_in             =>  cmd_strb_in, 
      addr_in             =>  cmd_addr_in, 
      write_in            =>  cmd_write_in,
      sel_in              =>  cmd_sel_in,  
      wdata_in            =>  cmd_wdata_in,
      ready_out           =>  cmd_ready_out,
      rdata_out           =>  cmd_rdata_out,
      -- 
      clk_125             =>  clk_125_in,
      clk_125_resetn      =>  clk_125_resetn_in,
      --
      p_addr              =>  p_addr, 
      p_write             =>  p_write,
      p_wdata             =>  p_wdata,
      p_enable            =>  p_enable,
      p_ready             =>  p_ready,
      p_rdata_0           =>  p_rdata(0),
      p_rdata_1           =>  p_rdata(1),
      p_rdata_2           =>  (others => '0'),
      p_rdata_3           =>  (others => '0'),
      p_rdata_4           =>  (others => '0'),
      p_rdata_5           =>  (others => '0'),
      p_rdata_6           =>  (others => '0'),
      p_rdata_7           =>  (others => '0')
      );
      
  i_cdc_0 : xpm_cdc_array_single
  generic map (
    DEST_SYNC_FF => 2,    -- DECIMAL; range: 2-10
    INIT_SYNC_FF => 0,    -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
    SIM_ASSERT_CHK => 0,  -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
    SRC_INPUT_REG => 0,   -- DECIMAL; 0=do not register input, 1=register input
    WIDTH => 2            -- DECIMAL; range: 1-1024 
    )
  port map (
    dest_out  => interface_reset, 
    dest_clk  => clk_125_in, 
    src_clk   => '0',   
    src_in    => dig_iq_interface_reset_in     
    );
    
  -----------------------------------------------------------

  dig_iq_interface_ready_out    <= dig_iq_interface_ready;
  
  axis_0_aclk_out               <= clk(0);
  axis_0_aresetn_out            <= axis_0_aresetn_r(0);
  s_axis_tdata(0)               <= s0_axis_tdata_in;
  s_axis_tvalid(0)              <= s0_axis_tvalid_in;
  s0_axis_tready_out            <= tx_data_ready(0);--s_axis_tready_int(0);
  m0_axis_tdata_out             <= rx_data(0);--m_axis_tdata_int(0);
  m0_axis_tvalid_out            <= rx_data_en(0);--m_axis_tvalid_int(0);

  axis_1_aclk_out               <= clk(1);
  axis_1_aresetn_out            <= axis_1_aresetn_r(0);
  s_axis_tdata(1)               <= s1_axis_tdata_in;
  s_axis_tvalid(1)              <= s1_axis_tvalid_in;
  s1_axis_tready_out            <= tx_data_ready(1);--s_axis_tready_int(1);  
  m1_axis_tdata_out             <= rx_data(1);--m_axis_tdata_int(1); 
  m1_axis_tvalid_out            <= rx_data_en(1);--m_axis_tvalid_int(1);

  qsfp_ref_clk_n(0)             <= qsfp0_ref_clk_n_in;
  qsfp_ref_clk_n(1)             <= qsfp1_ref_clk_n_in;

  qsfp_ref_clk_p(0)             <= qsfp0_ref_clk_p_in;
  qsfp_ref_clk_p(1)             <= qsfp1_ref_clk_p_in;

  qsfp_rx_rxn(0)                <= qsfp0_rx_rxn_in;
  qsfp_rx_rxn(1)                <= qsfp1_rx_rxn_in;

  qsfp_rx_rxp(0)                <= qsfp0_rx_rxp_in;
  qsfp_rx_rxp(1)                <= qsfp1_rx_rxp_in;

  qsfp0_tx_txn_out              <= qsfp_tx_txn(0);
  qsfp1_tx_txn_out              <= qsfp_tx_txn(1);

  qsfp0_tx_txp_out              <= qsfp_tx_txp(0);
  qsfp1_tx_txp_out              <= qsfp_tx_txp(1);


  process(clk(0))
  begin
    if (rising_edge(clk(0))) then
      if (dig_iq_interface_ready(0) = '1') then
        axis_0_aresetn_r      <= axis_0_aresetn_r(1 to 31) & '1';
      else
        axis_0_aresetn_r      <= (others => '0');
      end if;
    end if;
  end process;
  
  process(clk(1))
  begin
    if (rising_edge(clk(1))) then
      if (dig_iq_interface_ready(1) = '1') then
        axis_1_aresetn_r      <= axis_1_aresetn_r(1 to 31) & '1';
      else
        axis_1_aresetn_r      <= (others => '0');
      end if;
    end if;
  end process;

    
  -----------------------------------------------------------
  
  GEN_0:
  for i in 0 to 1 generate
    begin
    
    
      -- i_cdc_resetn : xpm_cdc_single
      -- generic map (
        -- DEST_SYNC_FF    => 2, 
        -- INIT_SYNC_FF    => 0, 
        -- SIM_ASSERT_CHK  => 0, 
        -- SRC_INPUT_REG   => 0  
      -- )
      -- port map (
        -- dest_out  => resetn(i), 
        -- dest_clk  => clk(i), 
        -- src_clk   => '0',   
        -- src_in    => dig_iq_resetn(i)    
        -- );
      
      -- i_cdc_rx_enable : xpm_cdc_single
      -- generic map (
        -- DEST_SYNC_FF    => 2, 
        -- INIT_SYNC_FF    => 0, 
        -- SIM_ASSERT_CHK  => 0, 
        -- SRC_INPUT_REG   => 0  
      -- )
      -- port map (
        -- dest_out  => rx_enable(i), 
        -- dest_clk  => clk(i), 
        -- src_clk   => '0',   
        -- src_in    => dig_iq_rx_enable(i)    
        -- );
        
        
  process(clk(i))
  begin
    if (rising_edge(clk(i))) then
        tx_data_clear_r(i)  <= tx_data_clear_in;
        tx_data_channel_reset_r(i) <= tx_data_channel_reset_r(i)(1 to 31) & '0';
        
        if (tx_data_channel_reset_in = '1') then
            tx_data_channel_reset_r(i)  <= (others => '1');
        end if;
    end if;
  end process;   
        
        
        
      i_dig_iq : DIG_IQ_HS_CUSTOM1X
        port map( 
          INIT_CLK              =>  clk_125_in,
          INTERFACE_RESET       =>  interface_reset(i),
          IntL                  =>  '1',
          MGTREFCLK_N           =>  qsfp_ref_clk_n(i),
          MGTREFCLK_P           =>  qsfp_ref_clk_p(i),
          ModPrsL               =>  '0',
          PADDR                 =>  p_addr,
          PCLK                  =>  clk_125_in,
          PENABLE               =>  p_enable(i),
          PRESETn               =>  clk_125_resetn_in,
          PSEL                  =>  '1',
          PWDATA                =>  p_wdata,
          PWRITE                =>  p_write,
          RXN                   =>  qsfp_rx_rxn(i),
          RXP                   =>  qsfp_rx_rxp(i),
          RX_DATA_READY         =>  rx_data_ready_in(i),
          SCL_I                 =>  '0',
          SDA_I                 =>  '0',
          TX_DATA_CHANNEL_RESET =>  tx_data_channel_reset_r(i)(0),
          TX_DATA_CLEAR         =>  tx_data_clear_r(i),
          TX_DATA_DAT           =>  s_axis_tdata(i),--tx_data_r(i),
          TX_DATA_EN            =>  s_axis_tvalid(i),--tx_data_en_r(i),
          DATA_CLK              =>  clk(i),
          INTERFACE_READY       =>  dig_iq_interface_ready(i),
          ModselL               =>  open,
          PRDATA                =>  p_rdata(i),
          PREADY                =>  p_ready(i),
          RX_DATA_CHANNEL_RESET =>  open,
          RX_DATA_DAT           =>  rx_data(i),
          RX_DATA_EN            =>  rx_data_en(i),
          SCL_O                 =>  open,
          SCL_OE                =>  open,
          SDA_O                 =>  open,
          SDA_OE                =>  open,
          TXN                   =>  qsfp_tx_txn(i),
          TXP                   =>  qsfp_tx_txp(i),
          TX_DATA_READY         =>  tx_data_ready(i)
          );
    
      -- GEN_1:
      -- for j in 0 to 239 generate
        -- begin  
        
          -- i_FD_rx_data : FD --FDRE
          -- generic map (
            -- INIT => '0'          -- Initial value of register, '0', '1'
            -- )
          -- port map (
            -- Q   => rx_data_r(i)(j),   -- 1-bit output: Data
            -- C   => clk(i),            -- 1-bit input: Clock
            -- --CE  => '1',             -- 1-bit input: Clock enable
            -- D   => rx_data(i)(j)      -- 1-bit input: Data
            -- --R   => '0'              -- 1-bit input: Synchronous reset
            -- );    
        -- end generate;
        
      -- rx_data_en_int(i)  <=  rx_data_en(i) and rx_enable(i);
        
      -- i_FD_rx_data_en : FD --FDRE
      -- generic map (
        -- INIT => '0'               -- Initial value of register, '0', '1'
        -- )
      -- port map (
        -- Q   => rx_data_en_r(i),   -- 1-bit output: Data
        -- C   => clk(i),            -- 1-bit input: Clock
        -- --CE  => '1',             -- 1-bit input: Clock enable
        -- D   => rx_data_en_int(i)  -- 1-bit input: Data
        -- --R   => '0'              -- 1-bit input: Synchronous reset
        -- );     
        
      -- i_clock_converter : axis_clock_converter_0
      -- port map(
        -- s_axis_aresetn  =>  resetn(i),
        -- m_axis_aresetn  =>  aresetn_in,
        -- s_axis_aclk     =>  clk(i),
        -- s_axis_tvalid   =>  rx_data_en_r(i),
        -- s_axis_tready   =>  cc_overflow_tready(i),
        -- s_axis_tdata    =>  rx_data_r(i),
        -- m_axis_aclk     =>  aclk_in,
        -- m_axis_tvalid   =>  m_axis_tvalid_int(i),
        -- m_axis_tready   =>  m_axis_tvalid_int(i),
        -- m_axis_tdata    =>  m_axis_tdata_int(i)
        -- );
        
      -- cc_overflow_int(i) <= not(cc_overflow_tready(i)) and rx_data_en_r(i);
        
      -- i_FDRE_cc_overflow : FDRE
      -- generic map (
        -- INIT => '0'          -- Initial value of register, '0', '1'
        -- )
      -- port map (
        -- Q   => dig_iq_cc_overflow(i), -- 1-bit output: Data
        -- C   => clk(i),                -- 1-bit input: Clock
        -- CE  => cc_overflow_int(i),    -- 1-bit input: Clock enable
        -- D   => '1',                   -- 1-bit input: Data
        -- R   => resetn(i)              -- 1-bit input: Synchronous reset
        -- );
        
      -----------------------------------------------------------------------------------------------
      -- R&S Documentation states:
      --  
      --  TX_DATA_READY signal -- TX channel is receptive. After the deactivation of this signal,
      --                          up to five more enabled data samples are allowed on the TX_DATA_DAT
      --                          bus.
      --  Thus, we can pipeline the tx_data between the output of the FIFO and the R&S core.
      --
      --  ** PIPELINING IS CURRENTLY COMMENTED OUT **
      -----------------------------------------------------------------------------------------------
      
      -- i_tx_fifo : axis_data_fifo_0
      -- port map(
        -- s_axis_aresetn  =>  aresetn_in,
        -- s_axis_aclk     =>  aclk_in,
        -- s_axis_tvalid   =>  s_axis_tvalid(i),
        -- s_axis_tready   =>  s_axis_tready_int(i),
        -- s_axis_tdata    =>  s_axis_tdata(i),
        -- m_axis_aclk     =>  clk(i),
        -- m_axis_tvalid   =>  tx_fifo_m_tvalid(i),
        -- m_axis_tready   =>  tx_data_ready(i),
        -- m_axis_tdata    =>  tx_fifo_m_tdata(i)
        -- );
      
      --tx_fifo_overflow_int(i) <= not(s_axis_tready_int(i)) and s_axis_tvalid(i);
      
      -- i_FDRE_tx_overflow : FDRE
      -- generic map (
        -- INIT => '0'          -- Initial value of register, '0', '1'
        -- )
      -- port map (
        -- Q   => dig_iq_tx_overflow(i),   -- 1-bit output: Data
        -- C   => aclk_in,                    -- 1-bit input: Clock
        -- CE  => tx_fifo_overflow_int(i), -- 1-bit input: Clock enable
        -- D   => '1',                     -- 1-bit input: Data
        -- R   => aresetn_in                  -- 1-bit input: Synchronous reset
        -- );

--      tx_data_en_int(i)  <=  tx_fifo_m_tvalid(i) and tx_data_ready(i);     
        
      --i_FD_tx_data_en : FD --RE
      --generic map (
      --  INIT => '0'          -- Initial value of register, '0', '1'
      --  )
      --port map (
      --  Q   => tx_data_en_r(i),   -- 1-bit output: Data
      --  C   => clk(i),            -- 1-bit input: Clock
      --  --CE  => '1',               -- 1-bit input: Clock enable
      --  D   => tx_data_en_int(i) -- 1-bit input: Data
      --  --R   => '0'                -- 1-bit input: Synchronous reset
      --  );
        
--      tx_data_en_r(i) <= tx_data_en_int(i);

      --GEN_2:
      --for j in 0 to 239 generate
      --  begin 
      --  
      --    i_FD_tx_data : FD --RE
      --    generic map (
      --      INIT => '0'          -- Initial value of register, '0', '1'
      --      )
      --    port map (
      --      Q   => tx_data_r(i)(j),   -- 1-bit output: Data
      --      C   => clk(i),            -- 1-bit input: Clock
      --      --CE  => '1',               -- 1-bit input: Clock enable
      --      D   => tx_fifo_m_tdata(i)(j)     -- 1-bit input: Data
      --      --R   => '0'                -- 1-bit input: Synchronous reset
      --      );
      --      
      --  end generate;
        
--        tx_data_r(i) <= tx_fifo_m_tdata(i);
        
    end generate;

  -----------------------------------------------------------

 

end structural;
