library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity qsfp_intfc_v1_0 is
  generic (
    -- Users to add parameters here
        FPGA_REVISION_DATE                    : std_logic_vector(31 downto 0) := x"0603_2024";
        MINOR_REV                             : std_logic_vector( 7 downto 0) := x"01";
    -- User parameters ends
    -- Do not modify the parameters beyond this line


    -- Parameters of Axi Slave Bus Interface S00_AXI
    C_S00_AXI_DATA_WIDTH                      : integer := 32;
    C_S00_AXI_ADDR_WIDTH                      : integer := 7
  );
  port (
    -- Users to add ports here
    clk_125_in                                : in  std_logic;
    clk_125_reset_n_in                        : in  std_logic;

    clk_250_in                                : in  std_logic;
    clk_250_reset_n_in                        : in  std_logic;

    rx_device_clk_in                          : in  std_logic;  
    tx_device_clk_in                          : in  std_logic;  

    clkin8_in                                 : in  std_logic;
--    sysref_in                                 : in  std_logic;
    ref_clk_div2_in                           : in  std_logic;

-----------------
    QSFP1_SI570_CLOCK_P                       : in  std_logic;
    QSFP1_SI570_CLOCK_N                       : in  std_logic;
    QSFP1_TX1_P                               : out std_logic;
    QSFP1_TX1_N                               : out std_logic;
    QSFP1_RX1_P                               : in  std_logic;
    QSFP1_RX1_N                               : in  std_logic;
--
    QSFP1_TX2_P                               : out std_logic;
    QSFP1_TX2_N                               : out std_logic;
    QSFP1_RX2_P                               : in  std_logic;
    QSFP1_RX2_N                               : in  std_logic;
--
    QSFP1_TX3_P                               : out std_logic;
    QSFP1_TX3_N                               : out std_logic;
    QSFP1_RX3_P                               : in  std_logic;
    QSFP1_RX3_N                               : in  std_logic;
--
    QSFP1_TX4_P                               : out std_logic;
    QSFP1_TX4_N                               : out std_logic;
    QSFP1_RX4_P                               : in  std_logic;
    QSFP1_RX4_N                               : in  std_logic;

    QSFP1_RESETL_LS                           : out std_logic;     
    QSFP1_MODPRSL_LS                          : in  std_logic;      
    QSFP1_INTL_LS                             : in  std_logic;     
-----------------
    QSFP2_SI570_CLOCK_P                       : in  std_logic;
    QSFP2_SI570_CLOCK_N                       : in  std_logic;
    QSFP2_TX1_P                               : out std_logic;
    QSFP2_TX1_N                               : out std_logic;
    QSFP2_RX1_P                               : in  std_logic;
    QSFP2_RX1_N                               : in  std_logic;
--      
    QSFP2_TX2_P                               : out std_logic;
    QSFP2_TX2_N                               : out std_logic;
    QSFP2_RX2_P                               : in  std_logic;
    QSFP2_RX2_N                               : in  std_logic;
--      
    QSFP2_TX3_P                               : out std_logic;
    QSFP2_TX3_N                               : out std_logic;
    QSFP2_RX3_P                               : in  std_logic;
    QSFP2_RX3_N                               : in  std_logic;
--      
    QSFP2_TX4_P                               : out std_logic;
    QSFP2_TX4_N                               : out std_logic;
    QSFP2_RX4_P                               : in  std_logic;
    QSFP2_RX4_N                               : in  std_logic;
        
    QSFP2_RESETL_LS                           : out std_logic;     
    QSFP2_MODPRSL_LS                          : in  std_logic;      
    QSFP2_INTL_LS                             : in  std_logic;     
-----------------
    QSFP3_SI570_CLOCK_P                       : in  std_logic;
    QSFP3_SI570_CLOCK_N                       : in  std_logic;
    QSFP3_TX1_P                               : out std_logic;
    QSFP3_TX1_N                               : out std_logic;
    QSFP3_RX1_P                               : in  std_logic;
    QSFP3_RX1_N                               : in  std_logic;
--      
    QSFP3_TX2_P                               : out std_logic;
    QSFP3_TX2_N                               : out std_logic;
    QSFP3_RX2_P                               : in  std_logic;
    QSFP3_RX2_N                               : in  std_logic;
--      
    QSFP3_TX3_P                               : out std_logic;
    QSFP3_TX3_N                               : out std_logic;
    QSFP3_RX3_P                               : in  std_logic;
    QSFP3_RX3_N                               : in  std_logic;
--      
    QSFP3_TX4_P                               : out std_logic;
    QSFP3_TX4_N                               : out std_logic;
    QSFP3_RX4_P                               : in  std_logic;
    QSFP3_RX4_N                               : in  std_logic;
        
    QSFP3_RESETL_LS                           : out std_logic;     
    QSFP3_MODPRSL_LS                          : in  std_logic;      
    QSFP3_INTL_LS                             : in  std_logic;     
-----------------
    QSFP4_SI570_CLOCK_P                       : in  std_logic;
    QSFP4_SI570_CLOCK_N                       : in  std_logic;
    QSFP4_TX1_P                               : out std_logic;
    QSFP4_TX1_N                               : out std_logic;
    QSFP4_RX1_P                               : in  std_logic;
    QSFP4_RX1_N                               : in  std_logic;
--
    QSFP4_TX2_P                               : out std_logic;
    QSFP4_TX2_N                               : out std_logic;
    QSFP4_RX2_P                               : in  std_logic;
    QSFP4_RX2_N                               : in  std_logic;
--
    QSFP4_TX3_P                               : out std_logic;
    QSFP4_TX3_N                               : out std_logic;
    QSFP4_RX3_P                               : in  std_logic;
    QSFP4_RX3_N                               : in  std_logic;
--
    QSFP4_TX4_P                               : out std_logic;
    QSFP4_TX4_N                               : out std_logic;
    QSFP4_RX4_P                               : in  std_logic;
    QSFP4_RX4_N                               : in  std_logic;

    QSFP4_RESETL_LS                           : out std_logic;     
    QSFP4_MODPRSL_LS                          : in  std_logic;         
    QSFP4_INTL_LS                             : in  std_logic;  
----
    qsfp1_aclk_out                            : out std_logic;
    qsfp1_aresetn_out                         : out std_logic;
    qsfp1_rx_tdata_240b_out                   : out std_logic_vector(239 downto 0);
    qsfp1_rx_tvalid_240b_out                  : out std_logic;
    qsfp1_rx_data_ready_in                    : in  std_logic;

    qsfp1_tx_tdata_240b_in                    : in  std_logic_vector(239 downto 0);
    qsfp1_tx_tvalid_240b_in                   : in  std_logic;
    qsfp1_tx_tready_240b_out                  : out std_logic; 

    qsfp1_rx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp1_rx_overflow_240b_cnt_in             : in  std_logic_vector(31 downto 0);
    qsfp1_rx_fifo_aempty_512b_cnt_in          : in  std_logic_vector(31 downto 0);
    qsfp1_rx_data_ready_cnt_in                : in  std_logic_vector(31 downto 0);
    qsfp1_tx_tvalid_128b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp1_tx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp1_rx_overflow_128b_cnt_in             : in  std_logic_vector(31 downto 0);
----
    qsfp2_aclk_out                            : out std_logic;
    qsfp2_aresetn_out                         : out std_logic;
    qsfp2_rx_tdata_240b_out                   : out std_logic_vector(239 downto 0);
    qsfp2_rx_tvalid_240b_out                  : out std_logic;
    qsfp2_rx_data_ready_in                    : in  std_logic;

    qsfp2_tx_tdata_240b_in                    : in  std_logic_vector(239 downto 0);
    qsfp2_tx_tvalid_240b_in                   : in  std_logic;
    qsfp2_tx_tready_240b_out                  : out std_logic; 

    qsfp2_rx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp2_rx_overflow_240b_cnt_in             : in  std_logic_vector(31 downto 0);
    qsfp2_rx_fifo_aempty_512b_cnt_in          : in  std_logic_vector(31 downto 0);
    qsfp2_rx_data_ready_cnt_in                : in  std_logic_vector(31 downto 0);
    qsfp2_tx_tvalid_128b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp2_tx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp2_rx_overflow_128b_cnt_in             : in  std_logic_vector(31 downto 0);
----
    qsfp3_aclk_out                            : out std_logic;
    qsfp3_aresetn_out                         : out std_logic;
    qsfp3_rx_tdata_240b_out                   : out std_logic_vector(239 downto 0);
    qsfp3_rx_tvalid_240b_out                  : out std_logic;
    qsfp3_rx_data_ready_in                    : in  std_logic;

    qsfp3_tx_tdata_240b_in                    : in  std_logic_vector(239 downto 0);
    qsfp3_tx_tvalid_240b_in                   : in  std_logic;
    qsfp3_tx_tready_240b_out                  : out std_logic; 

    qsfp3_rx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp3_rx_overflow_240b_cnt_in             : in  std_logic_vector(31 downto 0);
    qsfp3_rx_fifo_aempty_512b_cnt_in          : in  std_logic_vector(31 downto 0);
    qsfp3_rx_data_ready_cnt_in                : in  std_logic_vector(31 downto 0);
    qsfp3_tx_tvalid_128b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp3_tx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp3_rx_overflow_128b_cnt_in             : in  std_logic_vector(31 downto 0);
--
    qsfp4_aclk_out                            : out std_logic;
    qsfp4_aresetn_out                         : out std_logic;
    qsfp4_rx_tdata_240b_out                   : out std_logic_vector(239 downto 0);
    qsfp4_rx_tvalid_240b_out                  : out std_logic;
    qsfp4_rx_data_ready_in                    : in  std_logic;

    qsfp4_tx_tdata_240b_in                    : in  std_logic_vector(239 downto 0);
    qsfp4_tx_tvalid_240b_in                   : in  std_logic;
    qsfp4_tx_tready_240b_out                  : out std_logic; 

    qsfp4_rx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp4_rx_overflow_240b_cnt_in             : in  std_logic_vector(31 downto 0);
    qsfp4_rx_fifo_aempty_512b_cnt_in          : in  std_logic_vector(31 downto 0);
    qsfp4_rx_data_ready_cnt_in                : in  std_logic_vector(31 downto 0);
    qsfp4_tx_tvalid_128b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp4_tx_tvalid_240b_cnt_in               : in  std_logic_vector(31 downto 0);
    qsfp4_rx_overflow_128b_cnt_in             : in  std_logic_vector(31 downto 0);

    tx_tvalid_256b_cnt_in                     : in  std_logic_vector(31 downto 0);
    mem_xfer_tx_upload_tvalid_256b_cnt_in     : in  std_logic_vector(31 downto 0);
    dac_tx_tvalid_256b_cnt_in                 : in  std_logic_vector(31 downto 0);
    adc_rx_tvalid_256b_cnt_in                 : in  std_logic_vector(31 downto 0);
    
    cnt_reset_out                             : out std_logic;

    slv_reg9_out                              : out std_logic_vector(31 downto 0);
    slv_reg10_out                             : out std_logic_vector(31 downto 0);

    slv_reg31_out                             : out std_logic_vector(31 downto 0);

    slv_reg38_out                             : out std_logic_vector(31 downto 0);
                 
    slv_reg45_out                             : out std_logic_vector(31 downto 0);

    slv_reg52_out                             : out std_logic_vector(31 downto 0);

   
    -- User ports ends
    -- Do not modify the ports beyond this line

    -- Ports of Axi Slave Bus Interface S00_AXI
    sys_cpu_clk_in                            : in std_logic;
    s00_axi_aresetn_in                        : in std_logic;
    s00_axi_awaddr                            : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
    s00_axi_awprot                            : in std_logic_vector(2 downto 0);
    s00_axi_awvalid                           : in std_logic;
    s00_axi_awready                           : out std_logic;
    s00_axi_wdata                             : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
    s00_axi_wstrb                             : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
    s00_axi_wvalid                            : in std_logic;
    s00_axi_wready                            : out std_logic;
    s00_axi_bresp                             : out std_logic_vector(1 downto 0);
    s00_axi_bvalid                            : out std_logic;
    s00_axi_bready                            : in std_logic;
    s00_axi_araddr                            : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
    s00_axi_arprot                            : in std_logic_vector(2 downto 0);
    s00_axi_arvalid                           : in std_logic;
    s00_axi_arready                           : out std_logic;
    s00_axi_rdata                             : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
    s00_axi_rresp                             : out std_logic_vector(1 downto 0);
    s00_axi_rvalid                            : out std_logic;
    s00_axi_rready                            : in std_logic
  );
end qsfp_intfc_v1_0;

architecture arch_imp of qsfp_intfc_v1_0 is

  signal fpga_revision_date_r             : std_logic_vector(31 downto 0) := (others => '0');
  attribute keep                          : string;
  attribute keep of fpga_revision_date_r  : signal is "true";

  signal minor_rev_r                      : std_logic_vector( 7 downto 0) := (others => '0');
  attribute keep of minor_rev_r           : signal is "true";

  signal dig_iq_cmd_addr_i                : std_logic_vector (11 downto 0);
  signal dig_iq_cmd_sel_i                 : std_logic_vector ( 2 downto 0);
  signal dig_iq_cmd_strb_i                : std_logic;
  signal dig_iq_cmd_wdata_i               : std_logic_vector (31 downto 0);
  signal dig_iq_cmd_write_i               : std_logic;

--  signal dig_iq_cmd_addr                  : std_logic_vector (11 downto 0);
  signal dig_iq_cmd_rdata                 : std_logic_vector (31 downto 0);
  signal dig_iq_cmd_ready                 : std_logic;
--  signal dig_iq_cmd_sel                   : std_logic_vector ( 2 downto 0);
--  signal dig_iq_cmd_strb                  : std_logic;
--  signal dig_iq_cmd_wdata                 : std_logic_vector (31 downto 0);
--  signal dig_iq_cmd_write                 : std_logic;
  signal dig_iq_interface_ready           : std_logic_vector ( 1 downto 0);
  signal dig_iq_interface_reset           : std_logic_vector ( 1 downto 0);

  signal vio_dig_iq_cmd_addr              : std_logic_vector (11 downto 0);
  signal vio_dig_iq_cmd_sel               : std_logic_vector ( 2 downto 0);
  signal vio_dig_iq_cmd_strb              : std_logic;
  signal vio_dig_iq_cmd_wdata             : std_logic_vector (31 downto 0);
  signal vio_dig_iq_cmd_write             : std_logic;
  signal vio_enable                       : std_logic;

--
  signal qsfp1_aclk                       : std_logic;
  signal qsfp1_aresetn                    : std_logic;

  signal qsfp1_rx_rxn                     : std_logic_vector(3 downto 0);
  signal qsfp1_rx_rxp                     : std_logic_vector(3 downto 0);
  signal qsfp1_tx_txn                     : std_logic_vector(3 downto 0);
  signal qsfp1_tx_txp                     : std_logic_vector(3 downto 0); 
  signal qsfp1_reset_n                    : std_logic;   
  signal qsfp1_modprsl                    : std_logic;   
  signal qsfp1_intl                       : std_logic;   

  signal qsfp1_rx_tvalid_240b             : std_logic;
  signal qsfp1_tx_tready_240b             : std_logic;
--
  signal qsfp2_aclk                       : std_logic;
  signal qsfp2_aresetn                    : std_logic;

  signal qsfp2_rx_rxn                     : std_logic_vector(3 downto 0);
  signal qsfp2_rx_rxp                     : std_logic_vector(3 downto 0);
  signal qsfp2_tx_txn                     : std_logic_vector(3 downto 0);
  signal qsfp2_tx_txp                     : std_logic_vector(3 downto 0); 
  signal qsfp2_reset_n                    : std_logic;   
  signal qsfp2_modprsl                    : std_logic;   
  signal qsfp2_intl                       : std_logic;   

  signal qsfp2_rx_tvalid_240b             : std_logic;
  signal qsfp2_tx_tready_240b             : std_logic;
--
  signal qsfp3_aclk                       : std_logic;
  signal qsfp3_aresetn                    : std_logic;

  signal qsfp3_rx_rxn                     : std_logic_vector(3 downto 0);
  signal qsfp3_rx_rxp                     : std_logic_vector(3 downto 0);
  signal qsfp3_tx_txn                     : std_logic_vector(3 downto 0);
  signal qsfp3_tx_txp                     : std_logic_vector(3 downto 0);
  signal qsfp3_reset_n                    : std_logic;   
  signal qsfp3_modprsl                    : std_logic;   
  signal qsfp3_intl                       : std_logic;   

  signal qsfp3_rx_tvalid_240b             : std_logic;
  signal qsfp3_tx_tready_240b             : std_logic;
--
  signal qsfp4_aclk                       : std_logic;
  signal qsfp4_aresetn                    : std_logic;

  signal qsfp4_rx_rxn                     : std_logic_vector(3 downto 0);
  signal qsfp4_rx_rxp                     : std_logic_vector(3 downto 0);
  signal qsfp4_tx_txn                     : std_logic_vector(3 downto 0);
  signal qsfp4_tx_txp                     : std_logic_vector(3 downto 0);
  signal qsfp4_reset_n                    : std_logic;   
  signal qsfp4_modprsl                    : std_logic;   
  signal qsfp4_intl                       : std_logic;   

  signal qsfp4_rx_tvalid_240b             : std_logic;
  signal qsfp4_tx_tready_240b             : std_logic;

--
  signal tick_1ms                         : std_logic;

  signal clk_125_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
  signal clk_125_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
  signal clk_125_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');

  signal clk_250_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
  signal clk_250_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
  signal clk_250_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');

  signal qsfp1_aclk_tick_1ms_r            : std_logic_vector(0 to 2) := (others => '0');
  signal qsfp1_aclk_freq_r                : std_logic_vector(31 downto 0) := (others => '0');
  signal qsfp1_aclk_cnt_r                 : std_logic_vector(31 downto 0) := (others => '0');

  signal qsfp2_aclk_tick_1ms_r             : std_logic_vector(0 to 2) := (others => '0');
  signal qsfp2_aclk_freq_r                 : std_logic_vector(31 downto 0) := (others => '0');
  signal qsfp2_aclk_cnt_r                  : std_logic_vector(31 downto 0) := (others => '0');

  signal qsfp3_aclk_tick_1ms_r             : std_logic_vector(0 to 2) := (others => '0');
  signal qsfp3_aclk_freq_r                 : std_logic_vector(31 downto 0) := (others => '0');
  signal qsfp3_aclk_cnt_r                  : std_logic_vector(31 downto 0) := (others => '0');

  signal qsfp4_aclk_tick_1ms_r             : std_logic_vector(0 to 2) := (others => '0');
  signal qsfp4_aclk_freq_r                 : std_logic_vector(31 downto 0) := (others => '0');
  signal qsfp4_aclk_cnt_r                  : std_logic_vector(31 downto 0) := (others => '0');

  signal rx_device_clk_tick_1ms_r           : std_logic_vector(0 to 2) := (others => '0');
  signal rx_device_clk_freq_r               : std_logic_vector(31 downto 0) := (others => '0');      
  signal rx_device_clk_cnt_r                : std_logic_vector(31 downto 0) := (others => '0');      

  signal tx_device_clk_tick_1ms_r           : std_logic_vector(0 to 2) := (others => '0');
  signal tx_device_clk_freq_r               : std_logic_vector(31 downto 0) := (others => '0');
  signal tx_device_clk_cnt_r                : std_logic_vector(31 downto 0) := (others => '0');

  signal clkin8_tick_1ms_r                  : std_logic_vector(0 to 2) := (others => '0');
  signal clkin8_freq_r                      : std_logic_vector(31 downto 0) := (others => '0');
  signal clkin8_cnt_r                       : std_logic_vector(31 downto 0) := (others => '0');

  signal sys_cpu_clk_tick_1ms_r             : std_logic_vector(0 to 2) := (others => '0');
  signal sys_cpu_clk_freq_r                 : std_logic_vector(31 downto 0) := (others => '0');
  signal sys_cpu_clk_cnt_r                  : std_logic_vector(31 downto 0) := (others => '0');

  signal ref_clk_div2_tick_1ms_r            : std_logic_vector(0 to 2) := (others => '0');
  signal ref_clk_div2_freq_r                : std_logic_vector(31 downto 0) := (others => '0');
  signal ref_clk_div2_cnt_r                 : std_logic_vector(31 downto 0) := (others => '0');

  signal slv_reg0                           : std_logic_vector(31 downto 0);
  signal slv_reg1                           : std_logic_vector(31 downto 0);
  signal slv_reg2                           : std_logic_vector(31 downto 0);
  signal slv_reg3                           : std_logic_vector(31 downto 0);
  signal slv_reg4                           : std_logic_vector(31 downto 0);
  signal slv_reg5                           : std_logic_vector(31 downto 0);
  signal slv_reg6                           : std_logic_vector(31 downto 0);
  signal slv_reg7                           : std_logic_vector(31 downto 0);
  signal slv_reg8                           : std_logic_vector(31 downto 0);

  signal vio_cnt_reset                      : std_logic;
  signal cnt_rst                            : std_logic;

  signal dig_iq_mode_50g_40g_n              : std_logic;

  signal fsm_dig_iq_cmd_strb                : std_logic;
  signal fsm_dig_iq_cmd_addr                : std_logic_vector (11 downto 0);
  signal fsm_dig_iq_cmd_write               : std_logic;
  signal fsm_dig_iq_cmd_sel                 : std_logic_vector ( 2 downto 0);
  signal fsm_dig_iq_cmd_wdata               : std_logic_vector (31 downto 0);
  signal fsm_running                        : std_logic;

  signal dig_iq_cmd_rdata_1                 : std_logic_vector (31 downto 0);
  signal dig_iq_cmd_ready_1                 : std_logic;
  signal dig_iq_interface_ready_1           : std_logic_vector ( 1 downto 0);
  signal dig_iq_interface_reset_1           : std_logic_vector ( 1 downto 0);


  signal fsm_dig_iq_cmd_strb_1              : std_logic;
  signal fsm_dig_iq_cmd_addr_1              : std_logic_vector (11 downto 0);
  signal fsm_dig_iq_cmd_write_1             : std_logic;
  signal fsm_dig_iq_cmd_sel_1               : std_logic_vector ( 2 downto 0);
  signal fsm_dig_iq_cmd_wdata_1             : std_logic_vector (31 downto 0);
  signal fsm_running_1                      : std_logic;
  
  signal s00_axi_areset                   : std_logic;

  signal rx_data_ready                    : std_logic_vector(1 downto 0);
  signal rx_data_ready_1                    : std_logic_vector(1 downto 0);
  
begin

  cnt_reset_out     <= cnt_rst;--vio_cnt_reset when vio_enable = '1' else cnt_rst;
  s00_axi_areset    <= not s00_axi_aresetn_in;
  
  -- Instantiation of Axi Bus Interface S00_AXI
  qsfp_intfc_v1_0_S00_AXI_inst : entity work.qsfp_intfc_v1_0_S00_AXI
    generic map (
      C_S_AXI_DATA_WIDTH        => C_S00_AXI_DATA_WIDTH,
      C_S_AXI_ADDR_WIDTH        => C_S00_AXI_ADDR_WIDTH
    )
  port map (

    slv_reg0_in                 => slv_reg0,                                -- 0x8000_0000  
    slv_reg1_in                 => slv_reg1,                                -- 0x8000_0004         
    slv_reg2_in                 => slv_reg2,                                -- 0x8000_0008  
    slv_reg3_out                => slv_reg3,                                -- 0x8000_000C        
    slv_reg4_out                => slv_reg4,                                -- 0x8000_0010         
    slv_reg5_out                => slv_reg5,                                -- 0x8000_0014        
    slv_reg6_out                => slv_reg6,                                -- 0x8000_0018        
    slv_reg7_out                => slv_reg7,                                -- 0x8000_001C         
    slv_reg8_out                => slv_reg8,                                -- 0x8000_0020  

    slv_reg9_out                => slv_reg9_out,                            -- 0x8000_0024    
    slv_reg10_out               => slv_reg10_out,                           -- 0x8000_0028     

    slv_reg11_in                => clk_125_freq_r,                          -- 0x8000_002C 
    slv_reg12_in                => clk_125_cnt_r,                           -- 0x8000_0030
    slv_reg13_in                => clk_250_freq_r,                          -- 0x8000_0034
    slv_reg14_in                => clk_250_cnt_r,                           -- 0x8000_0038
    slv_reg15_in                => rx_device_clk_freq_r,                    -- 0x8000_003C 
    slv_reg16_in                => tx_device_clk_freq_r,                    -- 0x8000_0040
    slv_reg17_in                => qsfp1_aclk_freq_r,                       -- 0x8000_0044                 
    slv_reg18_in                => qsfp1_aclk_cnt_r,                        -- 0x8000_0048                 
    slv_reg19_in                => qsfp2_aclk_freq_r,                       -- 0x8000_004C                     
    slv_reg20_in                => qsfp2_aclk_cnt_r,                        -- 0x8000_0050                     

    slv_reg21_in                => qsfp3_aclk_freq_r,                       -- 0x8000_0054                 
    slv_reg22_in                => qsfp3_aclk_cnt_r,                        -- 0x8000_0058
    slv_reg23_in                => qsfp4_aclk_freq_r,                       -- 0x8000_005C  
    slv_reg24_in                => qsfp4_aclk_cnt_r,                        -- 0x8000_0060

    slv_reg25_in                => qsfp1_rx_tvalid_240b_cnt_in,             -- 0x8000_0064  
    slv_reg26_in                => qsfp1_rx_overflow_240b_cnt_in,           -- 0x8000_0068  
    slv_reg27_in                => qsfp1_rx_fifo_aempty_512b_cnt_in,        -- 0x8000_006C
    slv_reg28_in                => qsfp1_rx_data_ready_cnt_in,              -- 0x8000_0070
    slv_reg29_in                => qsfp1_tx_tvalid_128b_cnt_in,             -- 0x8000_0074 
    slv_reg30_in                => qsfp1_tx_tvalid_240b_cnt_in,             -- 0x8000_0078
    slv_reg31_in                => qsfp1_rx_overflow_128b_cnt_in,           -- 0x8000_007C  

    slv_reg32_in                => qsfp2_rx_tvalid_240b_cnt_in,             -- 0x8000_0080
    slv_reg33_in                => qsfp2_rx_overflow_240b_cnt_in,           -- 0x8000_0084  
    slv_reg34_in                => qsfp2_rx_fifo_aempty_512b_cnt_in,        -- 0x8000_0088  
    slv_reg35_in                => qsfp2_rx_data_ready_cnt_in,              -- 0x8000_008C
    slv_reg36_in                => qsfp2_tx_tvalid_128b_cnt_in,             -- 0x8000_0090
    slv_reg37_in                => qsfp2_tx_tvalid_240b_cnt_in,             -- 0x8000_0094 
    slv_reg38_in                => qsfp2_rx_overflow_128b_cnt_in,           -- 0x8000_0098  

    slv_reg39_in                => qsfp3_rx_tvalid_240b_cnt_in,             -- 0x8000_009C  
    slv_reg40_in                => qsfp3_rx_overflow_240b_cnt_in,           -- 0x8000_00A0
    slv_reg41_in                => qsfp3_rx_fifo_aempty_512b_cnt_in,        -- 0x8000_00A4  
    slv_reg42_in                => qsfp3_rx_data_ready_cnt_in,              -- 0x8000_00A8  
    slv_reg43_in                => qsfp3_tx_tvalid_128b_cnt_in,             -- 0x8000_00AC
    slv_reg44_in                => qsfp3_tx_tvalid_240b_cnt_in,             -- 0x8000_00B0
    slv_reg45_in                => qsfp3_rx_overflow_128b_cnt_in,           -- 0x8000_00B4  

    slv_reg46_in                => qsfp4_rx_tvalid_240b_cnt_in,             -- 0x8000_00B8
    slv_reg47_in                => qsfp4_rx_overflow_240b_cnt_in,           -- 0x8000_00BC  
    slv_reg48_in                => qsfp4_rx_fifo_aempty_512b_cnt_in,        -- 0x8000_00C0
    slv_reg49_in                => qsfp4_rx_data_ready_cnt_in,              -- 0x8000_00C4  
    slv_reg50_in                => qsfp4_tx_tvalid_128b_cnt_in,             -- 0x8000_00C8  
    slv_reg51_in                => qsfp4_tx_tvalid_240b_cnt_in,             -- 0x8000_00CC
    slv_reg52_in                => qsfp4_rx_overflow_128b_cnt_in,           -- 0x8000_00D0  

    slv_reg53_in                => adc_rx_tvalid_256b_cnt_in,               -- 0x8000_00D4
    slv_reg54_in                => (others => '0'),                         -- 0x8000_00D8

    slv_reg55_in                => (others => '0'),                         -- 0x8000_00DC
    slv_reg56_in                => tx_tvalid_256b_cnt_in,                   -- 0x8000_00E0
    slv_reg57_in                => mem_xfer_tx_upload_tvalid_256b_cnt_in,   -- 0x8000_00E4
    slv_reg58_in                => (others => '0'),                         -- 0x8000_00E8
    slv_reg59_in                => (others => '0'),                         -- 0x8000_00EC
    slv_reg60_in                => dac_tx_tvalid_256b_cnt_in,               -- 0x8000_00F0
    slv_reg61_in                => (others => '0'),                         -- 0x8000_00F4
    slv_reg62_in                => (others => '0'),                         -- 0x8000_00F8
    slv_reg63_in                => (others => '0'),                         -- 0x8000_00FC

    S_AXI_ACLK                  => sys_cpu_clk_in,
    S_AXI_ARESETN               => s00_axi_aresetn_in,
    S_AXI_AWADDR                => s00_axi_awaddr,
    S_AXI_AWPROT                => s00_axi_awprot,
    S_AXI_AWVALID               => s00_axi_awvalid,
    S_AXI_AWREADY               => s00_axi_awready,
    S_AXI_WDATA                 => s00_axi_wdata,
    S_AXI_WSTRB                 => s00_axi_wstrb,
    S_AXI_WVALID                => s00_axi_wvalid,
    S_AXI_WREADY                => s00_axi_wready,
    S_AXI_BRESP                 => s00_axi_bresp,
    S_AXI_BVALID                => s00_axi_bvalid,
    S_AXI_BREADY                => s00_axi_bready,
    S_AXI_ARADDR                => s00_axi_araddr,
    S_AXI_ARPROT                => s00_axi_arprot,
    S_AXI_ARVALID               => s00_axi_arvalid,
    S_AXI_ARREADY               => s00_axi_arready,
    S_AXI_RDATA                 => s00_axi_rdata,
    S_AXI_RRESP                 => s00_axi_rresp,
    S_AXI_RVALID                => s00_axi_rvalid,
    S_AXI_RREADY                => s00_axi_rready
  );

------------
  slv_reg0                  <= fpga_revision_date_r;        -- 0x8000_0000       
------------
  slv_reg1(0)               <= dig_iq_interface_ready(0);              
  slv_reg1(1)               <= qsfp1_modprsl; 
  slv_reg1(2)               <= qsfp1_intl;    
  slv_reg1(3)               <= '0';
  slv_reg1(4)               <= dig_iq_interface_ready(1);              
  slv_reg1(5)               <= qsfp2_modprsl; 
  slv_reg1(6)               <= qsfp2_intl;    
  slv_reg1(7)               <= '0';
  slv_reg1(8)               <= dig_iq_interface_ready_1(0);              
  slv_reg1(9)               <= qsfp3_modprsl; 
  slv_reg1(10)              <= qsfp3_intl;    
  slv_reg1(11)              <= '0';
  slv_reg1(12)              <= dig_iq_interface_ready_1(1);              
  slv_reg1(13)              <= qsfp4_modprsl; 
  slv_reg1(14)              <= qsfp4_intl;    
  slv_reg1(15)              <= '0';

  slv_reg1(23 downto 16)    <= (others => '0');                     
  slv_reg1(31 downto 24)    <= minor_rev_r;                                       -- 0x8000_0004         
------------
  slv_reg2                  <= (others => '0');  --dig_iq_cmd_rdata;              -- 0x8000_0008        
------------
--
--  dig_iq_cmd_sel_i          <= slv_reg3(17 downto 16);         
--  dig_iq_cmd_strb_i         <= slv_reg3(12);                                    -- 0x8000_0014 
--  dig_iq_cmd_addr_i         <= slv_reg3(11 downto 0);                           -- 0x8000_000C
------------
--             <= slv_reg4(17 downto 16);                                         -- 0x8000_0010 
------------
  qsfp1_reset_n           <= slv_reg5(0);                                         -- 0x8000_0014 
--                        <= slv_reg5(3 dwonto 1);
  qsfp2_reset_n           <= slv_reg5(4);
--                        <= slv_reg5(7 dwonto 5);
  qsfp3_reset_n           <= slv_reg5(8);
--                        <= slv_reg5(11 dwonto 9);
  qsfp4_reset_n           <= slv_reg5(12);
--                        <= slv_reg5(31 dwonto 13);
------------
  dig_iq_cmd_wdata_i        <= slv_reg6(31 downto 0);                             -- 0x8000_0018 
------------
  dig_iq_cmd_write_i        <= slv_reg7(0);                                       -- 0x8000_001C 
------------
  dig_iq_mode_50g_40g_n     <= slv_reg8(0);                                       -- 0x8000_0020 
--                          <= slv_reg8(24);
--                          <= slv_reg8(28);
  cnt_rst                   <= slv_reg8(31);

  -- Add user logic here
-------
  QSFP1_TX1_P         <= qsfp1_tx_txp(0);                
  QSFP1_TX1_N         <= qsfp1_tx_txn(0);               
  qsfp1_rx_rxp(0)     <= QSFP1_RX1_P;                   
  qsfp1_rx_rxn(0)     <= QSFP1_RX1_N;                   

  QSFP1_TX2_P         <= qsfp1_tx_txp(1);
  QSFP1_TX2_N         <= qsfp1_tx_txn(1);
  qsfp1_rx_rxp(1)     <= QSFP1_RX2_P;
  qsfp1_rx_rxn(1)     <= QSFP1_RX2_N;

  QSFP1_TX3_P         <= qsfp1_tx_txp(2);
  QSFP1_TX3_N         <= qsfp1_tx_txn(2);
  qsfp1_rx_rxp(2)     <= QSFP1_RX3_P;
  qsfp1_rx_rxn(2)     <= QSFP1_RX3_N;

  QSFP1_TX4_P         <= qsfp1_tx_txp(3);
  QSFP1_TX4_N         <= qsfp1_tx_txn(3);
  qsfp1_rx_rxp(3)     <= QSFP1_RX4_P;
  qsfp1_rx_rxn(3)     <= QSFP1_RX4_N;

  QSFP1_RESETL_LS     <= qsfp1_reset_n; 
  qsfp1_modprsl       <= QSFP1_MODPRSL_LS;
  qsfp1_intl          <= QSFP1_INTL_LS;    
-------
  QSFP2_TX1_P         <= qsfp2_tx_txp(0);                
  QSFP2_TX1_N         <= qsfp2_tx_txn(0);               
  qsfp2_rx_rxp(0)     <= QSFP2_RX1_P;                   
  qsfp2_rx_rxn(0)     <= QSFP2_RX1_N;                   

  QSFP2_TX2_P         <= qsfp2_tx_txp(1);
  QSFP2_TX2_N         <= qsfp2_tx_txn(1);
  qsfp2_rx_rxp(1)     <= QSFP2_RX2_P;
  qsfp2_rx_rxn(1)     <= QSFP2_RX2_N;

  QSFP2_TX3_P         <= qsfp2_tx_txp(2);
  QSFP2_TX3_N         <= qsfp2_tx_txn(2);
  qsfp2_rx_rxp(2)     <= QSFP2_RX3_P;
  qsfp2_rx_rxn(2)     <= QSFP2_RX3_N;

  QSFP2_TX4_P         <= qsfp2_tx_txp(3);
  QSFP2_TX4_N         <= qsfp2_tx_txn(3);
  qsfp2_rx_rxp(3)     <= QSFP2_RX4_P;
  qsfp2_rx_rxn(3)     <= QSFP2_RX4_N;

  QSFP2_RESETL_LS     <= qsfp2_reset_n; 
  qsfp2_modprsl       <= QSFP2_MODPRSL_LS;
  qsfp2_intl          <= QSFP2_INTL_LS;    
-------
  QSFP3_TX1_P         <= qsfp3_tx_txp(0);                
  QSFP3_TX1_N         <= qsfp3_tx_txn(0);               
  qsfp3_rx_rxp(0)     <= QSFP3_RX1_P;                   
  qsfp3_rx_rxn(0)     <= QSFP3_RX1_N;                   

  QSFP3_TX2_P         <= qsfp3_tx_txp(1);
  QSFP3_TX2_N         <= qsfp3_tx_txn(1);
  qsfp3_rx_rxp(1)     <= QSFP3_RX2_P;
  qsfp3_rx_rxn(1)     <= QSFP3_RX2_N;

  QSFP3_TX3_P         <= qsfp3_tx_txp(2);
  QSFP3_TX3_N         <= qsfp3_tx_txn(2);
  qsfp3_rx_rxp(2)     <= QSFP3_RX3_P;
  qsfp3_rx_rxn(2)     <= QSFP3_RX3_N;

  QSFP3_TX4_P         <= qsfp3_tx_txp(3);
  QSFP3_TX4_N         <= qsfp3_tx_txn(3);
  qsfp3_rx_rxp(3)     <= QSFP3_RX4_P;
  qsfp3_rx_rxn(3)     <= QSFP3_RX4_N;

  QSFP3_RESETL_LS     <= qsfp3_reset_n; 
  qsfp3_modprsl       <= QSFP3_MODPRSL_LS;
  qsfp3_intl          <= QSFP3_INTL_LS;    
-------
  QSFP4_TX1_P         <= qsfp4_tx_txp(0);
  QSFP4_TX1_N         <= qsfp4_tx_txn(0);
  qsfp4_rx_rxp(0)     <= QSFP4_RX1_P;
  qsfp4_rx_rxn(0)     <= QSFP4_RX1_N;

  QSFP4_TX2_P         <= qsfp4_tx_txp(1);
  QSFP4_TX2_N         <= qsfp4_tx_txn(1);
  qsfp4_rx_rxp(1)     <= QSFP4_RX2_P;
  qsfp4_rx_rxn(1)     <= QSFP4_RX2_N;

  QSFP4_TX3_P         <= qsfp4_tx_txp(2);
  QSFP4_TX3_N         <= qsfp4_tx_txn(2);
  qsfp4_rx_rxp(2)     <= QSFP4_RX3_P;
  qsfp4_rx_rxn(2)     <= QSFP4_RX3_N;

  QSFP4_TX4_P         <= qsfp4_tx_txp(3);
  QSFP4_TX4_N         <= qsfp4_tx_txn(3);
  qsfp4_rx_rxp(3)     <= QSFP4_RX4_P;
  qsfp4_rx_rxn(3)     <= QSFP4_RX4_N;
  
  QSFP4_RESETL_LS     <= qsfp4_reset_n; 
  qsfp4_modprsl       <= QSFP4_MODPRSL_LS;  
  qsfp4_intl          <= QSFP4_INTL_LS;      
    
--  i_vio_2 : entity work.vio_2_1
--    port map (
--      clk                   => clk_125_in, 
--      probe_in0(0)          => dig_iq_cmd_ready,                          -- 1    
--      probe_in1             => dig_iq_cmd_rdata,                          -- 32   
--      probe_in2             => dig_iq_interface_ready,                    -- 2 

--      probe_in3(0)          => qsfp1_modprsl,                             -- 1            
--      probe_in4(0)          => qsfp1_intl,                                -- 1 
--      probe_in5(0)          => qsfp4_modprsl,                             -- 1 
--      probe_in6(0)          => qsfp4_intl,                                -- 1 
--      probe_in7             => qsfp1_capture_tvalid_240b_cnt_in,          -- 32
--      probe_in8             => qsfp1_rx_data_ready_cnt_in,          -- 32
--      probe_in9             => qsfp1_capture_fifo_aempty_512b_cnt_in,     -- 32

--      probe_in10            => tx_tvalid_256b_cnt_in,          -- 32         
--      probe_in11            => mem_xfer_tx_upload_tvalid_256b_cnt_in,     -- 32  
--      probe_in12            => dac_tx_tvalid_256b_cnt_in,                 -- 32                              
--      probe_in13            => qsfp1_capture_rx_data_ready_in,              -- 1   

--      probe_in14            => qsfp1_capture_overflow_240b_cnt_in,        -- 32                                                
--      probe_in15            => qsfp4_playback_tvalid_256b_cnt_in,         -- 32                                                
--      probe_in16            => qsfp4_playback_tvalid_240b_cnt_in,         -- 32     
--      probe_in17            => adc_rx_tvalid_256b_cnt_in,                 -- 32   

--      probe_out0(0)         => vio_dig_iq_cmd_strb,                       -- 1                                       
--      probe_out1            => vio_dig_iq_cmd_addr,                       -- 12                             
--      probe_out2(0)         => vio_dig_iq_cmd_write,                      -- 1                              
--      probe_out3            => vio_dig_iq_cmd_sel,                        -- 3                               
--      probe_out4            => vio_dig_iq_cmd_wdata,                      -- 32      
--      probe_out5            => vio_dig_iq_mode_50g_40g_n,                 -- 1 
--      probe_out6(0)         => vio_enable,                                -- 1                                       

--      probe_out7(0)         => vio_qsfp1_reset_n,                         -- 1                                       
--      probe_out8(0)         => vio_qsfp4_reset_n,                         -- 1                                       
--      probe_out9(0)         => vio_qsfp1_aresetn,                    -- 1                                       
--      probe_out10(0)        => vio_qsfp4_aresetn,                    -- 1 
--      probe_out11(0)        => vio_cnt_reset                              -- 1       
--    );                              

--  dig_iq_cmd_strb             <= fsm_dig_iq_cmd_strb        when fsm_running = '1' else dig_iq_cmd_strb_i;
 --                                vio_dig_iq_cmd_strb        when vio_enable = '1'  else dig_iq_cmd_strb_i;         
--  dig_iq_cmd_addr             <= fsm_dig_iq_cmd_addr        when fsm_running = '1' else dig_iq_cmd_addr_i;
 --                                vio_dig_iq_cmd_addr        when vio_enable = '1'  else dig_iq_cmd_addr_i;      
--  dig_iq_cmd_write            <= fsm_dig_iq_cmd_write       when fsm_running = '1' else dig_iq_cmd_write_i;
--                                 vio_dig_iq_cmd_write       when vio_enable = '1'  else dig_iq_cmd_write_i;           
--  dig_iq_cmd_sel              <= fsm_dig_iq_cmd_sel         when fsm_running = '1' else dig_iq_cmd_sel_i;
--                                 vio_dig_iq_cmd_sel         when vio_enable = '1'  else dig_iq_cmd_sel_i;   
--  dig_iq_cmd_wdata            <= fsm_dig_iq_cmd_wdata       when fsm_running = '1' else dig_iq_cmd_wdata_i;
--                                 vio_dig_iq_cmd_wdata       when vio_enable = '1'  else dig_iq_cmd_wdata_i;      
--  dig_iq_mode_50g_40g_n       <= dig_iq_mode_50g_40g_n_i;   --vio_dig_iq_mode_50g_40g_n  when vio_enable = '1'  else dig_iq_mode_50g_40g_n_i;
    
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
  dig_iq_interface_reset(0)   <= not qsfp1_reset_n;
  dig_iq_interface_reset(1)   <= not qsfp2_reset_n;
  rx_data_ready               <= qsfp2_rx_data_ready_in & qsfp1_rx_data_ready_in; 
    
  i_qsfp_int_fsm : entity work.qsfp_init_fsm 
    port map (
      clk_125_in                      => clk_125_in,
      clk_125_aresetn_in              => clk_125_reset_n_in,

      mode_50g_40g_n_in               => dig_iq_mode_50g_40g_n,
      qsfp1_reset_n_in                => qsfp1_reset_n,
      qsfp4_reset_n_in                => qsfp2_reset_n,

      cmd_strb_out                    => fsm_dig_iq_cmd_strb,  
      cmd_addr_out                    => fsm_dig_iq_cmd_addr,  
      cmd_write_out                   => fsm_dig_iq_cmd_write, 
      cmd_sel_out                     => fsm_dig_iq_cmd_sel,   
      cmd_wdata_out                   => fsm_dig_iq_cmd_wdata, 
      cmd_ready_in                    => dig_iq_cmd_ready,
      fsm_running_out                 => fsm_running
      );

  ------------------------------------------------------    
  i_dig_iq_x2 : entity work.dig_iq_x2
    port map(
      --
      aclk_in                       =>  clk_250_in,   
      aresetn_in                    =>  clk_250_reset_n_in,
      --
      clk_125_in                    =>  clk_125_in,    
      clk_125_resetn_in             =>  clk_125_reset_n_in,       
      cmd_strb_in                   =>  fsm_dig_iq_cmd_strb,
      cmd_addr_in                   =>  fsm_dig_iq_cmd_addr,
      cmd_write_in                  =>  fsm_dig_iq_cmd_write,
      cmd_sel_in                    =>  fsm_dig_iq_cmd_sel, 
      cmd_wdata_in                  =>  fsm_dig_iq_cmd_wdata,
      cmd_ready_out                 =>  dig_iq_cmd_ready,
      cmd_rdata_out                 =>  dig_iq_cmd_rdata,
      dig_iq_interface_reset_in     =>  dig_iq_interface_reset,
      --
      dig_iq_interface_ready_out    =>  dig_iq_interface_ready,
      --
      rx_data_ready_in              =>  rx_data_ready,
      
      axis_0_aclk_out               =>  qsfp1_aclk,
      axis_0_aresetn_out            =>  qsfp1_aresetn,
      m0_axis_tdata_out             =>  qsfp1_rx_tdata_240b_out,
      m0_axis_tvalid_out            =>  qsfp1_rx_tvalid_240b,
      s0_axis_tdata_in              =>  qsfp1_tx_tdata_240b_in,
      s0_axis_tvalid_in             =>  qsfp1_tx_tvalid_240b_in,
      s0_axis_tready_out            =>  qsfp1_tx_tready_240b,
      --
      axis_1_aclk_out               =>  qsfp2_aclk,
      axis_1_aresetn_out            =>  qsfp2_aresetn,
      m1_axis_tdata_out             =>  qsfp2_rx_tdata_240b_out,
      m1_axis_tvalid_out            =>  qsfp2_rx_tvalid_240b, 
      s1_axis_tdata_in              =>  qsfp2_tx_tdata_240b_in,
      s1_axis_tvalid_in             =>  qsfp2_tx_tvalid_240b_in,
      s1_axis_tready_out            =>  qsfp2_tx_tready_240b,
      
      tx_data_channel_reset_in      =>  '0',
      tx_data_clear_in              =>  '0',     

      --
      qsfp0_ref_clk_p_in            =>  QSFP1_SI570_CLOCK_P,
      qsfp0_ref_clk_n_in            =>  QSFP1_SI570_CLOCK_N,
      qsfp0_rx_rxp_in               =>  qsfp1_rx_rxp,   
      qsfp0_rx_rxn_in               =>  qsfp1_rx_rxn,   
      qsfp0_tx_txp_out              =>  qsfp1_tx_txp,   
      qsfp0_tx_txn_out              =>  qsfp1_tx_txn,   
      --      
      qsfp1_ref_clk_p_in            =>  QSFP2_SI570_CLOCK_P,
      qsfp1_ref_clk_n_in            =>  QSFP2_SI570_CLOCK_N,
      qsfp1_rx_rxp_in               =>  qsfp2_rx_rxp,   
      qsfp1_rx_rxn_in               =>  qsfp2_rx_rxn,   
      qsfp1_tx_txp_out              =>  qsfp2_tx_txp,   
      qsfp1_tx_txn_out              =>  qsfp2_tx_txn
    );    
 
  qsfp1_aclk_out                    <= qsfp1_aclk;
  qsfp1_aresetn_out                 <= qsfp1_aresetn;
  qsfp1_rx_tvalid_240b_out          <= qsfp1_rx_tvalid_240b; 
  qsfp1_tx_tready_240b_out          <= qsfp1_tx_tready_240b;
    
  qsfp2_aclk_out                    <= qsfp2_aclk;
  qsfp2_aresetn_out                 <= qsfp2_aresetn;
  qsfp2_rx_tvalid_240b_out          <= qsfp2_rx_tvalid_240b; 
  qsfp2_tx_tready_240b_out          <= qsfp2_tx_tready_240b;
      
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
  dig_iq_interface_reset_1(0)         <= not qsfp3_reset_n;
  dig_iq_interface_reset_1(1)         <= not qsfp4_reset_n;
  rx_data_ready_1                     <= qsfp4_rx_data_ready_in & qsfp3_rx_data_ready_in; 



  i_qsfp_int_fsm_1 : entity work.qsfp_init_fsm 
    port map (
      clk_125_in                      => clk_125_in,
      clk_125_aresetn_in              => clk_125_reset_n_in,

      mode_50g_40g_n_in               => dig_iq_mode_50g_40g_n,
      qsfp1_reset_n_in                => qsfp3_reset_n,
      qsfp4_reset_n_in                => qsfp4_reset_n,

      cmd_strb_out                    => fsm_dig_iq_cmd_strb_1,  
      cmd_addr_out                    => fsm_dig_iq_cmd_addr_1,  
      cmd_write_out                   => fsm_dig_iq_cmd_write_1, 
      cmd_sel_out                     => fsm_dig_iq_cmd_sel_1,   
      cmd_wdata_out                   => fsm_dig_iq_cmd_wdata_1, 
      cmd_ready_in                    => dig_iq_cmd_ready_1,
      fsm_running_out                 => fsm_running_1
      );

  ------------------------------------------------------    
  i_dig_iq_x2_1 : entity work.dig_iq_x2
    port map(
      --
      clk_125_resetn_in             =>  clk_125_reset_n_in,       
      clk_125_in                    =>  clk_125_in,    
      --
      aclk_in                       =>  clk_250_in,   
      aresetn_in                    =>  clk_250_reset_n_in,
      cmd_strb_in                   =>  fsm_dig_iq_cmd_strb_1,
      cmd_addr_in                   =>  fsm_dig_iq_cmd_addr_1,
      cmd_write_in                  =>  fsm_dig_iq_cmd_write_1,
      cmd_sel_in                    =>  fsm_dig_iq_cmd_sel_1, 
      cmd_wdata_in                  =>  fsm_dig_iq_cmd_wdata_1,
      cmd_ready_out                 =>  dig_iq_cmd_ready_1,
      cmd_rdata_out                 =>  dig_iq_cmd_rdata_1,
      dig_iq_interface_reset_in     =>  dig_iq_interface_reset_1,
      --
      dig_iq_interface_ready_out    =>  dig_iq_interface_ready_1,
      --
      rx_data_ready_in              =>  rx_data_ready_1,
      
      axis_0_aclk_out               =>  qsfp3_aclk,
      axis_0_aresetn_out            =>  qsfp3_aresetn,
      m0_axis_tdata_out             =>  qsfp3_rx_tdata_240b_out,
      m0_axis_tvalid_out            =>  qsfp3_rx_tvalid_240b,
      s0_axis_tdata_in              =>  qsfp3_tx_tdata_240b_in,
      s0_axis_tvalid_in             =>  qsfp3_tx_tvalid_240b_in,
      s0_axis_tready_out            =>  qsfp3_tx_tready_240b,
      --
      axis_1_aclk_out               =>  qsfp4_aclk,
      axis_1_aresetn_out            =>  qsfp4_aresetn,
      m1_axis_tdata_out             =>  qsfp4_rx_tdata_240b_out,
      m1_axis_tvalid_out            =>  qsfp4_rx_tvalid_240b,
      s1_axis_tdata_in              =>  qsfp4_tx_tdata_240b_in,
      s1_axis_tvalid_in             =>  qsfp4_tx_tvalid_240b_in,
      s1_axis_tready_out            =>  qsfp4_tx_tready_240b,
      
      tx_data_channel_reset_in      =>  '0',
      tx_data_clear_in              =>  '0',     

      --
      qsfp0_ref_clk_p_in            =>  QSFP3_SI570_CLOCK_P,
      qsfp0_ref_clk_n_in            =>  QSFP3_SI570_CLOCK_N,
      qsfp0_rx_rxp_in               =>  qsfp3_rx_rxp,   
      qsfp0_rx_rxn_in               =>  qsfp3_rx_rxn,   
      qsfp0_tx_txp_out              =>  qsfp3_tx_txp,   
      qsfp0_tx_txn_out              =>  qsfp3_tx_txn,   
      --      
      qsfp1_ref_clk_p_in            =>  QSFP4_SI570_CLOCK_P,
      qsfp1_ref_clk_n_in            =>  QSFP4_SI570_CLOCK_N,
      qsfp1_rx_rxp_in               =>  qsfp4_rx_rxp,   
      qsfp1_rx_rxn_in               =>  qsfp4_rx_rxn,   
      qsfp1_tx_txp_out              =>  qsfp4_tx_txp,   
      qsfp1_tx_txn_out              =>  qsfp4_tx_txn
    );    

  qsfp3_aclk_out                  <= qsfp3_aclk;
  qsfp3_aresetn_out               <= qsfp3_aresetn;  
  qsfp3_rx_tvalid_240b_out        <= qsfp3_rx_tvalid_240b;
  qsfp3_tx_tready_240b_out        <= qsfp3_tx_tready_240b;

  qsfp4_aclk_out                  <= qsfp4_aclk;
  qsfp4_aresetn_out               <= qsfp4_aresetn;   
  qsfp4_rx_tvalid_240b_out        <= qsfp4_rx_tvalid_240b;
  qsfp4_tx_tready_240b_out        <= qsfp4_tx_tready_240b;
      
------------------------------------------------
  i_tick_gen : entity work.tick_gen
    generic map (
      CLOCK_SPEED_MHZ                       => 100
      ) 
    port map (
      clk_in                                => sys_cpu_clk_in, 

      tick_1us_out                          => open,
      tick_1ms_out                          => tick_1ms,
      tick_500ms_out                        => open,
      tick_750ms_out                        => open,
      tick_1s_out                           => open,

      prog_us_tick_rate_in                  => x"0000_0000",
      prog_us_tick_out                      => open,  

      reset_in                              => s00_axi_areset
      );

  process(sys_cpu_clk_in)  
  begin
    if (rising_edge(sys_cpu_clk_in)) then
      fpga_revision_date_r              <= FPGA_REVISION_DATE;
      minor_rev_r                       <= MINOR_REV;
    end if;
  end process;

--  i_vio_0 : entity work.vio_0_1
--    port map (
--      clk                         => sys_cpu_clk_in, 
--      probe_in0                   => fpga_revision_date_r,        -- 32
--      probe_in1                   => minor_rev_r,                 -- 8
--      probe_in2                   => clk_125_freq_r,              -- 32
--      probe_in3                   => clk_125_cnt_r,               -- 32
--      probe_in4                   => clk_250_freq_r,              -- 32         
--      probe_in5                   => clk_250_cnt_r,               -- 32
--      probe_in6                   => qsfp1_aclk_freq_r,    -- 32
--      probe_in7                   => qsfp1_aclk_cnt_r,     -- 32
--      probe_in8                   => qsfp4_aclk_freq_r,    -- 32
--      probe_in9                   => qsfp4_aclk_cnt_r,     -- 32
--      probe_in10                  => rx_device_clk_freq_r,        -- 32       
--      probe_in11                  => rx_device_clk_cnt_r,         -- 32       
--      probe_in12                  => tx_device_clk_freq_r,        -- 32
--      probe_in13                  => tx_device_clk_cnt_r,          -- 32
--      probe_in14                  => clkin8_freq_r,               -- 32
--      probe_in15                  => clkin8_cnt_r,                -- 32
--      probe_in16                  => sys_cpu_clk_freq_r,               -- 32
--      probe_in17                  => sys_cpu_clk_cnt_r,                -- 32
--      probe_in18                  => ref_clk_div2_freq_r,         -- 32
--      probe_in19                  => ref_clk_div2_cnt_r,           -- 32
--      probe_in20                  => qsfp2_aclk_freq_r,         -- 32
--      probe_in21                  => qsfp2_aclk_cnt_r,           -- 32
--      probe_in22                  => qsfp3_aclk_freq_r,         -- 32
--      probe_in23                  => qsfp3_aclk_cnt_r          -- 32
--    );
      
  process(clk_125_in)
  begin
    if (rising_edge(clk_125_in)) then
      clk_125_tick_1ms_r      <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
      if (clk_125_tick_1ms_r(0 to 1) = "01") then 
        clk_125_freq_r        <= clk_125_cnt_r;
        clk_125_cnt_r         <= (others => '0');
      else
        clk_125_cnt_r         <= clk_125_cnt_r + 1;
      end if;
    end if;
  end process;

  process(clk_250_in)
  begin
    if (rising_edge(clk_250_in)) then
      clk_250_tick_1ms_r      <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
      if (clk_250_tick_1ms_r(0 to 1) = "01") then 
        clk_250_freq_r        <= clk_250_cnt_r;
        clk_250_cnt_r         <= (others => '0');
      else
        clk_250_cnt_r         <= clk_250_cnt_r + 1;
      end if;
    end if;
  end process;

  process(qsfp1_aclk)
  begin
    if (rising_edge(qsfp1_aclk)) then
      qsfp1_aclk_tick_1ms_r      <= qsfp1_aclk_tick_1ms_r(1 to 2) & tick_1ms;
      if (qsfp1_aclk_tick_1ms_r(0 to 1) = "01") then 
        qsfp1_aclk_freq_r        <= qsfp1_aclk_cnt_r;
        qsfp1_aclk_cnt_r         <= (others => '0');
      else
        qsfp1_aclk_cnt_r         <= qsfp1_aclk_cnt_r + 1;
      end if;
    end if;
  end process;

  process(qsfp2_aclk)
  begin
    if (rising_edge(qsfp2_aclk)) then
      qsfp2_aclk_tick_1ms_r      <= qsfp2_aclk_tick_1ms_r(1 to 2) & tick_1ms;
      if (qsfp2_aclk_tick_1ms_r(0 to 1) = "01") then 
        qsfp2_aclk_freq_r        <= qsfp2_aclk_cnt_r;
        qsfp2_aclk_cnt_r         <= (others => '0');
      else
        qsfp2_aclk_cnt_r         <= qsfp2_aclk_cnt_r + 1;
      end if;
    end if;
  end process;
  
  process(qsfp3_aclk)
  begin
    if (rising_edge(qsfp3_aclk)) then
      qsfp3_aclk_tick_1ms_r      <= qsfp3_aclk_tick_1ms_r(1 to 2) & tick_1ms;
      if (qsfp3_aclk_tick_1ms_r(0 to 1) = "01") then 
        qsfp3_aclk_freq_r        <= qsfp3_aclk_cnt_r;
        qsfp3_aclk_cnt_r         <= (others => '0');
      else
        qsfp3_aclk_cnt_r         <= qsfp3_aclk_cnt_r + 1;
      end if;
    end if;
  end process;

  process(qsfp4_aclk)
  begin
    if (rising_edge(qsfp4_aclk)) then
      qsfp4_aclk_tick_1ms_r      <= qsfp4_aclk_tick_1ms_r(1 to 2) & tick_1ms;
      if (qsfp4_aclk_tick_1ms_r(0 to 1) = "01") then 
        qsfp4_aclk_freq_r        <= qsfp4_aclk_cnt_r;
        qsfp4_aclk_cnt_r         <= (others => '0');
      else
        qsfp4_aclk_cnt_r         <= qsfp4_aclk_cnt_r + 1;
      end if;
    end if;
  end process;

  process(rx_device_clk_in)
  begin
    if (rising_edge(rx_device_clk_in)) then
      rx_device_clk_tick_1ms_r      <= rx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
      if (rx_device_clk_tick_1ms_r(0 to 1) = "01") then 
        rx_device_clk_freq_r        <= rx_device_clk_cnt_r;
        rx_device_clk_cnt_r         <= (others => '0');
      else
        rx_device_clk_cnt_r         <= rx_device_clk_cnt_r + 1;
      end if;
    end if;
  end process;

  process(tx_device_clk_in)
  begin
    if (rising_edge(tx_device_clk_in)) then
      tx_device_clk_tick_1ms_r      <= tx_device_clk_tick_1ms_r(1 to 2) & tick_1ms;
      if (tx_device_clk_tick_1ms_r(0 to 1) = "01") then 
        tx_device_clk_freq_r        <= tx_device_clk_cnt_r;
        tx_device_clk_cnt_r         <= (others => '0');
      else
        tx_device_clk_cnt_r         <= tx_device_clk_cnt_r + 1;
      end if;
    end if;
  end process;
      
  process(clkin8_in)
  begin
    if (rising_edge(clkin8_in)) then
      clkin8_tick_1ms_r      <= clkin8_tick_1ms_r(1 to 2) & tick_1ms;
      if (clkin8_tick_1ms_r(0 to 1) = "01") then 
        clkin8_freq_r        <= clkin8_cnt_r;
        clkin8_cnt_r         <= (others => '0');
      else
        clkin8_cnt_r         <= clkin8_cnt_r + 1;
      end if;
    end if;
  end process;
  
  process(sys_cpu_clk_in)
  begin
    if (rising_edge(sys_cpu_clk_in)) then
      sys_cpu_clk_tick_1ms_r      <= sys_cpu_clk_tick_1ms_r(1 to 2) & tick_1ms;
      if (sys_cpu_clk_tick_1ms_r(0 to 1) = "01") then 
        sys_cpu_clk_freq_r        <= sys_cpu_clk_cnt_r;
        sys_cpu_clk_cnt_r         <= (others => '0');
      else
        sys_cpu_clk_cnt_r         <= sys_cpu_clk_cnt_r + 1;
      end if;
    end if;
  end process;
  
  process(ref_clk_div2_in)
  begin
    if (rising_edge(ref_clk_div2_in)) then
      ref_clk_div2_tick_1ms_r      <= ref_clk_div2_tick_1ms_r(1 to 2) & tick_1ms;
      if (ref_clk_div2_tick_1ms_r(0 to 1) = "01") then 
        ref_clk_div2_freq_r        <= ref_clk_div2_cnt_r;
        ref_clk_div2_cnt_r         <= (others => '0');
      else
        ref_clk_div2_cnt_r         <= ref_clk_div2_cnt_r + 1;
      end if;
    end if;
  end process;
  
  -- User logic ends

end arch_imp;
