###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

#
## mxfe
#

set_property         -dict {PACKAGE_PIN AR24   IOSTANDARD LVCMOS18                                     } [get_ports agc0[0]          ]    ; ## IO_L14P_T2L_N2_GC_65   	        FMC2_LA17_CC_P       	D20
set_property         -dict {PACKAGE_PIN AR25   IOSTANDARD LVCMOS18                                     } [get_ports agc0[1]          ]    ; ## IO_L14N_T2L_N3_GC_65		FMC2_LA17_CC_N       	D21
set_property         -dict {PACKAGE_PIN AU25   IOSTANDARD LVCMOS18                                     } [get_ports agc1[0]          ]    ; ## IO_L11P_T1U_N8_GC_65	        FMC2_LA18_CC_P       	C22
set_property         -dict {PACKAGE_PIN AU26   IOSTANDARD LVCMOS18                                     } [get_ports agc1[1]          ]    ; ## IO_L11N_T1U_N9_GC_65	        FMC2_LA18_CC_N       	C23
set_property         -dict {PACKAGE_PIN AU28   IOSTANDARD LVCMOS18                                     } [get_ports agc2[0]          ]    ; ## IO_L10P_T1U_N6_QBC_AD4P_65	FMC2_LA20_P          	G21
set_property         -dict {PACKAGE_PIN AV28   IOSTANDARD LVCMOS18                                     } [get_ports agc2[1]          ]    ; ## IO_L10N_T1U_N7_QBC_AD4N_65	FMC2_LA20_N          	G22
set_property         -dict {PACKAGE_PIN BB24   IOSTANDARD LVCMOS18                                     } [get_ports agc3[0]          ]    ; ## IO_L2P_T0L_N2_65			FMC2_LA21_P          	H25
set_property         -dict {PACKAGE_PIN BB25   IOSTANDARD LVCMOS18                                     } [get_ports agc3[1]          ]    ; ## IO_L2N_T0L_N3_65			FMC2_LA21_N          	H26
set_property         -dict {PACKAGE_PIN AT27   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE    } [get_ports clkin6_n         ]    ; ## IO_L13N_T2L_N1_GC_QBC_65		FMC2_CLK1_M2C_N      	G3
set_property         -dict {PACKAGE_PIN AR27   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE    } [get_ports clkin6_p         ]    ; ## IO_L13P_T2L_N0_GC_QBC_65		FMC2_CLK1_M2C_P      	G2
set_property         -dict {PACKAGE_PIN AK11      } [get_ports clkin8_n        ]    							  ; ## MGTREFCLK0N_224 			FMC2_GBTCLK1_M2C_N   	B21
set_property         -dict {PACKAGE_PIN AK12      } [get_ports clkin8_p        ]    							  ; ## MGTREFCLK0P_224 			FMC2_GBTCLK1_M2C_P   	B20

set_property         -dict {PACKAGE_PIN AV21   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE    } [get_ports clkin10_n         ]    ; ## IO_L11N_T1U_N9_GC_64		LA00_N_CC      	G7
set_property         -dict {PACKAGE_PIN AU21   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE    } [get_ports clkin10_p         ]    ; ## IO_L11P_T1U_N8_GC_64		LA00_P_CC      	G6


set_property         -dict {PACKAGE_PIN AH11                                                           } [get_ports fpga_refclk_in_n ]   ; ## MGTREFCLK0N_225			FMC2_GBTCLK0_M2C_C_N 	D5
set_property         -dict {PACKAGE_PIN AH12                                                           } [get_ports fpga_refclk_in_p ]   ; ## MGTREFCLK0P_225			FMC2_GBTCLK0_M2C_C_P 	D4
set_property  -quiet -dict {PACKAGE_PIN AP3                                                           } [get_ports rx_data_n[2]     ]    ; ## MGTHRXN2_225    FPGA_SERDIN_0_N	FMC2_DP2_M2C_n       	A7
set_property  -quiet -dict {PACKAGE_PIN AP4                                                           } [get_ports rx_data_p[2]     ]    ; ## MGTHRXP2_225    FPGA_SERDIN_0_P	FMC2_DP2_M2C_P       	A6
set_property  -quiet -dict {PACKAGE_PIN AR1                                                           } [get_ports rx_data_n[0]     ]    ; ## MGTHRXN1_225    FPGA_SERDIN_1_N	FMC2_DP0_M2C_n       	C7
set_property  -quiet -dict {PACKAGE_PIN AR2                                                           } [get_ports rx_data_p[0]     ]    ; ## MGTHRXP1_225    FPGA_SERDIN_1_P	FMC2_DP0_M2C_P       	C6
set_property  -quiet -dict {PACKAGE_PIN AU1                                                           } [get_ports rx_data_n[7]     ]    ; ## MGTHRXN3_224    FPGA_SERDIN_2_N	FMC2_DP7_M2C_N       	B13
set_property  -quiet -dict {PACKAGE_PIN AU2                                                           } [get_ports rx_data_p[7]     ]    ; ## MGTHRXP3_224    FPGA_SERDIN_2_P	FMC2_DP7_M2C_P       	B12
set_property  -quiet -dict {PACKAGE_PIN AW1                                                           } [get_ports rx_data_n[6]     ]    ; ## MGTHRXN1_224    FPGA_SERDIN_3_N	FMC2_DP6_M2C_N       	B17
set_property  -quiet -dict {PACKAGE_PIN AW2                                                           } [get_ports rx_data_p[6]     ]    ; ## MGTHRXP1_224    FPGA_SERDIN_3_P	FMC2_DP6_M2C_P       	B16
set_property  -quiet -dict {PACKAGE_PIN BA1                                                           } [get_ports rx_data_n[5]     ]    ; ## MGTHRXN0_224    FPGA_SERDIN_4_N	FMC2_DP5_M2C_N       	A19
set_property  -quiet -dict {PACKAGE_PIN BA2                                                           } [get_ports rx_data_p[5]     ]    ; ## MGTHRXP0_224    FPGA_SERDIN_4_P	FMC2_DP5_M2C_P       	A18
set_property  -quiet -dict {PACKAGE_PIN AV3                                                           } [get_ports rx_data_n[4]     ]    ; ## MGTHRXN2_224    FPGA_SERDIN_5_N	FMC2_DP4_M2C_N       	A15
set_property  -quiet -dict {PACKAGE_PIN AV4                                                           } [get_ports rx_data_p[4]     ]    ; ## MGTHRXP2_224    FPGA_SERDIN_5_P	FMC2_DP4_M2C_P       	A14
set_property  -quiet -dict {PACKAGE_PIN AT3                                                           } [get_ports rx_data_n[3]     ]    ; ## MGTHRXN0_225    FPGA_SERDIN_6_N	FMC2_DP3_M2C_n       	A11
set_property  -quiet -dict {PACKAGE_PIN AT4                                                           } [get_ports rx_data_p[3]     ]    ; ## MGTHRXP0_225    FPGA_SERDIN_6_P	FMC2_DP3_M2C_P       	A10
set_property  -quiet -dict {PACKAGE_PIN AN1                                                           } [get_ports rx_data_n[1]     ]    ; ## MGTHRXN3_225    FPGA_SERDIN_7_N	FMC2_DP1_M2C_n       	A3
set_property  -quiet -dict {PACKAGE_PIN AN2                                                           } [get_ports rx_data_p[1]     ]    ; ## MGTHRXP3_225    FPGA_SERDIN_7_P	FMC2_DP1_M2C_P       	A2
set_property  -quiet -dict {PACKAGE_PIN AP7                                                           } [get_ports tx_data_n[0]     ]    ; ## MGTHTXN1_225    FPGA_SERDOUT_0_N	FMC2_DP0_C2M_n       	C3
set_property  -quiet -dict {PACKAGE_PIN AP8                                                           } [get_ports tx_data_p[0]     ]    ; ## MGTHTXP1_225    FPGA_SERDOUT_0_P	FMC2_DP0_C2M_P       	C2
set_property  -quiet -dict {PACKAGE_PIN AN5                                                           } [get_ports tx_data_n[2]     ]    ; ## MGTHTXN2_225    FPGA_SERDOUT_1_N	FMC2_DP2_C2M_n       	A27
set_property  -quiet -dict {PACKAGE_PIN AN6                                                           } [get_ports tx_data_p[2]     ]    ; ## MGTHTXP2_225    FPGA_SERDOUT_1_P	FMC2_DP2_C2M_P       	A26
set_property  -quiet -dict {PACKAGE_PIN AT7                                                           } [get_ports tx_data_n[7]     ]    ; ## MGTHTXN3_224    FPGA_SERDOUT_2_N	FMC2_DP7_C2M_N       	B33
set_property  -quiet -dict {PACKAGE_PIN AT8                                                           } [get_ports tx_data_p[7]     ]    ; ## MGTHTXP3_224    FPGA_SERDOUT_2_P	FMC2_DP7_C2M_P       	B32
set_property  -quiet -dict {PACKAGE_PIN AW5                                                           } [get_ports tx_data_n[6]     ]    ; ## MGTHTXN1_224    FPGA_SERDOUT_3_N	FMC2_DP6_C2M_N       	B37
set_property  -quiet -dict {PACKAGE_PIN AW6                                                           } [get_ports tx_data_p[6]     ]    ; ## MGTHTXP1_224    FPGA_SERDOUT_3_P	FMC2_DP6_C2M_P       	B36
set_property  -quiet -dict {PACKAGE_PIN AM7                                                           } [get_ports tx_data_n[1]     ]    ; ## MGTHTXN3_225    FPGA_SERDOUT_4_N	FMC2_DP1_C2M_n       	A23
set_property  -quiet -dict {PACKAGE_PIN AM8                                                           } [get_ports tx_data_p[1]     ]    ; ## MGTHTXP3_225    FPGA_SERDOUT_4_P	FMC2_DP1_C2M_P       	A22
set_property  -quiet -dict {PACKAGE_PIN AY3                                                           } [get_ports tx_data_n[5]     ]    ; ## MGTHTXN0_224    FPGA_SERDOUT_5_N	FMC2_DP5_C2M_N       	A39
set_property  -quiet -dict {PACKAGE_PIN AY4                                                           } [get_ports tx_data_p[5]     ]    ; ## MGTHTXP0_224    FPGA_SERDOUT_5_P	FMC2_DP5_C2M_P       	A38
set_property  -quiet -dict {PACKAGE_PIN AU5                                                           } [get_ports tx_data_n[4]     ]    ; ## MGTHTXN2_224    FPGA_SERDOUT_6_N	FMC2_DP4_C2M_N       	A35
set_property  -quiet -dict {PACKAGE_PIN AU6                                                           } [get_ports tx_data_p[4]     ]    ; ## MGTHTXP2_224    FPGA_SERDOUT_6_P	FMC2_DP4_C2M_P       	A34
set_property  -quiet -dict {PACKAGE_PIN AR5                                                           } [get_ports tx_data_n[3]     ]    ; ## MGTHTXN0_225    FPGA_SERDOUT_7_N	FMC2_DP3_C2M_n       	A31
set_property  -quiet -dict {PACKAGE_PIN AR6                                                           } [get_ports tx_data_p[3]     ]    ; ## MGTHTXP0_225    FPGA_SERDOUT_7_P	FMC2_DP3_C2M_P       	A30
set_property  -quiet -dict {PACKAGE_PIN AV23   IOSTANDARD LVDS     DIFF_TERM_ADV TERM_100              } [get_ports fpga_syncin_0_n  ]    ; ## IO_L7N_T1L_N1_QBC_AD13N_64	FMC2_LA02_n          	H8
set_property  -quiet -dict {PACKAGE_PIN AU23   IOSTANDARD LVDS     DIFF_TERM_ADV TERM_100              } [get_ports fpga_syncin_0_p  ]    ; ## IO_L7P_T1L_N0_QBC_AD13P_64	FMC2_LA02_P          	H7
set_property  -quiet -dict {PACKAGE_PIN AW19   IOSTANDARD LVCMOS18                                     } [get_ports fpga_syncin_1_n  ]    ; ## IO_L9N_T1L_N5_AD12N_64		FMC2_LA03_n          	G10
set_property  -quiet -dict {PACKAGE_PIN AW20   IOSTANDARD LVCMOS18                                     } [get_ports fpga_syncin_1_p  ]    ; ## IO_L9P_T1L_N4_AD12P_64		FMC2_LA03_P          	G9
set_property  -quiet -dict {PACKAGE_PIN AV19   IOSTANDARD LVDS                                         } [get_ports fpga_syncout_0_n ]    ; ## IO_L12N_T1U_N11_GC_64		FMC2_LA01_CC_n       	D9
set_property  -quiet -dict {PACKAGE_PIN AU20   IOSTANDARD LVDS                                         } [get_ports fpga_syncout_0_p ]    ; ## IO_L12P_T1U_N10_GC_64		FMC2_LA01_CC_P       	D8
set_property  -quiet -dict {PACKAGE_PIN AY22   IOSTANDARD LVCMOS18                                     } [get_ports fpga_syncout_1_n ]    ; ## IO_L2N_T0L_N3_64			FMC2_LA06_n          	C11
set_property  -quiet -dict {PACKAGE_PIN AY23   IOSTANDARD LVCMOS18                                     } [get_ports fpga_syncout_1_p ]    ; ## IO_L2P_T0L_N2_64			FMC2_LA06_P          	C10
set_property         -dict {PACKAGE_PIN AM21   IOSTANDARD LVCMOS18                                     } [get_ports gpio[0]          ]    ; ## IO_L20P_T3L_N2_AD1P_64		FMC2_LA15_P          	H19
set_property         -dict {PACKAGE_PIN AM20   IOSTANDARD LVCMOS18                                     } [get_ports gpio[1]          ]    ; ## IO_L20N_T3L_N3_AD1N_64		FMC2_LA15_N          	H20
set_property         -dict {PACKAGE_PIN AV27   IOSTANDARD LVCMOS18                                     } [get_ports gpio[2]          ]    ; ## IO_L9P_T1L_N4_AD12P_65		FMC2_LA19_P          	H22
set_property         -dict {PACKAGE_PIN AW27   IOSTANDARD LVCMOS18                                     } [get_ports gpio[3]          ]    ; ## IO_L9N_T1L_N5_AD12N_65		FMC2_LA19_N          	H23
set_property         -dict {PACKAGE_PIN AJ21   IOSTANDARD LVCMOS18                                     } [get_ports gpio[4]          ]    ; ## IO_L23P_T3U_N8_64		FMC2_LA13_P          	D17
set_property         -dict {PACKAGE_PIN AJ20   IOSTANDARD LVCMOS18                                     } [get_ports gpio[5]          ]    ; ## IO_L23N_T3U_N9_64		FMC2_LA13_N          	D18
set_property         -dict {PACKAGE_PIN AM19   IOSTANDARD LVCMOS18                                     } [get_ports gpio[6]          ]    ; ## IO_L19P_T3L_N0_DBC_AD9P_64	FMC2_LA14_P          	C18
set_property         -dict {PACKAGE_PIN AN19   IOSTANDARD LVCMOS18                                     } [get_ports gpio[7]          ]    ; ## IO_L19N_T3L_N1_DBC_AD9N_64	FMC2_LA14_N          	C19
set_property         -dict {PACKAGE_PIN AL22   IOSTANDARD LVCMOS18                                     } [get_ports gpio[8]          ]    ; ## IO_L21P_T3L_N4_AD8P_64		FMC2_LA16_P          	G18
set_property         -dict {PACKAGE_PIN AL21   IOSTANDARD LVCMOS18                                     } [get_ports gpio[9]          ]    ; ## IO_L21N_T3L_N5_AD8N_64		FMC2_LA16_N          	G19
set_property         -dict {PACKAGE_PIN BB26   IOSTANDARD LVCMOS18                                     } [get_ports gpio[10]         ]    ; ## IO_L4N_T0U_N7_DBC_AD7N_65	FMC2_LA22_N          	G25
set_property         -dict {PACKAGE_PIN AK19   IOSTANDARD LVCMOS18                                     } [get_ports hmc_gpio1        ]    ; ## IO_L22N_T3U_N7_DBC_AD0N_64	FMC2_LA11_N          	H17
set_property         -dict {PACKAGE_PIN BA21   IOSTANDARD LVCMOS18                                     } [get_ports hmc_sync         ]    ; ## IO_L3N_T0L_N5_AD15N_64		FMC2_LA07_N          	H14
set_property         -dict {PACKAGE_PIN BB20   IOSTANDARD LVCMOS18                                     } [get_ports irqb[0]          ]    ; ## IO_L5P_T0U_N8_AD14P_64		FMC2_LA08_P          	G12
set_property         -dict {PACKAGE_PIN BB19   IOSTANDARD LVCMOS18                                     } [get_ports irqb[1]          ]    ; ## IO_L5N_T0U_N9_AD14N_64		FMC2_LA08_N          	G13
set_property         -dict {PACKAGE_PIN BA22   IOSTANDARD LVCMOS18                                     } [get_ports rstb             ]    ; ## IO_L3P_T0L_N4_AD15P_64		FMC2_LA07_P          	H13
set_property         -dict {PACKAGE_PIN BA18   IOSTANDARD LVCMOS18                                     } [get_ports rxen[0]          ]    ; ## IO_L6P_T0U_N10_AD6P_64		FMC2_LA10_P          	C14
set_property         -dict {PACKAGE_PIN BB18   IOSTANDARD LVCMOS18                                     } [get_ports rxen[1]          ]    ; ## IO_L6N_T0U_N11_AD6N_64		FMC2_LA10_N          	C15
set_property         -dict {PACKAGE_PIN AY19   IOSTANDARD LVCMOS18                                     } [get_ports spi0_csb         ]    ; ## IO_L10P_T1U_N6_QBC_AD4P_64	FMC2_LA05_P          	D11
set_property         -dict {PACKAGE_PIN AY18   IOSTANDARD LVCMOS18                                     } [get_ports spi0_miso        ]    ; ## IO_L10N_T1U_N7_QBC_AD4N_64	FMC2_LA05_N          	D12
set_property         -dict {PACKAGE_PIN AN21   IOSTANDARD LVCMOS18                                     } [get_ports spi0_mosi        ]    ; ## IO_L16P_T2U_N6_QBC_AD3P_64	FMC2_LA04_P          	H10
set_property         -dict {PACKAGE_PIN AP21   IOSTANDARD LVCMOS18                                     } [get_ports spi0_sclk        ]    ; ## IO_L16N_T2U_N7_QBC_AD3N_64	FMC2_LA04_N          	H11
set_property         -dict {PACKAGE_PIN BA23   IOSTANDARD LVCMOS18                                     } [get_ports spi1_csb         ]    ; ## IO_L1P_T0L_N0_DBC_64		FMC2_LA12_P          	G15
set_property         -dict {PACKAGE_PIN AK20   IOSTANDARD LVCMOS18                                     } [get_ports spi1_sclk        ]    ; ## IO_L22P_T3U_N6_DBC_AD0P_64	FMC2_LA11_P          	H16
set_property         -dict {PACKAGE_PIN BB23   IOSTANDARD LVCMOS18                                     } [get_ports spi1_sdio        ]    ; ## IO_L1N_T0L_N1_DBC_64		FMC2_LA12_N          	G16
set_property         -dict {PACKAGE_PIN AT21   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE    } [get_ports sysref2_n        ]    ; ## IO_L13N_T2L_N1_GC_QBC_64		FMC2_CLK0_M2C_n      	H5
set_property         -dict {PACKAGE_PIN AT22   IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE    } [get_ports sysref2_p        ]    ; ## IO_L13P_T2L_N0_GC_QBC_64		FMC2_CLK0_M2C_P      	H4
set_property         -dict {PACKAGE_PIN AY20   IOSTANDARD LVCMOS18                                     } [get_ports txen[0]          ]    ; ## IO_L4P_T0U_N6_DBC_AD7P_64	FMC2_LA09_P          	D14
set_property         -dict {PACKAGE_PIN BA20   IOSTANDARD LVCMOS18                                     } [get_ports txen[1]          ]    ; ## IO_L4N_T0U_N7_DBC_AD7N_64	FMC2_LA09_N          	D15

set_property         -dict {PACKAGE_PIN A9     IOSTANDARD LVCMOS33                                     } [get_ports pll_scl          ]    ; ## IO_L12N_AD8N_91
set_property         -dict {PACKAGE_PIN A10    IOSTANDARD LVCMOS33                                     } [get_ports pll_sda          ]    ; ## IO_L12N_AD8P_91

