-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
-- Date        : Fri Sep 19 16:06:04 2025
-- Host        : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
-- Command     : write_vhdl -force -mode synth_stub -rename_top axis_mux_256b -prefix
--               axis_mux_256b_ axis_mux_256b_stub.vhdl
-- Design      : axis_mux_256b
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xczu19eg-ffvc1760-2-i
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity axis_mux_256b is
  Port ( 
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    aselect : in STD_LOGIC;
    s0_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
    s0_axis_tvalid : in STD_LOGIC;
    s0_axis_tready : out STD_LOGIC;
    s1_axis_tdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
    s1_axis_tvalid : in STD_LOGIC;
    s1_axis_tready : out STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC
  );

end axis_mux_256b;

architecture stub of axis_mux_256b is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,aselect,s0_axis_tdata[255:0],s0_axis_tvalid,s0_axis_tready,s1_axis_tdata[255:0],s1_axis_tvalid,s1_axis_tready,m_axis_tdata[255:0],m_axis_tvalid,m_axis_tready";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axis_mux,Vivado 2023.2";
begin
end;
