// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
// Date        : Fri Sep 19 16:06:04 2025
// Host        : nicksbaby running 64-bit Ubuntu 22.04.5 LTS
// Command     : write_verilog -force -mode synth_stub -rename_top axis_mux_256b -prefix
//               axis_mux_256b_ axis_mux_256b_stub.v
// Design      : axis_mux_256b
// Purpose     : Stub declaration of top-level module interface
// Device      : xczu19eg-ffvc1760-2-i
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axis_mux,Vivado 2023.2" *)
module axis_mux_256b(aclk, aresetn, aselect, s0_axis_tdata, 
  s0_axis_tvalid, s0_axis_tready, s1_axis_tdata, s1_axis_tvalid, s1_axis_tready, 
  m_axis_tdata, m_axis_tvalid, m_axis_tready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,aselect,s0_axis_tdata[255:0],s0_axis_tvalid,s0_axis_tready,s1_axis_tdata[255:0],s1_axis_tvalid,s1_axis_tready,m_axis_tdata[255:0],m_axis_tvalid,m_axis_tready" */;
  input aclk;
  input aresetn;
  input aselect;
  input [255:0]s0_axis_tdata;
  input s0_axis_tvalid;
  output s0_axis_tready;
  input [255:0]s1_axis_tdata;
  input s1_axis_tvalid;
  output s1_axis_tready;
  output [255:0]m_axis_tdata;
  output m_axis_tvalid;
  input m_axis_tready;
endmodule
