#####################################
#
#  VCU128 Rev1.0 XDC
#  Date: 01/24/2018
#
####################################
###################################


create_clock -period 6.40 -name QSFP1_SI570_CLOCK_P [get_ports QSFP1_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz
create_clock -period 6.40 -name QSFP2_SI570_CLOCK_P [get_ports QSFP2_SI570_CLOCK_P]
create_clock -period 6.40 -name QSFP3_SI570_CLOCK_P [get_ports QSFP3_SI570_CLOCK_P]
create_clock -period 6.40 -name QSFP4_SI570_CLOCK_P [get_ports QSFP4_SI570_CLOCK_P]; # actual clk freq is 156.25 MHz


### J79
set_property PACKAGE_PIN L33     [get_ports "QSFP4_SI570_CLOCK_N"] ;# Bank 131 - MGTREFCLK0N_131      CLK0_N	     
set_property PACKAGE_PIN L32     [get_ports "QSFP4_SI570_CLOCK_P"] ;# Bank 131 - MGTREFCLK0P_131      CLK0_P
set_property PACKAGE_PIN G42     [get_ports "QSFP4_RX1_N"] ;# Bank 131 - MGTYRXN0_131
set_property PACKAGE_PIN G41     [get_ports "QSFP4_RX1_P"] ;# Bank 131 - MGTYRXP0_131
set_property PACKAGE_PIN F40      [get_ports "QSFP4_RX2_N"] ;# Bank 131 - MGTYRXN1_131
set_property PACKAGE_PIN F39      [get_ports "QSFP4_RX2_P"] ;# Bank 131 - MGTYRXP1_131
set_property PACKAGE_PIN E42      [get_ports "QSFP4_RX3_N"] ;# Bank 131 - MGTYRXN2_131
set_property PACKAGE_PIN E41      [get_ports "QSFP4_RX3_P"] ;# Bank 131 - MGTYRXP2_131
set_property PACKAGE_PIN D40      [get_ports "QSFP4_RX4_N"] ;# Bank 131 - MGTYRXN3_131
set_property PACKAGE_PIN D39      [get_ports "QSFP4_RX4_P"] ;# Bank 131 - MGTYRXP3_131

set_property PACKAGE_PIN H35     [get_ports "QSFP4_TX1_N"] ;# Bank 131 - MGTYTXN0_131
set_property PACKAGE_PIN H34     [get_ports "QSFP4_TX1_P"] ;# Bank 131 - MGTYTXP0_131
set_property PACKAGE_PIN G37      [get_ports "QSFP4_TX2_N"] ;# Bank 131 - MGTYTXN1_131
set_property PACKAGE_PIN G36      [get_ports "QSFP4_TX2_P"] ;# Bank 131 - MGTYTXP1_131
set_property PACKAGE_PIN F35      [get_ports "QSFP4_TX3_N"] ;# Bank 131 - MGTYTXN2_131
set_property PACKAGE_PIN F34      [get_ports "QSFP4_TX3_P"] ;# Bank 131 - MGTYTXP2_131
set_property PACKAGE_PIN E37      [get_ports "QSFP4_TX4_N"] ;# Bank 131 - MGTYTXN3_131
set_property PACKAGE_PIN E36      [get_ports "QSFP4_TX4_P"] ;# Bank 131 - MGTYTXP3_131

set_property -dict {PACKAGE_PIN E3  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP4_INTL_LS"]    ;# 
set_property -dict {PACKAGE_PIN F4  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP4_RESETL_LS"]  ;# 
set_property -dict {PACKAGE_PIN E2  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP4_MODPRSL_LS"] ;# 

### J78
set_property PACKAGE_PIN R33      [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 130 - MGTREFCLK0N_130   CLK1_N
set_property PACKAGE_PIN R32      [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 130 - MGTREFCLK0P_130   CLK1_P
# set_property PACKAGE_PIN W41      [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 130 - MGTREFCLK1N_130
# set_property PACKAGE_PIN W40      [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 130 - MGTREFCLK1P_130
 set_property PACKAGE_PIN L42      [get_ports "QSFP3_RX1_N"] ;# Bank 130 - MGTYRXN0_130
 set_property PACKAGE_PIN L41      [get_ports "QSFP3_RX1_P"] ;# Bank 130 - MGTYRXP0_130
 set_property PACKAGE_PIN K40      [get_ports "QSFP3_RX2_N"] ;# Bank 130 - MGTYRXN1_130
 set_property PACKAGE_PIN K39      [get_ports "QSFP3_RX2_P"] ;# Bank 130 - MGTYRXP1_130
 set_property PACKAGE_PIN J42      [get_ports "QSFP3_RX3_N"] ;# Bank 130 - MGTYRXN2_130
 set_property PACKAGE_PIN J41      [get_ports "QSFP3_RX3_P"] ;# Bank 130 - MGTYRXP2_130
 set_property PACKAGE_PIN H40      [get_ports "QSFP3_RX4_N"] ;# Bank 130 - MGTYRXN3_130
 set_property PACKAGE_PIN H39      [get_ports "QSFP3_RX4_P"] ;# Bank 130 - MGTYRXP3_130

 set_property PACKAGE_PIN M35      [get_ports "QSFP3_TX1_N"] ;# Bank 130 - MGTYTXN0_130
 set_property PACKAGE_PIN M34      [get_ports "QSFP3_TX1_P"] ;# Bank 130 - MGTYTXP0_130
 set_property PACKAGE_PIN L37      [get_ports "QSFP3_TX2_N"] ;# Bank 130 - MGTYTXN1_130
 set_property PACKAGE_PIN L36      [get_ports "QSFP3_TX2_P"] ;# Bank 130 - MGTYTXP1_130
 set_property PACKAGE_PIN K35      [get_ports "QSFP3_TX3_N"] ;# Bank 130 - MGTYTXN2_130
 set_property PACKAGE_PIN K34      [get_ports "QSFP3_TX3_P"] ;# Bank 130 - MGTYTXP2_130
 set_property PACKAGE_PIN J37      [get_ports "QSFP3_TX4_N"] ;# Bank 130 - MGTYTXN3_130
 set_property PACKAGE_PIN J36      [get_ports "QSFP3_TX4_P"] ;# Bank 130 - MGTYTXP3_130

set_property -dict {PACKAGE_PIN E7  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP3_INTL_LS"]    ;# 
set_property -dict {PACKAGE_PIN A8  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP3_RESETL_LS"]  ;# 
set_property -dict {PACKAGE_PIN A7  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP3_MODPRSL_LS"] ;# 

### J77
set_property PACKAGE_PIN W33      [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 129 - MGTREFCLK0N_129   CLK3_N
set_property PACKAGE_PIN W32      [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 129 - MGTREFCLK0P_129   CLK3_P
# set_property PACKAGE_PIN R41      [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 129 - MGTREFCLK1N_129
# set_property PACKAGE_PIN R40      [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 129 - MGTREFCLK1P_129
 set_property PACKAGE_PIN R42      [get_ports "QSFP2_RX1_N"] ;# Bank 129 - MGTYRXN0_129
 set_property PACKAGE_PIN R41      [get_ports "QSFP2_RX1_P"] ;# Bank 129 - MGTYRXP0_129
 set_property PACKAGE_PIN P40      [get_ports "QSFP2_RX2_N"] ;# Bank 129 - MGTYRXN1_129
 set_property PACKAGE_PIN P39      [get_ports "QSFP2_RX2_P"] ;# Bank 129 - MGTYRXP1_129
 set_property PACKAGE_PIN N42      [get_ports "QSFP2_RX3_N"] ;# Bank 129 - MGTYRXN2_129
 set_property PACKAGE_PIN N41      [get_ports "QSFP2_RX3_P"] ;# Bank 129 - MGTYRXP2_129
 set_property PACKAGE_PIN M40      [get_ports "QSFP2_RX4_N"] ;# Bank 129 - MGTYRXN3_129
 set_property PACKAGE_PIN M39      [get_ports "QSFP2_RX4_P"] ;# Bank 129 - MGTYRXP3_129

 set_property PACKAGE_PIN T35      [get_ports "QSFP2_TX1_N"] ;# Bank 129 - MGTYTXN0_129
 set_property PACKAGE_PIN T34      [get_ports "QSFP2_TX1_P"] ;# Bank 129 - MGTYTXP0_129
 set_property PACKAGE_PIN R37      [get_ports "QSFP2_TX2_N"] ;# Bank 129 - MGTYTXN1_129
 set_property PACKAGE_PIN R36      [get_ports "QSFP2_TX2_P"] ;# Bank 129 - MGTYTXP1_129
 set_property PACKAGE_PIN P35      [get_ports "QSFP2_TX3_N"] ;# Bank 129 - MGTYTXN2_129
 set_property PACKAGE_PIN P34      [get_ports "QSFP2_TX3_P"] ;# Bank 129 - MGTYTXP2_129
 set_property PACKAGE_PIN N37      [get_ports "QSFP2_TX4_N"] ;# Bank 129 - MGTYTXN3_129
 set_property PACKAGE_PIN N36      [get_ports "QSFP2_TX4_P"] ;# Bank 129 - MGTYTXP3_129


set_property -dict {PACKAGE_PIN F8  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP2_INTL_LS"]    ;# 
set_property -dict {PACKAGE_PIN F9  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP2_RESETL_LS"]  ;# 
set_property -dict {PACKAGE_PIN D8  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP2_MODPRSL_LS"] ;# 
# set_property PACKAGE_PIN BK25     [get_ports "QSFP2_RECCLK_N"] ;
# set_property IOSTANDARD  LVDS     [get_ports "QSFP2_RECCLK_N"] ;
# set_property PACKAGE_PIN BJ26     [get_ports "QSFP2_RECCLK_P"] ;
# set_property IOSTANDARD  LVDS     [get_ports "QSFP2_RECCLK_P"] ;

### J76
set_property PACKAGE_PIN AB35      [get_ports "QSFP1_SI570_CLOCK_N"] ;# Bank 128 - MGTREFCLK0N_128     CLK2_N	   
set_property PACKAGE_PIN AB34      [get_ports "QSFP1_SI570_CLOCK_P"] ;# Bank 128 - MGTREFCLK0P_128      CLK2_P
set_property PACKAGE_PIN W42      [get_ports "QSFP1_RX1_N"] ;# Bank 128 - MGTYRXN0_128
set_property PACKAGE_PIN W41      [get_ports "QSFP1_RX1_P"] ;# Bank 128 - MGTYRXP0_128
set_property PACKAGE_PIN V40      [get_ports "QSFP1_RX2_N"] ;# Bank 128 - MGTYRXN1_128
set_property PACKAGE_PIN V39      [get_ports "QSFP1_RX2_P"] ;# Bank 128 - MGTYRXP1_128
set_property PACKAGE_PIN U42      [get_ports "QSFP1_RX3_N"] ;# Bank 128 - MGTYRXN2_128
set_property PACKAGE_PIN U41      [get_ports "QSFP1_RX3_P"] ;# Bank 128 - MGTYRXP2_128
set_property PACKAGE_PIN T40      [get_ports "QSFP1_RX4_N"] ;# Bank 128 - MGTYRXN3_128
set_property PACKAGE_PIN T39      [get_ports "QSFP1_RX4_P"] ;# Bank 128 - MGTYRXP3_128

set_property PACKAGE_PIN Y35      [get_ports "QSFP1_TX1_N"] ;# Bank 128 - MGTYTXN0_128
set_property PACKAGE_PIN Y34      [get_ports "QSFP1_TX1_P"] ;# Bank 128 - MGTYTXP0_128
set_property PACKAGE_PIN W37      [get_ports "QSFP1_TX2_N"] ;# Bank 128 - MGTYTXN1_128
set_property PACKAGE_PIN W36      [get_ports "QSFP1_TX2_P"] ;# Bank 128 - MGTYTXP1_128
set_property PACKAGE_PIN V35      [get_ports "QSFP1_TX3_N"] ;# Bank 128 - MGTYTXN2_128
set_property PACKAGE_PIN V34      [get_ports "QSFP1_TX3_P"] ;# Bank 128 - MGTYTXP2_128
set_property PACKAGE_PIN U37      [get_ports "QSFP1_TX4_N"] ;# Bank 128 - MGTYTXN3_128
set_property PACKAGE_PIN U36      [get_ports "QSFP1_TX4_P"] ;# Bank 128 - MGTYTXP3_128

set_property -dict {PACKAGE_PIN J8  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP1_INTL_LS"]    ;# 
set_property -dict {PACKAGE_PIN F6  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP1_RESETL_LS"]  ;# 
set_property -dict {PACKAGE_PIN J9  IOSTANDARD  LVCMOS18 }   [get_ports "QSFP1_MODPRSL_LS"] ;# 

# set_property PACKAGE_PIN BH25     [get_ports "QSFP1_RECCLK_N"] ;# 
# set_property IOSTANDARD  LVDS     [get_ports "QSFP1_RECCLK_N"] ;# 
# set_property PACKAGE_PIN BH26     [get_ports "QSFP1_RECCLK_P"] ;# 
# set_property IOSTANDARD  LVDS     [get_ports "QSFP1_RECCLK_P"] ;# 

