--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
--Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
--Date        : Wed Jan 24 11:31:28 2024
--Host        : LENOVO-P620-RoundHill running 64-bit major release  (build 9200)
--Command     : generate_target iq_240b_to_512b.bd
--Design      : iq_240b_to_512b
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity iq_240b_to_512b is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    m_axis_tready : in STD_LOGIC;
    m_axis_tvalid : out STD_LOGIC;
    overflow : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready_out   : out std_logic;
    sel_12b_16bn : in STD_LOGIC
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of iq_240b_to_512b : entity is "iq_240b_to_512b,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=iq_240b_to_512b,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=11,numReposBlks=11,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of iq_240b_to_512b : entity is "iq_240b_to_512b.hwdef";
end iq_240b_to_512b;

architecture STRUCTURE of iq_240b_to_512b is
  component iq_240b_to_512b_axis_data_fifo_0_0 is
  port (
    s_axis_aresetn : in STD_LOGIC;
    s_axis_aclk : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
  );
  end component iq_240b_to_512b_axis_data_fifo_0_0;
  component axis_demux is
    generic(
    DWIDTH : integer := 512
    );
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    aselect : in STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    m0_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
    m0_axis_tvalid : out STD_LOGIC;
    m0_axis_tready : in STD_LOGIC;
    m1_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
    m1_axis_tvalid : out STD_LOGIC;
    m1_axis_tready : in STD_LOGIC
  );
  end component axis_demux;
  component iq_240b_to_512b_xlslice_0_0 is
  port (
    Din : in STD_LOGIC_VECTOR ( 319 downto 0 );
    Dout : out STD_LOGIC_VECTOR ( 223 downto 0 )
  );
  end component iq_240b_to_512b_xlslice_0_0;
  component dig_iq_decoder is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    select_12b : in STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 239 downto 0 );
    s_axis_tvalid : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
    m_axis_tvalid : out STD_LOGIC
  );
  end component dig_iq_decoder;
  component axis_mux is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    aselect : in STD_LOGIC;
    s0_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    s0_axis_tvalid : in STD_LOGIC;
    s0_axis_tready : out STD_LOGIC;
    s1_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    s1_axis_tvalid : in STD_LOGIC;
    s1_axis_tready : out STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC
  );
  end component axis_mux;
  component iq_240b_to_512b_axis_register_slice_28B_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 223 downto 0 )
  );
  end component iq_240b_to_512b_axis_register_slice_28B_0;
  component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  end component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0;
  component iq_240b_to_512b_overflow_detect_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 );
    transfer_dropped : out STD_LOGIC
  );
  end component iq_240b_to_512b_overflow_detect_0;
  component iq_240b_to_512b_axis_register_slice_40B_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 319 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 319 downto 0 )
  );
  end component iq_240b_to_512b_axis_register_slice_40B_0;
  component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
    m_axis_tkeep : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  end component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0;
  component iq_240b_to_512b_axis_register_slice_64B_0 is
  port (
    aclk : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_tvalid : in STD_LOGIC;
    s_axis_tready : out STD_LOGIC;
    s_axis_tdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
    m_axis_tvalid : out STD_LOGIC;
    m_axis_tready : in STD_LOGIC;
    m_axis_tdata : out STD_LOGIC_VECTOR ( 511 downto 0 )
  );
  end component iq_240b_to_512b_axis_register_slice_64B_0;
  signal aclk_1 : STD_LOGIC;
  signal aresetn_1 : STD_LOGIC;
  signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
  signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
  signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
  signal axis_demux_0_m0_axis_tdata : STD_LOGIC_VECTOR ( 319 downto 0 );
  signal axis_demux_0_m0_axis_tvalid : STD_LOGIC;
  signal axis_demux_0_m1_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
  signal axis_demux_0_m1_axis_TREADY : STD_LOGIC;
  signal axis_demux_0_m1_axis_TVALID : STD_LOGIC;
  signal axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY : STD_LOGIC;
  signal axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID : STD_LOGIC;
  signal axis_dwidth_converter_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal axis_dwidth_converter_0_M_AXIS_TREADY : STD_LOGIC;
  signal axis_dwidth_converter_0_M_AXIS_TVALID : STD_LOGIC;
  signal axis_mux_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal axis_mux_0_m_axis_TREADY : STD_LOGIC;
  signal axis_mux_0_m_axis_TVALID : STD_LOGIC;
  signal axis_register_slice_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 223 downto 0 );
  signal axis_register_slice_0_M_AXIS_TREADY : STD_LOGIC;
  signal axis_register_slice_0_M_AXIS_TVALID : STD_LOGIC;
  signal axis_register_slice_0_s_axis_tready : STD_LOGIC;
  signal axis_register_slice_40B_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
  signal axis_register_slice_40B_M_AXIS_TREADY : STD_LOGIC;
  signal axis_register_slice_40B_M_AXIS_TVALID : STD_LOGIC;
  signal const_1b0_dout : STD_LOGIC;
  signal dig_iq_decoder_0_m_axis_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
  signal dig_iq_decoder_0_m_axis_TVALID : STD_LOGIC;
  signal iq_240b_to_512b_m_axis_TDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
  signal iq_240b_to_512b_m_axis_TREADY : STD_LOGIC;
  signal iq_240b_to_512b_m_axis_TVALID : STD_LOGIC;
  signal iq_240b_to_512b_overflow : STD_LOGIC;
  signal overflow_detect_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 319 downto 0 );
  signal overflow_detect_M_AXIS_TREADY : STD_LOGIC;
  signal overflow_detect_M_AXIS_TVALID : STD_LOGIC;
  signal s_axis_1_TDATA : STD_LOGIC_VECTOR ( 239 downto 0 );
  signal s_axis_1_TVALID : STD_LOGIC;
  signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 223 downto 0 );
  signal NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF s_axis:m_axis, ASSOCIATED_RESET aresetn, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0";
  attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
  attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
  attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 m_axis TREADY";
  attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis TVALID";
  attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis TVALID";
  attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis TDATA";
  attribute X_INTERFACE_PARAMETER of m_axis_tdata : signal is "XIL_INTERFACENAME m_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 1, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 64, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
  attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis TDATA";
  attribute X_INTERFACE_PARAMETER of s_axis_tdata : signal is "XIL_INTERFACENAME s_axis, CLK_DOMAIN iq_240b_to_512b_aclk, FREQ_HZ 195312500, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.0, TDATA_NUM_BYTES 30, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0";
begin
  aclk_1 <= aclk;
  aresetn_1 <= aresetn;
  const_1b0_dout <= sel_12b_16bn;
  iq_240b_to_512b_m_axis_TREADY <= m_axis_tready;
  m_axis_tdata(511 downto 0) <= iq_240b_to_512b_m_axis_TDATA(511 downto 0);
  m_axis_tvalid <= iq_240b_to_512b_m_axis_TVALID;
  overflow <= iq_240b_to_512b_overflow;
  s_axis_1_TDATA(239 downto 0) <= s_axis_tdata(239 downto 0);
  s_axis_1_TVALID <= s_axis_tvalid;
  
  s_axis_tready_out  <= axis_data_fifo_0_M_AXIS_TREADY;
  
axis_data_fifo_0: component iq_240b_to_512b_axis_data_fifo_0_0
     port map (
      m_axis_tdata(319 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
      m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
      m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
      s_axis_aclk => aclk_1,
      s_axis_aresetn => aresetn_1,
      s_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
      s_axis_tready => overflow_detect_M_AXIS_TREADY,
      s_axis_tvalid => overflow_detect_M_AXIS_TVALID
    );
axis_demux_16b_12b_iq: component axis_demux
     generic map (
       DWIDTH    => 320
     )
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      aselect => const_1b0_dout,
      m0_axis_tdata => axis_demux_0_m0_axis_tdata(319 downto 0),
      m0_axis_tready => axis_register_slice_0_s_axis_tready,
      m0_axis_tvalid => axis_demux_0_m0_axis_tvalid,
      m1_axis_tdata => axis_demux_0_m1_axis_TDATA(319 downto 0),
      m1_axis_tready => axis_demux_0_m1_axis_TREADY,
      m1_axis_tvalid => axis_demux_0_m1_axis_TVALID,
      s_axis_tdata => axis_data_fifo_0_M_AXIS_TDATA(319 downto 0),
      s_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
      s_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID
    );
axis_dwidth_conv_28B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_28B_to_64B_0
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      m_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
      m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_28B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
      m_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
      m_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
      s_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
      s_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
      s_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID
    );
axis_dwidth_conv_40B_to_64B: component iq_240b_to_512b_axis_dwidth_conv_40B_to_64B_0
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      m_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
      m_axis_tkeep(63 downto 0) => NLW_axis_dwidth_conv_40B_to_64B_m_axis_tkeep_UNCONNECTED(63 downto 0),
      m_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
      m_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID,
      s_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
      s_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
      s_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID
    );
axis_mux_16b_12b_iq: component axis_mux
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      aselect => const_1b0_dout,
      m_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
      m_axis_tready => axis_mux_0_m_axis_TREADY,
      m_axis_tvalid => axis_mux_0_m_axis_TVALID,
      s0_axis_tdata(511 downto 0) => axis_dwidth_converter_0_M_AXIS_TDATA(511 downto 0),
      s0_axis_tready => axis_dwidth_converter_0_M_AXIS_TREADY,
      s0_axis_tvalid => axis_dwidth_converter_0_M_AXIS_TVALID,
      s1_axis_tdata(511 downto 0) => axis_dwidth_conv_40B_to_64B_M_AXIS_TDATA(511 downto 0),
      s1_axis_tready => axis_dwidth_conv_40B_to_64B_M_AXIS_TREADY,
      s1_axis_tvalid => axis_dwidth_conv_40B_to_64B_M_AXIS_TVALID
    );
axis_register_slice_28B: component iq_240b_to_512b_axis_register_slice_28B_0
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      m_axis_tdata(223 downto 0) => axis_register_slice_0_M_AXIS_TDATA(223 downto 0),
      m_axis_tready => axis_register_slice_0_M_AXIS_TREADY,
      m_axis_tvalid => axis_register_slice_0_M_AXIS_TVALID,
      s_axis_tdata(223 downto 0) => xlslice_0_Dout(223 downto 0),
      s_axis_tready => axis_register_slice_0_s_axis_tready,
      s_axis_tvalid => axis_demux_0_m0_axis_tvalid
    );
axis_register_slice_40B: component iq_240b_to_512b_axis_register_slice_40B_0
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      m_axis_tdata(319 downto 0) => axis_register_slice_40B_M_AXIS_TDATA(319 downto 0),
      m_axis_tready => axis_register_slice_40B_M_AXIS_TREADY,
      m_axis_tvalid => axis_register_slice_40B_M_AXIS_TVALID,
      s_axis_tdata(319 downto 0) => axis_demux_0_m1_axis_TDATA(319 downto 0),
      s_axis_tready => axis_demux_0_m1_axis_TREADY,
      s_axis_tvalid => axis_demux_0_m1_axis_TVALID
    );
axis_register_slice_64B: component iq_240b_to_512b_axis_register_slice_64B_0
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      m_axis_tdata(511 downto 0) => iq_240b_to_512b_m_axis_TDATA(511 downto 0),
      m_axis_tready => iq_240b_to_512b_m_axis_TREADY,
      m_axis_tvalid => iq_240b_to_512b_m_axis_TVALID,
      s_axis_tdata(511 downto 0) => axis_mux_0_m_axis_TDATA(511 downto 0),
      s_axis_tready => axis_mux_0_m_axis_TREADY,
      s_axis_tvalid => axis_mux_0_m_axis_TVALID
    );
iq_decoder_12b_16b: component dig_iq_decoder
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      m_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
      m_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
      s_axis_tdata(239 downto 0) => s_axis_1_TDATA(239 downto 0),
      s_axis_tvalid => s_axis_1_TVALID,
      select_12b => const_1b0_dout
    );
overflow_detect: component iq_240b_to_512b_overflow_detect_0
     port map (
      aclk => aclk_1,
      aresetn => aresetn_1,
      m_axis_tdata(319 downto 0) => overflow_detect_M_AXIS_TDATA(319 downto 0),
      m_axis_tready => overflow_detect_M_AXIS_TREADY,
      m_axis_tvalid => overflow_detect_M_AXIS_TVALID,
      s_axis_tdata(319 downto 0) => dig_iq_decoder_0_m_axis_TDATA(319 downto 0),
      s_axis_tvalid => dig_iq_decoder_0_m_axis_TVALID,
      transfer_dropped => iq_240b_to_512b_overflow
    );
xlslice_0: component iq_240b_to_512b_xlslice_0_0
     port map (
      Din(319 downto 0) => axis_demux_0_m0_axis_tdata(319 downto 0),
      Dout(223 downto 0) => xlslice_0_Dout(223 downto 0)
    );
end STRUCTURE;
