47 lines
1.4 KiB
VHDL
47 lines
1.4 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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Library xpm;
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use xpm.vcomponents.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity axis_demux_128b is
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port (
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aselect : in std_logic;
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s_axis_tdata : in std_logic_vector(127 downto 0);
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s_axis_tvalid : in std_logic;
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s_axis_tready : out std_logic;
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m0_axis_tdata : out std_logic_vector(127 downto 0);
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m0_axis_tvalid : out std_logic;
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m0_axis_tready : in std_logic;
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m1_axis_tdata : out std_logic_vector(127 downto 0);
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m1_axis_tvalid : out std_logic;
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m1_axis_tready : in std_logic
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);
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end entity axis_demux_128b;
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architecture imp of axis_demux_128b is
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begin
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m0_axis_tdata <= s_axis_tdata;
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m0_axis_tvalid <= s_axis_tvalid when aselect = '0' else '0';
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m1_axis_tdata <= s_axis_tdata;
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m1_axis_tvalid <= s_axis_tvalid when aselect = '1' else '0';
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s_axis_tready <= m0_axis_tready when aselect = '0' else m1_axis_tready;
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end imp;
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