library IEEE; use IEEE.STD_LOGIC_1164.ALL; Library xpm; use xpm.vcomponents.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity axis_mux_128b is port ( aclk : in STD_LOGIC; aresetn : in std_logic; aselect : in std_logic_vector(1 downto 0); s0_axis_tdata : in std_logic_vector(127 downto 0); s0_axis_tvalid : in std_logic; s0_axis_tready : out std_logic; s1_axis_tdata : in std_logic_vector(127 downto 0); s1_axis_tvalid : in std_logic; s1_axis_tready : out std_logic; s2_axis_tdata : in std_logic_vector(127 downto 0); s2_axis_tvalid : in std_logic; s2_axis_tready : out std_logic; s3_axis_tdata : in std_logic_vector(127 downto 0); s3_axis_tvalid : in std_logic; s3_axis_tready : out std_logic; m_axis_tdata : out std_logic_vector(127 downto 0); m_axis_tvalid : out std_logic; m_axis_tready : in std_logic ); end entity axis_mux_128b; architecture imp of axis_mux_128b is begin m_axis_tdata <= s0_axis_tdata when aselect = "00" else s1_axis_tdata when aselect = "01" else s2_axis_tdata when aselect = "10" else s3_axis_tdata; m_axis_tvalid <= s0_axis_tvalid when aselect = "00" else s1_axis_tvalid when aselect = "01" else s2_axis_tvalid when aselect = "10" else s3_axis_tvalid; s0_axis_tready <= m_axis_tready when aselect = "00" else '0'; s1_axis_tready <= m_axis_tready when aselect = "01" else '0'; s2_axis_tready <= m_axis_tready when aselect = "10" else '0'; s3_axis_tready <= m_axis_tready when aselect = "11" else '0'; end imp;