library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity axis_demux_128b is
  port ( 
    aselect                     : in  std_logic;

    s_axis_tdata                : in  std_logic_vector(127 downto 0);
    s_axis_tvalid               : in  std_logic;
    s_axis_tready               : out std_logic;

    m0_axis_tdata               : out std_logic_vector(127 downto 0);
    m0_axis_tvalid              : out std_logic;
    m0_axis_tready              : in  std_logic;

    m1_axis_tdata               : out std_logic_vector(127 downto 0);
    m1_axis_tvalid              : out std_logic;
    m1_axis_tready              : in  std_logic
    );
end entity axis_demux_128b;

architecture imp of axis_demux_128b is

begin
     
  m0_axis_tdata    <= s_axis_tdata;
  m0_axis_tvalid   <= s_axis_tvalid  when aselect = '0' else '0';

  m1_axis_tdata    <= s_axis_tdata; 
  m1_axis_tvalid   <= s_axis_tvalid  when aselect = '1' else '0';
    
  s_axis_tready    <= m0_axis_tready when aselect = '0' else m1_axis_tready;

end imp;