--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:53:22 03/24/2017
-- Design Name:   
-- Module Name:   
-- Project Name:  xem7350
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: dac_interface
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
entity test_bench is
end test_bench;
 
architecture behavior of test_bench is 
 
  constant C_M_AXI_DATA_WIDTH             : integer := 32;
  constant C_M_AXI_ADDR_WIDTH             : integer := 32;

   -- Clock period definitions
  constant CLK_125_PERIOD           : time := 8 ns;    -- 125 MHz
  constant CLK_250_PERIOD           : time := 4 ns;    -- 250 MHz        
  constant S_AXI_ACLK_PERIOD        : time := 10 ns;   -- 100 MHz
  constant M_AXI_ACLK_PERIOD        : time := 4 ns;    -- 250 MHz       2.58 ns;  -- 387 MHz    
  constant QSFP4_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     
  constant QSFP1_AXIS_ACLK_PERIOD   : time := 5.12 ns;    -- 195.310 MHz       5.12 ns;     

  signal clk_125                    : std_logic :=  '0';
  signal clk_125_aresetn            : std_logic_vector(0 to 15) := (others => '0');
  signal clk_125_reset              : std_logic;
  
  signal clk_250                    : std_logic :=  '0';
  signal clk_250_aresetn            : std_logic_vector(0 to 15) := (others => '0');
  signal clk_250_areset             : std_logic;

  signal tx_device_clk_1            : std_logic :=  '0';
  signal tx_device_clk_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
  signal tx_device_clk_aresetn      : std_logic;

  signal rx_device_clk_1            : std_logic :=  '0';
  signal rx_device_clk_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
  signal rx_device_clk_aresetn      : std_logic;
  signal rx_device_clk_areset       : std_logic;

  signal qsfp4_axis_aclk            : std_logic :=  '0';
  signal qsfp4_axis_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
  signal qsfp4_axis_aresetn      : std_logic;

  signal qsfp1_axis_aclk            : std_logic :=  '0';
  signal qsfp1_axis_aresetn_r    : std_logic_vector(0 to 15) := (others => '0');
  signal qsfp1_axis_aresetn      : std_logic;

  
--
  signal tick_1ms                         : std_logic;

  signal clk_125_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
  signal clk_125_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
  signal clk_125_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');

  signal clk_250_tick_1ms_r               : std_logic_vector(0 to 2) := (others => '0');
  signal clk_250_freq_r                   : std_logic_vector(31 downto 0) := (others => '0');
  signal clk_250_cnt_r                    : std_logic_vector(31 downto 0) := (others => '0');

  
  
begin
 
  clk_125  <= not clk_125 after CLK_125_PERIOD/2;
  clk_250  <= not clk_250 after CLK_250_PERIOD/2; 
  tx_device_clk_1  <= not tx_device_clk_1 after CLK_250_PERIOD/2; 
  rx_device_clk_1  <= not rx_device_clk_1 after CLK_250_PERIOD/2; 

  qsfp4_axis_aclk  <= not qsfp4_axis_aclk after QSFP4_AXIS_ACLK_PERIOD/2; 
  qsfp1_axis_aclk  <= not qsfp1_axis_aclk after QSFP1_AXIS_ACLK_PERIOD/2; 

--
  process(clk_125)
  begin
    if (rising_edge(clk_125)) then
      clk_125_aresetn     <= clk_125_aresetn(1 to 15) & '1';
    end if;
  end process;

  process(clk_125)
  begin
    if (rising_edge(clk_125)) then
      clk_125_aresetn     <= clk_125_aresetn(1 to 15) & '1';
    end if;
  end process;
  
  clk_125_reset  <= not clk_125_aresetn(0);
--  
  process(clk_250)
  begin
    if (rising_edge(clk_250)) then
      clk_250_aresetn     <= clk_250_aresetn(1 to 15) & '1';
    end if;
  end process;
  
  clk_250_areset  <= not clk_250_aresetn(0);
--
  process(tx_device_clk_1)
  begin
    if (rising_edge(tx_device_clk_1)) then
      tx_device_clk_aresetn_r     <= tx_device_clk_aresetn_r(1 to 15) & '1';
    end if;
  end process;

  tx_device_clk_aresetn  <= tx_device_clk_aresetn_r(0);


------------------------------------------------
  i_tick_gen : entity work.tick_gen
    generic map (
      CLOCK_SPEED_MHZ                       => 125
      ) 
    port map (
      clk_in                                => clk_125,

      tick_1us_out                          => open,
      tick_1ms_out                          => tick_1ms,
      tick_500ms_out                        => open,
      tick_750ms_out                        => open,
      tick_1s_out                           => open,

      prog_us_tick_rate_in                  => x"0000_0000",
      prog_us_tick_out                      => open,  

      reset_in                              => clk_125_reset   
      );


  process(clk_125)
  begin
    if (rising_edge(clk_125)) then
      clk_125_tick_1ms_r      <= clk_125_tick_1ms_r(1 to 2) & tick_1ms;
      if (clk_125_tick_1ms_r(0 to 1) = "01") then 
        clk_125_freq_r        <= clk_125_cnt_r;
        clk_125_cnt_r         <= (others => '0');
      else
        clk_125_cnt_r         <= clk_125_cnt_r + 1;
      end if;
    end if;
  end process;

  process(clk_250)
  begin
    if (rising_edge(clk_250)) then
      clk_250_tick_1ms_r      <= clk_250_tick_1ms_r(1 to 2) & tick_1ms;
      if (clk_250_tick_1ms_r(0 to 1) = "01") then 
        clk_250_freq_r        <= clk_250_cnt_r;
        clk_250_cnt_r         <= (others => '0');
      else
        clk_250_cnt_r         <= clk_250_cnt_r + 1;
      end if;
    end if;
  end process;


  

end;