-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:53:22 03/24/2017 -- Design Name: -- Module Name: -- Project Name: xem7350 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: dac_interface -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; entity tb_cap_plybk is end tb_cap_plybk; architecture behavior of tb_cap_plybk is constant C_M_AXI_DATA_WIDTH : integer := 32; constant C_M_AXI_ADDR_WIDTH : integer := 32; -- Clock period definitions constant CLK_125_PERIOD : time := 8 ns; -- 125 MHz constant CLK_250_PERIOD : time := 4 ns; -- 250 MHz constant S_AXI_ACLK_PERIOD : time := 10 ns; -- 100 MHz constant M_AXI_ACLK_PERIOD : time := 4 ns; -- 250 MHz 2.58 ns; -- 387 MHz constant QSFP4_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; constant QSFP1_AXIS_ACLK_PERIOD : time := 5.12 ns; -- 195.310 MHz 5.12 ns; signal clk_125 : std_logic := '0'; signal clk_125_aresetn : std_logic_vector(0 to 15) := (others => '0'); signal clk_125_reset : std_logic; signal clk_250 : std_logic := '0'; signal clk_250_aresetn : std_logic_vector(0 to 15) := (others => '0'); signal clk_250_areset : std_logic; signal tx_device_clk_1 : std_logic := '0'; signal tx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); signal tx_device_clk_aresetn : std_logic; signal rx_device_clk_1 : std_logic := '0'; signal rx_device_clk_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); signal rx_device_clk_aresetn : std_logic; signal rx_device_clk_areset : std_logic; signal qsfp4_playback_aclk : std_logic := '0'; signal qsfp4_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); signal qsfp4_playback_aresetn : std_logic; signal qsfp1_capture_aclk : std_logic; signal qsfp1_axis_aresetn_r : std_logic_vector(0 to 15) := (others => '0'); signal qsfp1_capture_aresetn : std_logic; -- signal tick_1ms : std_logic; signal clk_125_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); signal clk_125_freq_r : std_logic_vector(31 downto 0) := (others => '0'); signal clk_125_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); signal clk_250_tick_1ms_r : std_logic_vector(0 to 2) := (others => '0'); signal clk_250_freq_r : std_logic_vector(31 downto 0) := (others => '0'); signal clk_250_cnt_r : std_logic_vector(31 downto 0) := (others => '0'); signal adc_rx_tdata_128b : std_logic_vector(127 downto 0) := (others => '0'); signal adc_rx_tvalid_128b : std_logic := '0'; signal adc_rx_tready_128b : std_logic; signal adc_rx_tvalid_128b_cnt : std_logic_vector(31 downto 0); signal qsfp4_playback_tdata_240b : std_logic_vector(239 downto 0); signal qsfp4_playback_tvalid_240b : std_logic; signal qsfp4_playback_tready_240b : std_logic := '1'; signal qsfp1_capture_tdata_240b : std_logic_vector(239 downto 0); signal qsfp1_capture_tvalid_240b : std_logic; signal tx_tdata_128b : std_logic_vector(127 downto 0); signal tx_tvalid_128b : std_logic; signal tx_tready_128b : std_logic := '1'; signal qsfp1_capture_rx_data_ready : std_logic; signal playback_data_path_enable_n : std_logic := '1'; signal adc_rx_tvalid_128b_ena : std_logic; begin clk_125 <= not clk_125 after CLK_125_PERIOD/2; clk_250 <= not clk_250 after CLK_250_PERIOD/2; tx_device_clk_1 <= not tx_device_clk_1 after CLK_250_PERIOD/2; rx_device_clk_1 <= not rx_device_clk_1 after CLK_250_PERIOD/2; qsfp4_playback_aclk <= not qsfp4_playback_aclk after QSFP4_AXIS_ACLK_PERIOD/2; -- qsfp1_capture_aclk <= not qsfp1_capture_aclk after QSFP1_AXIS_ACLK_PERIOD/2; -- process(clk_125) begin if (rising_edge(clk_125)) then clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; end if; end process; process(clk_125) begin if (rising_edge(clk_125)) then clk_125_aresetn <= clk_125_aresetn(1 to 15) & '1'; end if; end process; clk_125_reset <= not clk_125_aresetn(0); -- process(clk_250) begin if (rising_edge(clk_250)) then clk_250_aresetn <= clk_250_aresetn(1 to 15) & '1'; end if; end process; clk_250_areset <= not clk_250_aresetn(0); -- process(tx_device_clk_1) begin if (rising_edge(tx_device_clk_1)) then tx_device_clk_aresetn_r <= tx_device_clk_aresetn_r(1 to 15) & '1'; end if; end process; tx_device_clk_aresetn <= tx_device_clk_aresetn_r(0); -- process(rx_device_clk_1) begin if (rising_edge(rx_device_clk_1)) then rx_device_clk_aresetn_r <= rx_device_clk_aresetn_r(1 to 15) & '1'; end if; end process; rx_device_clk_aresetn <= rx_device_clk_aresetn_r(0); -- process(qsfp4_playback_aclk) begin if (rising_edge(qsfp4_playback_aclk)) then qsfp4_axis_aresetn_r <= qsfp4_axis_aresetn_r(1 to 15) & '1'; end if; end process; qsfp4_playback_aresetn <= qsfp4_axis_aresetn_r(0); -- process(rx_device_clk_1) begin if (rising_edge(rx_device_clk_1)) then adc_rx_tdata_128b <= adc_rx_tdata_128b + x"0003_0002_0001_0004_0005_0006_0007_0008"; end if; end process; -- process(qsfp1_capture_aclk) begin if (rising_edge(qsfp1_capture_aclk)) then qsfp1_axis_aresetn_r <= qsfp1_axis_aresetn_r(1 to 15) & '1'; end if; end process; qsfp1_capture_aresetn <= qsfp1_axis_aresetn_r(0); adc_rx_tvalid_128b_ena <= adc_rx_tvalid_128b and qsfp1_capture_rx_data_ready; i_qsfp4_playback_intfc : entity work.qsfp4_playback_intfc port map ( rx_device_clk_in => rx_device_clk_1, rx_device_clk_aresetn_in => rx_device_clk_aresetn, rx_tdata_128b_in => adc_rx_tdata_128b, rx_tvalid_128b_in => adc_rx_tvalid_128b_ena, rx_tready_128b_out => adc_rx_tready_128b, rx_tvalid_128b_cnt_out => adc_rx_tvalid_128b_cnt, rx_tvalid_128b_en_cnt_out => open, playback_data_path_enable_n_in => playback_data_path_enable_n, qsfp4_playback_aclk_in => qsfp4_playback_aclk, qsfp4_playback_aresetn_in => qsfp4_playback_aresetn, qsfp4_playback_tdata_240b_out => qsfp4_playback_tdata_240b, qsfp4_playback_tvalid_240b_out => qsfp4_playback_tvalid_240b, qsfp4_playback_tready_240b_in => qsfp4_playback_tready_240b, qsfp4_playback_tvalid_240b_cnt_out => open, cnt_reset_in => '0' ); --/////////////////////////////// qsfp1_capture_aclk <= qsfp4_playback_aclk; -- qsfp1_capture_tdata_240b <= qsfp4_playback_tdata_240b; -- qsfp1_capture_tvalid_240b <= qsfp4_playback_tvalid_240b; -- --/////////////////////////////// --// ****>>>> FROM QSFP1 CAPTURE INTERFACE i_qsfp1_capture_intfc : entity work.qsfp1_capture_intfc port map ( qsfp1_capture_aclk_in => qsfp1_capture_aclk, qsfp1_capture_aresetn_in => qsfp1_capture_aresetn, qsfp1_capture_tdata_240b_in => qsfp1_capture_tdata_240b, qsfp1_capture_tvalid_240b_in => qsfp1_capture_tvalid_240b, qsfp1_capture_tvalid_240b_cnt_out => open, qsfp1_capture_fifo_aempty_512b_cnt_out => open, qsfp1_capture_iq_240b_to_512b_overflow_cnt_out => open, qsfp1_capture_rx_data_ready_out => qsfp1_capture_rx_data_ready, qsfp1_capture_rx_data_ready_cnt_out => open, tx_device_clk_in => tx_device_clk_1, tx_device_clk_aresetn_in => tx_device_clk_aresetn, tx_tdata_128b_out => tx_tdata_128b, -- out tx_tvalid_128b_out => tx_tvalid_128b, -- out tx_tready_128b_in => tx_tready_128b, -- in tx_tvalid_128b_cnt_out => open, cnt_reset_in => '0' ); -- Stimulus process stim_proc: process begin wait until rx_device_clk_aresetn = '1'; wait for 200 ns; wait until rising_edge(rx_device_clk_1); adc_rx_tvalid_128b <= '1'; wait for 500 ns; wait until rising_edge(rx_device_clk_1); playback_data_path_enable_n <= '0'; wait for 5 us; wait until rising_edge(qsfp4_playback_aclk); playback_data_path_enable_n <='0'; wait for 5 us; wait until rising_edge(qsfp4_playback_aclk); qsfp4_playback_tready_240b <='1'; wait; -- wait here forever end process; end;