user.org
user
qsfp_intfc
1.0
S00_AXI
AWADDR
s00_axi_awaddr
AWPROT
s00_axi_awprot
AWVALID
s00_axi_awvalid
AWREADY
s00_axi_awready
WDATA
s00_axi_wdata
WSTRB
s00_axi_wstrb
WVALID
s00_axi_wvalid
WREADY
s00_axi_wready
BRESP
s00_axi_bresp
BVALID
s00_axi_bvalid
BREADY
s00_axi_bready
ARADDR
s00_axi_araddr
ARPROT
s00_axi_arprot
ARVALID
s00_axi_arvalid
ARREADY
s00_axi_arready
RDATA
s00_axi_rdata
RRESP
s00_axi_rresp
RVALID
s00_axi_rvalid
RREADY
s00_axi_rready
WIZ_DATA_WIDTH
32
WIZ_NUM_REG
32
SUPPORTS_NARROW_BURST
0
S00_AXI_RST
RST
s00_axi_aresetn
POLARITY
ACTIVE_LOW
S00_AXI_CLK
CLK
s00_axi_aclk
ASSOCIATED_BUSIF
S00_AXI
ASSOCIATED_RESET
s00_axi_aresetn
FREQ_HZ
100 MHz
S00_AXI
S00_AXI_reg
0
4096
32
register
OFFSET_BASE_PARAM
C_S00_AXI_BASEADDR
OFFSET_HIGH_PARAM
C_S00_AXI_HIGHADDR
xilinx_softwaredriver
Software Driver
:vivado.xilinx.com:sw.driver
xilinx_softwaredriver_view_fileset
viewChecksum
a826d92e
xilinx_xpgui
UI Layout
:vivado.xilinx.com:xgui.ui
xilinx_xpgui_view_fileset
viewChecksum
300e9af8
bd_tcl
Block Diagram
:vivado.xilinx.com:block.diagram
bd_tcl_view_fileset
viewChecksum
45a2f450
xilinx_anylanguagesynthesis
Synthesis
:vivado.xilinx.com:synthesis
qsfp_intfc_v1_0
xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset
xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset
xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset
xilinx_anylanguagesynthesis_view_fileset
viewChecksum
d5e858a3
xilinx_anylanguagebehavioralsimulation
Simulation
:vivado.xilinx.com:simulation
qsfp_intfc_v1_0
xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
viewChecksum
96fd02a1
clk_125_in
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
clk_125_reset_n_in
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
clk_250_in
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
clk_250_reset_n_in
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
clk_100_in
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
clk_100_reset_in
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_SI570_CLOCK_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_SI570_CLOCK_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX1_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX1_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX1_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX1_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX2_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX2_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX2_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX2_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX3_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX3_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX3_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX3_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX4_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_TX4_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX4_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RX4_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_RESETL_LS
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_MODPRSL_LS
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP1_INTL_LS
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_SI570_CLOCK_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_SI570_CLOCK_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX1_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX1_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX1_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX1_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX2_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX2_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX2_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX2_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX3_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX3_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX3_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX3_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX4_P
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_TX4_N
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX4_P
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RX4_N
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_RESETL_LS
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_MODPRSL_LS
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
QSFP4_INTL_LS
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_awaddr
in
6
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_awprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_awvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_awready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_wdata
in
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_wstrb
in
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_wvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_wready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_bresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_bvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_bready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_araddr
in
6
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_arprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_arvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_arready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_rdata
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_rresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_rvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s00_axi_rready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
C_S00_AXI_DATA_WIDTH
C S00 AXI DATA WIDTH
Width of S_AXI data bus
32
C_S00_AXI_ADDR_WIDTH
C S00 AXI ADDR WIDTH
Width of S_AXI address bus
7
FPGA_REVISION_DATE
Fpga Revision Date
0x06032024
MINOR_REV
Minor Rev
"00000001"
choice_list_6fc15197
32
choice_list_9d8b0d81
ACTIVE_HIGH
ACTIVE_LOW
choice_pairs_ce1226b1
1
0
xilinx_softwaredriver_view_fileset
drivers/qsfp_intfc_v1_0/data/qsfp_intfc.mdd
mdd
driver_mdd
drivers/qsfp_intfc_v1_0/data/qsfp_intfc.tcl
tclSource
driver_tcl
drivers/qsfp_intfc_v1_0/src/Makefile
driver_src
drivers/qsfp_intfc_v1_0/src/qsfp_intfc.h
cSource
driver_src
drivers/qsfp_intfc_v1_0/src/qsfp_intfc.c
cSource
driver_src
drivers/qsfp_intfc_v1_0/src/qsfp_intfc_selftest.c
cSource
driver_src
xilinx_xpgui_view_fileset
xgui/qsfp_intfc_v1_0.tcl
tclSource
CHECKSUM_300e9af8
XGUI_VERSION_2
bd_tcl_view_fileset
bd/bd.tcl
tclSource
xilinx_anylanguagesynthesis_view_fileset
src/vio_2_1/vio_2_1.xci
xci
CELL_NAME_i_vio_2
src/axis_data_fifo_1kx240_1/axis_data_fifo_1kx240_1.xci
xci
CELL_NAME_i_qsfp0_to_qsfp1_fifo
src/ila_3/ila_3.xci
xci
CELL_NAME_i_ila_0
src/vio_0_1/vio_0_1.xci
xci
CELL_NAME_i_vio_0
hdl/qsfp_intfc_v1_0_S00_AXI.vhd
vhdlSource
src/dig_iq_p_intfc.vhd
vhdlSource
src/dig_iq_x2.vhd
vhdlSource
src/tick_gen.vhd
vhdlSource
hdl/qsfp_intfc_v1_0.vhd
vhdlSource
CHECKSUM_c464279f
xilinx_anylanguagesynthesis_xilinx_com_ip_vio_3_0__ref_view_fileset
xilinx_anylanguagesynthesis_xilinx_com_ip_ila_6_2__ref_view_fileset
xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
src/vio_0_1/vio_0_1.xci
xci
CELL_NAME_i_vio_0
src/ila_3/ila_3.xci
xci
CELL_NAME_i_ila_0
src/axis_data_fifo_1kx240_1/axis_data_fifo_1kx240_1.xci
xci
CELL_NAME_i_qsfp0_to_qsfp1_fifo
src/vio_2_1/vio_2_1.xci
xci
CELL_NAME_i_vio_2
hdl/qsfp_intfc_v1_0_S00_AXI.vhd
vhdlSource
src/dig_iq_p_intfc.vhd
vhdlSource
src/dig_iq_x2.vhd
vhdlSource
src/tick_gen.vhd
vhdlSource
hdl/qsfp_intfc_v1_0.vhd
vhdlSource
xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_vio_3_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_ila_6_2__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset
QSFP AXI IP
C_S00_AXI_DATA_WIDTH
C S00 AXI DATA WIDTH
Width of S_AXI data bus
32
false
C_S00_AXI_ADDR_WIDTH
C S00 AXI ADDR WIDTH
Width of S_AXI address bus
7
false
C_S00_AXI_BASEADDR
C S00 AXI BASEADDR
0xFFFFFFFF
false
C_S00_AXI_HIGHADDR
C S00 AXI HIGHADDR
0x00000000
false
Component_Name
qsfp_intfc_v1_0
FPGA_REVISION_DATE
Fpga Revision Date
0x06032024
MINOR_REV
Minor Rev
"00000001"
virtexuplusHBM
AXI_Peripheral
qsfp_intfc_v1.0
XPM_CDC
XPM_FIFO
5
2024-06-06T16:37:12Z
2023.2